[paper] SEMIDV Device Simulator with Quantum Effects

Chien-Ting Tung

SEMIDV: A Compact Semiconductor Device Simulator with Quantum Effects

ArXiv preprint arXiv:2504.00214 (2025)

Abstract: In this paper, I present SEMIDV – a compact semiconductor device simulator incorporating quantum effects. SEMIDV solves the Poisson-Drift-Diffusion equations for semiconductor devices and provides a user-friendly Python interface for scripting and data analysis. Localization landscape theory is introduced to provide quantum corrections to the Drift- Diffusion equation. This theory directly solves the ground state of the Schrödinger equation without further approximation, offering an efficient solution for quantum effect modeling. Additionally, a compact mobility model considering ballistic transport is developed to capture the ballistic length dependence of mobility and the velocity overshoot effect in short-channel devices. Finally, a study on a nanosheet FET using SEMIDV is conducted. I analyze the electrical characteristics of a state-of- the-art GAA/RibbonFET with a 6 nm gate length and discuss the effects of velocity overshoot and quantum confinement on currents and capacitances. A design for an ultra-short-channel transistor with a gate length down to 4.5 nm with a Vdd = 0.45 V is proposed to push the boundaries of integrated circuit technology further.

FIG: Silicon 6nm RibbonFET CMOS structure for SIMIDV calibration 

[Session] Improving Chip Design Enablement for Universities in Europe

DATE2025 FS06 Focus Session:

Improving Chip Design Enablement for Universities in Europe

Date: Tuesday, 01 April 2025

Time: 11:00 CEST - 12:30 CEST

Location / Room: Rhône 1

Session chair:
Ulf Schlichtmann, TU Munich, DE

Session co-chair:
Holger Blume, Leibniz University Hannover, DE

Organisers:
Norbert Wehn, University of Kaiserslautern-Landau, DE
Lukas Krupp, University of Kaiserslautern-Landau, DE

Time	Label	Presentation Title Authors
11:00 CEST	FS06.1	PANEL: IMPROVING CHIP DESIGN ENABLEMENT FOR UNIVERSITIES IN EUROPE Speaker : Norbert Wehn, RPTU University of Kaiserslautern-Landau, DE Authors : Matthew Venn 1 , Joachim Rodrigues 2 , David Atienza 3 , Ian O'Connor 4 , Andreas Brüning 5  and Patrick Haspel 6 1 Tiny Tapeout, ES;  2 Lund University, SE;  3 EPFL, CH;  4 Lyon Institute of Nanotechnology, FR;  5 FMD, DE;  6 Synopsys, DE Abstract The semiconductor industry is central to the European economy, particularly in the industrial and automotive sectors. Semiconductor fabrication and chip design are the two largest segments of the microelectronics value chain. While Europe is strengthening semiconductor fabrication and technology with considerable investments, e.g., in new fabs, chip design capabilities fall far short of the required capacities. The EU MicroElectronics Training, Industry and Skills (METIS) Report 2023 has shown that chip designers are the job profiles identified as the most difficult to find in the European microelectronics industry. European universities face many challenges hindering their ability to produce skilled graduates and contribute to the semiconductor ecosystem. While student interest in, e.g., AI is booming, we observe a decreasing interest in microelectronics. The main reasons for this are the high entry barriers for students, reinforced by the lack of chip design enablement in academia. Hence, there are ongoing initiatives in different European countries, on the EU level, and worldwide to strengthen chip design education and research. This focus session will bring together stakeholders of these initiatives from Europe and the USA to explore the critical challenges, opportunities, and potential strategies facing chip design enablement in European academic institutions. The session will be held in the panel format with active audience participation to guarantee inclusiveness and foster a broad view of the topic.