2017 1st Electron Devices Technology and Manufacturing Conference (call for #papers) https://t.co/CAj9B5ifWU

2017 1st Electron Devices Technology and Manufacturing Conference (call for #papers) https://t.co/CAj9B5ifWU

— Wladek Grabinski (@wladek60) October 27, 2016

from Twitter https://twitter.com/wladek60

October 27, 2016 at 05:08PM
via IFTTT

AMS Multi Project Wafer Service

AMS MPW Service:

ams' Multi Project Wafer (MPW) service, also known as shuttle runs, is a fast and cost-efficient prototyping service, which combines several designs from different customers onto a single wafer.

ams’ best in class MPW service offers significant cost advantages for foundry customers as the costs for wafers and masks are shared among a number of different shuttle participants. It includes the whole range of 0.18µm and 0.35µm specialty processes:

• CMOS Mixed Signal
• CMOS Mixed Signal with embedded EEPROM
• CMOS High Voltage (up to 120 Volts)
• CMOS High Voltage with embedded EEPROM
• CMOS Opto
• SiGe-BiCMOS

The complete MPW schedule including detailed start dates per process is available on the web at http://asic.ams.com/MPW

Deliverables: Participating the ams MPW service includes the delivery of 40 prototypes for design verification. Packaged engineering samples are offered within 2 days (ceramic) and 3 weeks (plastics) cycle time, respectively. The total turnaround time from MPW deadline to delivery is app. 8 weeks (CMOS). Overall, ams offers almost 150 MPW start dates in 2016 and 2017, enabled by long lasting co-operations with partner organizations such as CMP, Europractice, Fraunhofer IIS and Mosis. Customers located in APAC region may also participate via our local MPW program partners Toppan Technical Design Center Co., Ltd (TDC) and MEDs Technologies [read more...]

ARM Fellow Surveys Moore's Law at 3nm IC https://t.co/JUPsAtrkFb #papers

ARM Fellow Surveys Moore's Law at 3nm IC https://t.co/JUPsAtrkFb #papers

— Wladek Grabinski (@wladek60) October 27, 2016

from Twitter https://twitter.com/wladek60

October 27, 2016 at 10:43AM
via IFTTT

[JEDS #papers ] Characterization of RF Noise in UTBB FD-SOI MOSFET https://t.co/LNlvvNOb5V https://t.co/XQsatKslTX

[JEDS #papers ] Characterization of RF Noise in UTBB FD-SOI MOSFET https://t.co/LNlvvNOb5V https://t.co/XQsatKslTX

— Wladek Grabinski (@wladek60) October 26, 2016

from Twitter https://twitter.com/wladek60

October 26, 2016 at 05:03PM
via IFTTT

[JEDS #papers ] Characterization of RF Noise in UTBB FD-SOI MOSFET https://t.co/LNlvvNOb5V

[JEDS #papers ] Characterization of RF Noise in UTBB FD-SOI MOSFET https://t.co/LNlvvNOb5V

— Wladek Grabinski (@wladek60) October 26, 2016

from Twitter https://twitter.com/wladek60

October 26, 2016 at 04:49PM
via IFTTT

Transistor Sizing for Bias-Stress Instability Compensation in Inkjet-Printed Organic C-Inverters https://t.co/91uJURy3KA #papers

Transistor Sizing for Bias-Stress Instability Compensation in Inkjet-Printed Organic C-Inverters https://t.co/91uJURy3KA #papers

— Wladek Grabinski (@wladek60) October 25, 2016

from Twitter https://twitter.com/wladek60

October 25, 2016 at 09:07PM
via IFTTT

[ESSDERC Paper] Compact model for variability of low frequency noise due to number fluctuation effect

Compact model for variability of low frequency noise due to number fluctuation effect

N. Mavredakis and M. Bucher

2016 46th European Solid-State Device Research Conference (ESSDERC)

Lausanne, Switzerland, 2016, pp. 464-467

doi:10.1109/ESSDERC.2016.7599686

Abstract: Variability of low frequency noise (LFN) in MOSFETs is both geometry- and bias-dependent. RTS noise prevails in smaller devices where noise deviation is mostly area-dominated. As device dimensions increase, operating conditions determine noise variability maximizing it in weak inversion and increasing it with drain voltage. This dependence is shown to be directly related with fundamental carrier number fluctuation effect. A new bias- and area-dependent, physics-based, compact model for 1/f noise variability is proposed. The model exploits the log-normal behavior of LFN. The model is shown to give consistent results for average noise, variance, and standard deviation, covering bias-dependence and scaling over a large range of geometry.

Keywords: compact models, Low-frequency noise, MOSFET, Reactive power, Semiconductor device modeling, Shape, Standards, MOSFET, low frequency noise, noise variability

URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7599686&isnumber=7598672

[SSE Paper] Elimination of the channel current effect on the characterization of MOSFET threshold voltage using junction capacitance measurements

Elimination of the channel current effect on the characterization of MOSFET threshold voltage using junction capacitance measurements 

Daniel Tomaszewski^a, Grzegorz Głuszko^a, Lidia Łukasiak^b,
Krzysztof Kucharski^a, Jolanta Malesinska^b

^aDivision of Silicon Microsystem and Nanostructure Technology, Instytut Technologii Elektronowej (ITE), ul. Okulickiego 5E, 05-500 Piaseczno, Poland 

^bInstitute of Microelectronics and Optoelectronics, Warsaw University of Technology, ul. Koszykowa 75, 00-662 Warsaw, Poland

Abstract: An alternative method for an extraction of the MOSFET threshold voltage has been proposed. It is based on an analysis of the MOSFET source-bulk junction capacitance behavior as a function of the gate-source voltage. The effect of the channel current on the threshold voltage extraction is fully eliminated. For the threshold voltage and junction capacitance model parameters non-iterative methods have been used. The proposed method has been demonstrated using a series of MOS transistors manufactured using a standard CMOS technology.

Keywords: MOSFET CMOS Threshold voltage Junction capacitance Parameter extraction

Cite: Tomaszewski D et al. Elimination of the channel current effect on the characterization of MOSFET threshold voltage using junction capacitance measurements. Solid State Electron (2016), http://dx.doi.org/10.1016/j.sse.2016.10.006

Sub-Minimum-Area MPW Sharing

Is Your Multi-Project Wafer Project Smaller Than the Fab Minimum Area?

Share the minimum area with other MPW customers to save mask costs

With the cost of mask sets going up with every node, even a multi-project wafer (MPW) can break your NRE budget, particularly if you plan to run multiple test spins. At 28nm, a 6mm2 area tile can cost over $100,000.

One solution is to share the minimum tile area with someone else who is using the same technology and metal stack that you are targeting. We periodically get these kinds of requests from customers. Please contact directly star@esilicon.com if you would like eSilicon to list your own MPW shuttle sharing opportunity, or if you would like eSilicon to contact you when future MPW tile sharing opportunities are available.

Following are upcoming opportunities to share a multi-project wafer (MPW) tapeout with another eSilicon customer. If you are interested, just email eSilicon.

Multi-Project Wafer Minimum Tile Sharing Opportunities for TSMC Technologies

Tapeout Month	Technology	Metal Stack	I/O	Price/mm2	Minimum Area	Final GDSII Due	Tapeout Date	Estimated Ship Date
October	65nm MS RF GP	1P9M_6x1z1u	2.5V	$4,700	1mm2	October 10	October 12	November 23
	65nm MS RF LP	1P9M_6x1z1u	2.5V	$4,700	1mm2	October 10	October 12	November 23
	180nm MS RF G	1P6M_4x1u	3.3V	$1,000	5mm2	October 24	October 26	December 7
November	40nm MS RF LP	1P10M	1.8V	$7,500	1mm2	October 31	November 2	January 17

[read more...]

#Compact #Modeling of Surface Potential, Charge, and Current in Nanoscale Transistors Under Quasi-Ballistic Regime https://t.co/BsnCEEdo8a

#Compact #Modeling of Surface Potential, Charge, and Current in Nanoscale Transistors Under Quasi-Ballistic Regime https://t.co/BsnCEEdo8a

— Wladek Grabinski (@wladek60) October 21, 2016

from Twitter https://twitter.com/wladek60

October 21, 2016 at 04:54PM
via IFTTT

Free Semiconductor Books on SemiWiki

Download free PDF versions of three pivotal semiconductor books available on SemiWiki.com:

1. Mobile Unleashed: The History of ARM
2. Fabless: The Transformation of the Semiconductor Industry
3. EDAGraffiti: 25 years of experience in EDA

Only registered SemiWiki members can access these wiki pages so if you are not already a member please join as a guest: https://www.semiwiki.com/forum/register.php

[mos-ak] [2nd Announcement and Call for Papers] 9th International MOS-AK Workshop Berkeley DEC.7, 2016

 9th International MOS-AK Workshop  

  Berkeley December 7, 2016 
    2nd Announcement and Call for Papers   

Together with the MOS-AK workshop host, Prof. Jaijeet Roychowdhury, UCB and International MOS-AK Board of R&D Advisers: Larry Nagel, Omega Enterprises Consulting (USA), Andrei Vladimirescu, UCB (USA); ISEP (FR) as well as all the Extended MOS-AK TPC Committee, we have pleasure to invite to the 9th International MOS-AK Workshop which will be held at EECS Department, University of California, Berkeley on December, 7, 2016. Planned MOS-AK workshop is organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors.

Important Dates:

• Preannouncement - Sept 2016
• Call for Papers - Oct. 2016
• Final Workshop Program - Nov. 2016
• MOS-AK Workshop - Dec. 7 2016

Venue:

EECS Department
University of California, Berkeley

Topics to be covered include the following among other related to the compact/SPICE modeling :

• Compact Modeling (CM) of the electron devices
• Advances in semiconductor technologies and processing
• Verilog-A language for CM standardization
• New CM techniques and extraction software
• Open Source TCAD/EDA modeling and simulation
• CM of passive, active, sensors and actuators
• Emerging Devices, TFT, CMOS and SOI-based memory cells
• Microwave, RF device modeling, high voltage device modeling
• Nanoscale CMOS devices and circuits
• Technology R&D, DFY, DFT and reliability/ageing IC Designs
• Foundry/Fabless Interface Strategies

Online MOS-AK Abstract Submission:
Prospective authors should submit online 

http://www.mos-ak.org/berkeley_2016/abstracts.php

(any related inquiries can be sent to abstracts@mos-ak.org)

Online Workshop Registration:

http://www.mos-ak.org/berkeley_2016/registration.php
(any related inquiries can be sent to register@mos-ak.org)

Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication in a special issue of the International Journal of High Speed Electronics and Systems

Extended MOS-AK Committee

WG19102016

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Reliable Gate Stack And Substrate Parameter Extraction Based On CV Measurements For 14nm FDSOI Technology https://t.co/enF2K7D6tT #papers

Reliable Gate Stack And Substrate Parameter Extraction Based On CV Measurements For 14nm FDSOI Technology https://t.co/enF2K7D6tT #papers

— Wladek Grabinski (@wladek60) October 17, 2016

from Twitter https://twitter.com/wladek60

October 17, 2016 at 02:19PM
via IFTTT

Theoretical analysis and modeling for nanoelectronics https://t.co/PsFJzoJgC8 #papers #feedly

Theoretical analysis and modeling for nanoelectronics https://t.co/PsFJzoJgC8 #papers #feedly

— Wladek Grabinski (@wladek60) October 15, 2016

from Twitter https://twitter.com/wladek60

October 15, 2016 at 10:00PM
via IFTTT

FOSDEM 2017 EDA Devroom Call for Participation

FOSDEM 2017 Electronic Design Automation Devroom
Call for Participation

This is the call for participation in the FOSDEM 2017 devroom on Free/Open Source Software (FOSS) Electronic Design Automation (EDA) tools, to be held on Sunday 5 February 2017 in Brussels, Belgium. We are looking for contributions under the form of talks and tutorials covering the following main topics:

• Printed Circuit Board (PCB) design tools (e.g. KiCad and gEDA)
• Analogue and digital simulators (e.g. ngspice, Qucs, Gnucap, Xyce, GHDL, Icarus and Verilator)
• Any other EDA tools such as high-level tools for digital hardware design (e.g. Migen) and HDL synthesis tools (e.g.Yosys)
• Inter-project opportunities for collaboration

We hope to provide an opportunity for attendees to bring themselves up to date on the latest FOSS EDA developments, share knowledge and identify opportunities to collaborate on development tasks. Have a look at last year's event for a taste of what the EDA devroom is about.

The submission process
Please submit your proposals at 

https://penta.fosdem.org/submission/FOSDEM17 

before 1 December 2016.

If you already have a Pentabarf account (for example as a result of having submitted a proposal in the past), make sure you use it to log in and submit your proposal. Do not create a new account if you already have one. Please provide a bit of information about yourself under Person -> Description -> Abstract. When you submit your proposal (creating an "Event" in Pentabarf), make sure you choose the "Electronic Design Automation (EDA) devroom" in the track drop-down menu. Otherwise your proposal might go unnoticed. Fill in at least a title and abstract for the proposed talk and a suggested duration. Bear in mind that a lot of the value in these meetings comes from the discussions, so please be reasonable regarding the duration of the talk.

Important dates

• 1 December 2016: deadline for submission of proposals
• 11 December 2016: announcement of final schedule
• 5 February 2017: devroom day

Recordings
The FOSDEM organisers hope to be able to live-stream and record all the talks. The recordings will be published under the same licence as all FOSDEM content (CC-BY). Only presentations will be recorded, not informal discussions and whatever happens during the lunch break. By agreeing to present at FOSDEM, you automatically give permission to be recorded. The organisers will agree to make exceptions but only for exceptional and well-reasoned cases.
Mailing list

Feel free to subscribe to the mailing list of the EDA devroom to submit ideas, ask questions and generally discuss about the event.

Spread the word!
This is the third EDA devroom at FOSDEM. The first two were very well received. Let's make sure as many projects and developers as possible are present. Thanks!

[call for papers] 1st EDTM 2017

EDTM Call for Papers 

Submission deadline: November 4th, 2016

Camera ready, one page text and one page figures

1st EDTM 2017

At Toyama International Conference Center, Toyama, Japan

February 28th to March 2nd, 2017

Why EDTM has been started: System performance continues to grow, even though device scaling is saturated. Based on strong manufacturing technologies, Asia has strong potential to take an initiative for system integration. Deep-dive discussions among technical communities on materials, processes, and devices are aimed to accelerate manufacturing innovations through this forum.

1. Technical sessions

EDTM 2017 and beyond will have a strong specific technical focus, and this year’s focus being on devices and process technologies for advanced applications, IoE (Internet of Everything) and related low-power devices, advanced memories, sensors, actuators, MEMS, bio.-chips, passive devices, and all types of (exploratory) devices related to advance applications and IoE. Papers/Posters on materials and processes for enabling above-menHoned devices building in heterogeneous integration such as 2.1, 2.5 and 3D structures using wafer-level packaging process (e.g.) are of great focus. EDTM aims for highest quality, and all papers accepted would be subject to IEEE-EDS standard review processes and conference publishing guidelines. Accepted and presented papers will be published in EDTM proceedings. A selected number of high impact EDTM papers would be invited for the consideration of publication in the IEEE Journal of Electron Devices Society (J- EDS) as extended version of EDTM conference papers following the IEEE publication policy and J-EDS author-guidelines.

2. Education

• Tutorials: We will provide both the basic and advanced programs. Basic program will be presented in local language.
• Poster sessions: Primarily intended for young engineers and students. The best poster will be awarded in the conference.
• Short courses: Will bring high level programs.

3. Exhibition

Given the strong semiconductor manufacturing base in Asia, we intend to offer exhibits that will demonstrate products and technology. All of the exhibitors will have an opportunity to offer technical insight and share their knowhow. Moreover, we hope to offer Forum Making Session to engage and allow deeper discussions between device, material, and equipment engineers and technologists.

Papers in the following areas are requested by Subcommittee on:

• Devices and Manufacturing for “Cloud and Edge”
• Packaging and Manufacturing for “Cloud and Edge”
• Process, Tools, and Manufacturing
• Semiconductor Materials
• Reliability & Modeling (including compact/SPICE)

[read more...]

IEDM 2016 Session 7: Modeling and Simulation Advanced Numerical and Compact Models

IEDM 2016 Session 7

Modeling and Simulation Advanced Numerical and Compact Models

Monday, December 5, 1:30 p.m. Continental Ballroom 7-9 

Co-Chairs: Denis Rideau, STMicroelectronics 

Xing Zhou, Nanyang Technological University

1:35 PM 

7.1 A Novel Synthesis of Rent's Rule and Effective-Media Theory Predicts FEOL and BEOL Reliability of Self-Heated ICs, W. Ahn, H. Jiang, S.H. Shin and M. Alam, Purdue University

2:00 PM 

7.2 New Approach for Understanding "Random Device Physics" from Channel Percolation Perspectives: Statistical Simulations, Key Factors and Experimental Results, Z. Zhang, Z. Zhang, R. Wang, X. Jiang, S. Guo, Y. Wang, X. Wang*, B. Cheng*, A. Asenov* and R. Huang, Peking University, *Synopsys

2:25 PM 

7.3 Oxide-Based Analog Synapse: Physical Modeling, Experimental Characterization, and Optimization, B. Gao, H. Wu, J. Kang*, H, Yu**, H. Qian, Tsinghua University, *Peking University, **Southern University of Science and Technology

2:50 PM 

7.4 Extending the Bounds of Performance in E-mode p-channel GaN MOSHFETs, A. Kumar and M. De Souza, The University of Sheffield

3:15 PM 

7.5 NSP: Physical Compact Model for Stacked-planar and Vertical Gate-All-Around MOSFETs, O. Rozeau, S. Martinie, T. Poiroux, F. Triozon, S. Barraud, J. Lacord, Y.-M. Niquet*, C. Tabone, R. Coquand, E. Augendre, M. Vinet, O. Faynot, and J.-C. Barb, CEA-Leti, *CEA-INAC

3:40 PM 

7.6 A Physics-Based Compact Model for Material- and Operation-Oriented Switching Behaviors of CBRAM, Y. Zhao, J. Hu, P. Huang, F. Yuan*, Y. Chai*, X. Liu and J. Kang, Peking University, *The Hong Kong Polytechnic University

4:05 PM 

7.7 Multi-Domain Compact Modeling for GeSbTe-based Memory and Selector Devices and Simulation for Large-scale 3-D Cross-Point Memory Arrays, N. Xu, J. Wang, Y. Deng, Y. Lu, B. Fu, W. Choi, U. Monga*, J. Jeon*, J. Kim*, K.-H. Lee* and E. S. Jung*, Samsung Semiconductor Inc., *Samsung Electronics

[read more...]

Compound Semiconductor Technical Committee Meeting

SEMI® International Standards Program

Compound Semiconductor Technical Committee Meeting

Fraunhofer IISB, Schottkystrasse 10, D-91058 Erlangen, Germany

Thu 13th October 2016 14:00 to 16:30

Co-chairs:
• Dr. Arnd-Dietrich Weber, SiCrystal
• N.N. 

Agenda: European Compound Semiconductor Committee Meeting

Task Force meetings – tbd

14:00 Welcome and Self-Introductions all

14:05 SEMI Standards Overview and Legal Reminders SEMI Staff

14:10 Review of the minutes and action items from the previous meeting SEMI Staff

14:15 Task Force Reports (~5 minutes each)

SiC-Task Force A. Weber

Status M55 5-year review (doc 4689)

Status M81 5-year-review (doc 6015)

Contactless Capacitive Resistivity Task Force W. Jantz

14:30 Discussion and approval of doc 4689 (M55 review) for ballot A. Weber

15:00 5-Year-Review of published documents

5-year-review of M54 (Guide for semi-insulating GaAs parameters): discuss and

approve TFOF and SNARF U. Kretzer

dentification and discussion of action items all

15:30 Compound Materials Liaison Reports

North America

Japan SEMI Staff

15:45 Any Other Business / Questions A. Weber

16:00 Next Meetings

16:15 Adjourn 

Lectures on Electromagnetism https://t.co/nxi9p90Cte #papers

Lectures on Electromagnetism https://t.co/nxi9p90Cte #papers

— Wladek Grabinski (@wladek60) October 12, 2016

from Twitter https://twitter.com/wladek60

October 12, 2016 at 10:55AM
via IFTTT

[website] Open Circuit Design Software

Visit the Open Circuit Design Software to learn more about the major electronic design automation (EDA) tools hosted by Open Circuit Design:

• Magic, the VLSI layout editor, extraction, and DRC tool
• XCircuit, the circuit drawing and schematic capture tool
• IRSIM, the switch-level digital circuit simulator
• Netgen, the circuit netlist comparison (LVS) and netlist conversion tool
• Qrouter, the over-the-cell (sea-of-gates) detail router
• Qflow, a complete digital synthesis design flow using open-source software and open-source standard cell libraries
• PCB, the printed circuit board layout editor

[More about Open Circuit Design Software]

[paper] Well-Posed Models of Memristive Devices

Well-Posed Models of Memristive Devices

Tianshi Wang, Jaijeet Roychowdhury

(Submitted on 15 May 2016)

Existing compact models for memristive devices (including RRAM and CBRAM) all suffer from issues related to mathematical ill-posedness and/or improper implementation. This limits their value for simulation and design and in some cases, results in qualitatively unphysical predictions. We identify the causes of ill-posedness in these models. We then show how memristive devices in general can be modelled using only continuous/smooth primitives in such a way that they always respect physical bounds for filament length and also feature well-defined and correct DC behaviour. We show how to express these models properly in languages like Verilog-A and ModSpec (MATLAB). We apply these methods to correct previously published RRAM and memristor models and make them well posed. The result is a collection of memristor models that may be dubbed "simulation-ready", i.e., that feature the right physical characteristics and are suitable for robust and consistent simulation in DC, AC, transient, etc., analyses. We provide implementations of these models in both ModSpec/MATLAB and Verilog-A.

Subjects: Emerging Technologies (cs.ET); Computational Engineering, Finance, and Science (cs.CE)
Cite as: arXiv:1605.04897 [cs.ET]
(or arXiv:1605.04897v1 [cs.ET] for this version)

Eben Upton Founder, Raspberry Pi Foundation at ARM TechCon

Hear Big Names Deliver Big Ideas Attend 6 inspirational keynotes with 1 free expo pass [get pass]

ARM TechCon is proud to announce its full keynote lineup for 2016. From the founder of Raspberry Pi to the CEO of SoftBank (and his take on its 32 billion dollar ARM acquisition), these presentations feature the leaders impacting your industry’s future. Hear them all when you register for a free expo pass.

Eben Upton Founder, Raspberry Pi Foundation

Charlie Miller Senior Security Engineer, Uber Advanced Technologies Center

Masayoshi Son CEO and Chairman of the Board, SoftBank Group Corp.

Mike Muller CTO, ARM

Jon Masters Chief ARM Architect and Technical Lead for RHEL Server, Red Hat

Simon Segars CEO, ARM

100 reads: Compact Device Modeling using Verilog-AMS and ADMS

Article reached 100 reads: Compact device modeling using Verilog-AMS and ADMS
Lemaitre L · Grabiński W · McAndrew C
Abstract: This paper shows how high level language as Verily-AMS can serve as support for compact modeling development of new devices. First section gives a full Verily-AMS code of a simplified bipolar transistor. Each part of the code is carefully examined and explained. Second section compared different implementations if the simplified bipolar transistor in different spice simulators. ADMS, an open-source tool developed at Motorola, performs the implementations from Verily-AMS to simulators. Third sections concludes the paper by describing by implementation of the EKV model into ADS using the compact model interface provided by Agilent.
View publication
12 citations 107 reads

SourceForge Project: FreeCAD

FreeCAD is a general purpose feature-based, parametric 3D modeler for CAD, MCAD, CAx, CAE and PLM, aimed directly at mechanical engineering and product design but also fits a wider range of uses in engineering, such as architecture or other engineering specialties. It is 100% Open Source and extremely modular, allowing for very advanced extension and customization.

FreeCAD is based on OpenCasCade, a powerful geometry kernel, features an Open Inventor-compliant 3D scene representation model provided by the Coin 3D library, and a broad Python API. The interface is built with Qt. FreeCAD runs exactly the same way on Windows, Mac OSX and Linux platforms. [Download FreeCAD]

The History of ARM

Free Copy of Mobile Unleashed: The History of ARM!
by Daniel Nenni Published on 10-04-2016

As most of you know SemiWiki published a book which is a really nice history of ARM. We have received many compliments on it and we are very proud. As a thank you to all SemiWiki members I would like to offer a free electronic version of the book (PDF).

Only registered SemiWiki members can access this wiki so if you are not already a member please join as  guest: https://www.semiwiki.com/forum/register.php

A Compact Model of Drain Current for GaN HEMTs Based on 2-DEG Charge Linearization

N. Karumuri; G. Dutta; N. DasGupta; A. DasGupta, "A Compact Model of Drain Current for GaN HEMTs Based on 2-DEG Charge Linearization," in IEEE Transactions on Electron Devices , vol.PP, no.99, pp.1-7 doi: 10.1109/TED.2016.2605130

Abstract: A physics-based simple and accurate compact model of drain current for GaN-based high electron mobility transistors (HEMTs) is presented. The model is developed using analytical relations for charges in the 2-D electron gas and barrier layer. For the first time, a simple charge linearization approach has been used for GaN-based HEMTs. The access regions are accurately modeled using transistors. The model is rigorously validated over a wide range of geometries and parameters for AlGaN/GaN and AlInN/GaN HEMTs. The model also passes the DC Gummel symmetry test.

keywords: {Computational modeling; Electric potential; HEMTs; Integrated circuit modeling; MODFETs; Threshold voltage;2-D electron gas (2-DEG) charge;AlGaN/GaN;AlInN/GaN;GaN high electron mobility transistor (HEMT); Gummel symmetry; SPICE model.;charge linearization; charge-based; compact model;drain current},

[read more...]

Prof. Andrzej Strojwas receives 2016 Kaufman Award

The Dictates of Fate: Andrzej Strojwas receives 2016 Kaufman Award
as of Sept. 29, 2016 by Peggy Aycinena

Dr. Andrzej J. Strojwas, professor of Electrical and Computer Engineering at Carnegie Mellon University, has been named recipient of the 2016 Phil Kaufman Award for Distinguished Contributions to Electronic System Design.

Interestingly, this is the first year that the Kaufman award is being presented for contributions to Electronic System Design, not EDA. Very appropriate given that Strojwas’ contributions are in manufacturing and not design. Prof. Stojwas is CTO at PDF Solutions, which per company CEO John Kibarian has never been an EDA company. And with Kibarian serving as co-chair of the ESD Alliance, the organization formerly known as EDAC has now fully embraced its role across the entirety of electronic system design.

Besides this nod to EDAC’s ongoing evolution, the larger implications in CEDA and the ESD Alliance naming Andrzej Strojwas as this year’s Kaufman recipient are profound: The problems associated with electronic systems are not so much in the design these days, but in the extraordinary difficulties associated with manufacturing those designs. It’s really tough, as you all know, when the structures being manufactured are smaller than the wavelengths of light used to etch them.

Which bring us back to Dr. Strojwas. He has been CTO at PDF for 20 years. Back in the last century/millennium, the problems of manufacturing below 193 nanometers could only have been guessed at, yet the company was already working on the intriguing issues of capturing post-manufacturing data and somehow packaging it up to make it useful: How does the semiconductor supply chain glean vital information about the vagaries of manufacturing a real chip and send it back up to the designers so they can learn from the reality when they put pen to paper to design the next hypothetical?

This engineering of the engineering demands scientific curiosity, steely eyed attitudes towards the realities of physics and material science, and a large dollop of business savvy to navigate between the needs and demands of the foundries and the needs and demands of the designers. Let’s allow Dr. Strojwas to take it from here. We spoke by phone this week after his award was announced. 

[read more...]

Angstrem is developing new radiation-resistant microchips

as of August 16, 2016 by VICTORIA ZAVYALOVA, RBTH

Angstrem is planning to export microchips to India's aerospace sector. This is a major turning point for the Russian microelectronics industry, which until recently was almost entirely dependent on imports.
The Russian company Angstrem is completing the development of new radiation-resistant microchips for use in outer space. In September the manufacturer is planning to begin deliveries to India, its first major export market. This initial delivery will total about 10,000 microchips, and the contract is estimated at $200,000.
"While India has a full-fledged space program, the country does not have a complete technological cycle for the production of spacecraft and launch vehicles," said Vitali Aryshev, Angstrem's director of communications, when explaining the choice of this market. [read more...]

Power Semiconductor Devices and Smart Power IC Technologies CFP https://t.co/P8bWJZLgrw #papers #feedly

Power Semiconductor Devices and Smart Power IC Technologies CFP https://t.co/P8bWJZLgrw #papers #feedly

— Wladek Grabinski (@wladek60) October 1, 2016

from Twitter https://twitter.com/wladek60

October 01, 2016 at 02:29PM
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