[EDS DL] Prof. M. Lanza, KAUST; Hexagonal boron nitride based electronic devices and circuits: status and prospects

PROF. Mario Lanza, KAUST- Hexagonal boron nitride based

electronic devices and circuits: status and prospects

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The EDS Germany Chapter and NanoP proudly presents Mario Lanza from KAUST, Saudi Arabia for a Distinguished Lecture on
"Hexagonal boron nitride based electronic devices and circuits: status and prospects". The lecture will be held on 20th May 2021 at 3pm Berlin time.

Date and Time

• Date: 20 May 2021
• Time: 03:00 PM to 04:00 PM
• All times are Europe/Berlin
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Location

The Distiguished Lecture will be held via Zoom. Login information provided before the event and requires registration.

• Wiesenstraße 14
• Gießen
• Germany 35390

Hosts

• Germany Section Chapter, ED15
• Co-sponsored by NanoP, Technische Hochschule Mittelhessen - University of Applied Sciences

Registration

• Starts 29 March 2021 06:00 PM
• Ends 16 May 2021 12:00 AM
• All times are Europe/Berlin
• No Admission Charge

• Register Now

[webinar] "More Moore Roadmap" by IRDS and SINANO

IEEE EDS France, IRDS and the SINANO Institute will organize a Webinar 

"More Moore Roadmap"

by Mustafa Badaroglu 

IRDS-IFT More Moore Leader

The webinar will be held on 8th April 2021 at 16:00 Paris time. Interest participants please register via IEEE vTools by the following link: https://events.vtools.ieee.org/event/register/267103

Other Webinars of the IRDS Chapters will be announced in the EDS Newsletters

Intel 2.0 = #Intel #Foundry Services https://t.co/GpOUxvmj8q #semi https://t.co/55IAiX3lK6

Intel 2.0 = #Intel #Foundry Services https://t.co/GpOUxvmj8q #semi pic.twitter.com/55IAiX3lK6

— Wladek Grabinski (@wladek60) March 30, 2021

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March 30, 2021 at 11:09PM
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#QuickFeather: First #FPGA board to ship with a #FOSSi toolchain https://t.co/ZydBBEyjBC #semi #opensource https://t.co/fuiix66vy7

#QuickFeather: First #FPGA board to ship with a #FOSSi toolchain https://t.co/ZydBBEyjBC #semi #opensource pic.twitter.com/fuiix66vy7

— Wladek Grabinski (@wladek60) March 30, 2021

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March 30, 2021 at 03:12PM
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[https://t.co/wdfbm5xXB8] #Philips sells consumer electronics division to PE in #China for 3.7 billion euros. Philips announced that it will sell its consumer electronics division to Hillhouse Capital, a major private equity fund in China https://t.co/hNB1xoRgAK #semi https://t.co/Ea4ZcwCfdE

[https://t.co/wdfbm5xXB8] #Philips sells consumer electronics division to PE in #China for 3.7 billion euros. Philips announced that it will sell its consumer electronics division to Hillhouse Capital, a major private equity fund in China
https://t.co/hNB1xoRgAK #semi pic.twitter.com/Ea4ZcwCfdE

— Wladek Grabinski (@wladek60) March 26, 2021

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from Twitter https://twitter.com/wladek60

March 26, 2021 at 03:28PM
via IFTTT

[https://t.co/Jk28F7d8do] Verification In #OpenSource Era https://t.co/3Skg6dmbqz #SEMI https://t.co/I86bPeSKMA

[https://t.co/Jk28F7d8do] Verification In #OpenSource Era https://t.co/3Skg6dmbqz #SEMI pic.twitter.com/I86bPeSKMA

— Wladek Grabinski (@wladek60) March 25, 2021

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from Twitter https://twitter.com/wladek60

March 25, 2021 at 02:43PM
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[mos-ak] [2nd Announcement and C4P] 3rd MOS-AK LAEDC Workshop (virtual/online) April 18, 2021

2nd Announcement and C4P

Together with  local organization team, International MOS-AK Board of R&D Advisers as well as all the Extended MOS-AK TPC Committee, we have the pleasure to invite to 3rd consecutive MOS-AK Compact/SPICE Modeling Workshop which will be organized as the virtual/online event on April 18, 2021 preceding the LAEDC Conference.

Planned virtual 3rd MOS-AK LAEDC Workshop aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring academic and industrial experts in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors.

Venue: Virtual/Online at LAEDC Conference

Online Workshop Registration to be in April 2021, 

any related enquiries can be sent to registration@mos-ak.org

Topics to be covered include the following among other related to the compact/SPICE modeling and its Verilog-A standardization:

• Compact Modeling (CM) of the electron devices
• Advances in semiconductor technologies and processing
• Verilog-A language for CM standardization
• New CM techniques and extraction software
• Open Source (FOSS) TCAD/EDA modeling and simulation
• CM of passive, active, sensors and actuators
• Emerging Devices, Organic TFT, CMOS and SOI-based memory cells
• Microwave, RF device modeling, high voltage device modeling
• Nanoscale CMOS, BiCMOS, SiGe, GaN, InP devices and circuits
• Technology R&D, DFY, DFT and reliability/aging IC designs
• Foundry/Fabless Interface Strategies

Online Abstract Submission to be open, 

any related enquiries can be sent to abstracts@mos-ak.org

Important Dates: 

• Call for Papers - Dec. 2020
  
• 2nd Announcement - March 2020
• Final Workshop Program - April 2020
• MOS-AK Workshop April 18, 2021

W.Grabinski for Extended MOS-AK Committee

WG23032021

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[EETimes] (Re)Shoring Up #semi Manufacturing - https://t.co/fNy0FgOiEG https://t.co/mVhn0SPjOS

[EETimes] (Re)Shoring Up #semi Manufacturing - https://t.co/fNy0FgOiEG pic.twitter.com/mVhn0SPjOS

— Wladek Grabinski (@wladek60) March 23, 2021

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from Twitter https://twitter.com/wladek60

March 23, 2021 at 03:22PM
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Virtual Si Museum /2111/ E.Eng Tools

This is how I was introduced to the engineering. My very fist log rule and my HP-21 scientific calculator (successor of the famous HP-35)

REF:

[1] Slide rule: https://en.wikipedia.org/wiki/Slide_rule

[2] HP-21 scientific calculator: https://en.wikipedia.org/wiki/HP-21

[Extended C4P] ESSDERC Track3 "Compact Modeling and Process/Device Simulation"

51st European Solid-State Device Research Conference ESSDERC

47th  European Solid-State Circuits Research Conference ESSCIRC  

will be held together in hybrid format in Grenoble in September this year

https://www.esscirc-essderc2021.org/

The conferences will be arranged in three device-related tracks, three joint tracks, and seven circuit-related tracks. Among the device-related there will be the Track3: "Compact modeling and process/device simulation" (including TCAD and advanced simulation techniques and studies) although not limited, papers are solicited for the following main topics:

• Compact/SPICE modeling of electronic, optical, organic, and hybrid devices and their IC implementation and interconnection.

• Verilog-A models of the semiconductor devices (including Bio/Med sensors, MEMS, Microwave, RF, High voltage and Power, emerging technologies and novel devices), parameter extraction, reliability and variability, performance evaluation and open source benchmarking/implementation methodologies.

• Modeling of interactions between process, device and circuit design, Design Technology Co-Optimization, Foundry/Fabless Interface Strategies.

• Numerical, analytical, statistical modeling and simulation of electronic, optical and hybrid devices, interconnect, isolation and 2D/3D integration; Aspects of materials, fabrication processes and devices e.g. advanced physical phenomena (quantum mechanical and non-stationary transport phenomena, ballistic transport, …); Mechanical or electro-thermal modeling and simulation; DfM.

• Reliability of materials and devices.

• Design Technology-Co-Optimization.

The deadline for the submission of abstracts is April 19th April 26th and the call for papers can be downloaded here https://www.esscirc-essderc2021.org/call-for-papers

Thierry Poiroux, CEA-LETI (F) - Track3 Chair

Compact Modeling and Process/Device Simulation

https://www.esscirc-essderc2021.org/

[C4P] 32nd MIEL 2021

32nd IEEE International Conference on Microelectronics (MIEL 2021) 

Niš  September 12-14, 2021

This year,  MIEL 2021 will be dedicated to

Professor Ninoslav Stojadinovic, founder of MIEL Conference.

Due to the unprecedented health, travel and social distance restrictions imposed in Serbia and all over the world as a result of the COVID-19 pandemic, all participants will be invited to join a virtual MIEL 2021.

Accepted papers will be published in the Proceedings of the MIEL 2021 Conference, and included in IEEE Xplore database, subject to regular registration of at least one of the authors before July 16th, 2021.

 

We are pleased to invite you, as an expert in the field of microelectronics, to submit a paper to MIEL 2021 Conference and to encourage colleagues to do it.

 

The deadline for the submission of two page-extended summaries (including figures, tables, and references) is May 7th, 2021.

 

Extended versions of selected papers from MIEL 2021 Conference will be published (after the regular review process) in:

Journal of Circuits, Systems and Computers

or

Facta Universitatis, Series: Electronics and Energetics

Looking forward to receiving your abstract for MIEL 2021 Conference, we remain with

 

Best regards,

Vojkan Davidović

Danijel Danković

http://miel.elfak.ni.ac.rs/

Please contact miel@elfak.ni.ac.rs for further information.

[C4P] EuroSOI-ULIS 2021, September 1-3, 2021, Caen (F)

The Seventh Joint International EuroSOI and ULIS Conference 

will be held in hybrid format in Caen, Normandy, France

from September 1 to September 3, 2021

After a virtual 2020 edition, if sanitary condition will permit, the 2021 EUROSOI-ULIS event will be held in hybrid format. The conference will be preceded on August 31, 2021 by "The Future of Nanoelectronics Devices and Systems Beyond Moore" Workshop.

The Conference Committee hopes that you will actively participate by submitting high quality papers and will enjoy the conference.
Original 2-page abstracts with illustrations will be accepted for review in pdf format.

Abstract submission is now open. The abstract submission deadline is Mai 17, 2021 Mai 31, 2021. 

More information are provided on the Conference website: 
https://eurosoiulis2021.sciencesconf.org

Papers in the following areas are solicited:

• Advanced SOI materials and structures; physical mechanisms and innovative SOI-like devices.
• New channel materials for CMOS: strained Si, strained SOI, SiGe, GeOI, III-V and high mobility materials on insulator; carbon nanotubes; graphene and other two-dimensional materials.
• Properties of ultra-thin films and buried oxides, defects, interface quality; thin gate dielectrics: high-κ materials for switches and memory.
• Nanometer scale devices: technology, characterization techniques and evaluation metrics for high performance, low power, reliability, high frequency and memory applications.
• Alternative transistor architectures including FDSOI, Nanowire, FinFET, MuGFET, vertical MOSFET, FeFET and Tunnel FET, MEMS/NEMS, Beyond-CMOS nanoelectronic devices.
• New functionalities in silicon-compatible nanostructures and innovative devices representing the More than Moore domain, nanoelectronic sensors, biosensor devices, energy harvesting devices, RF devices, imagers, etc.
• CMOS scaling perspectives; device/circuit level performance evaluation; switches and memory scaling; three-dimensional integration of devices and circuits, heterogeneous integration.
• Transport phenomena, compact modeling, device simulation, front- and back-end process simulation.
• Advanced test structures and characterization techniques, parameter extraction, reliability and variability assessment techniques for new materials and novel devices.
  

Confirmed Plenary Talks Speakers:

• Alexander Zaslavsky (Brown University, USA)
• Anne Vandooren (imec, Belgium)
• Frédéric Allibert (SOITEC, France)
• Jean-Michel Sallèse (EPFL, Switzerland)
• Sorin Cristoloveanu (IMEP Minatec, Grenoble, France)
• Sorin Voinigescu (University of Toronto, Canada)

The authors of the accepted contributions will be requested to provide a 4-page extended abstract which will be included in the Conference Technical Digest which will be published by IEEE and will be available online through IEEE Xplore. Outstanding papers will be invited for publication in a special issue of Solid-State Electronics.

The best paper award, renamed "The Androula Nassiopoulou Best Paper Award" in tribute to her, will be attributed by the SINANO Institute. The best poster award will be attributed by ELSEVIER.

We look forward to seeing you in Caen in 2021 ( https://en.normandie-tourisme.fr/unmissable-sites/caen/things-to-do/).

With best regards,
The EuroSOI-ULIS 2021 Organizing Committee

Note:
We are glad to inform you that 2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Proceedings has been posted to the IEEE Xplore digital library
https://ieeexplore.ieee.org/xpl/conhome/9365069/proceeding
If you missed the last edition of EuroSOI-ULIS, do not miss the scientific articles published in the IEEE Xplore database! Many thanks to all authors and attendees for their essential contributions that endorsed EuroSOI ULIS'2020 as a successful virtual conference! Information on EuroSOI-ULIS'2020 virtual edition may be found in the IEEE EDS Newletter published in January 2021 (https://eds.ieee.org/publications/eds-newsletter ; pages  58-60)

[Workshop] Democratizing IC Design, April 7th, 2021

Solid-State Circuits Directions Workshop: Democratizing IC Design

Wednesday, April 7th, 2021 at 7:00 AM PT / 10:00 AM ET This event is free and open to all

CLICK HERE TO REGISTER

EVENT DESCRIPTION Solid-State Circuits Directions (SSCD) is a new technical committee within the IEEE Solid-State Circuits Society (related article). Its charter is to promote forward-looking topics, build new communities and stimulate interaction with others. Following SSCD’s inaugural event on hardware security, the upcoming workshop will look at the new movement toward an open-source ecosystem for integrated circuit design. Over the past several decades, society has strongly benefited from free and open-source software. More recently, the open-source spirit has expanded to hardware and has energized a new maker community that tinkers with embedded systems at the printed circuit board level. Groundbreaking developments have now also opened the door toward democratizing integrated circuit design. Last year, Google, SkyWater and efabless have partnered to launch a shuttle program based on SkyWater’s SKY130 open-source process (130 nm CMOS). This technology is offered to the open community along with a complete design flow to enable designers to implement their ideas. This workshop will provide an overview of this program and highlight upcoming opportunities to benefit from it. Finally, it will showcase specific design work delivered by the community members and articulate a call to action for volunteers to design, teach and mentor. AGENDA 7:00 AM PT- Welcome & Introductions (Boris Murmann, Stanford University) 7:05 AM PT- Fully open source manufacturable PDK for a 130nm process (Tim Ansell, Google) 7:35 AM PT- 45 Chips in 30 Days: Open Source ASIC at its best! (Mohamed Kassem, efabless) 7:55 AM PT- Design 1: Open Source eFPGA implementation in SKY130 (Xifan Tang, University of Utah) 8:25 AM PT- Design 2: Amateur Radio Satellite Transceiver (Thomas Parry, SystematIC Design) 8:55 AM PT- Call to Action: Need volunteers to design, teach and mentor 9:00 AM PT- Adjourn

[C4P] ISPS 2021 Prague, August 25–27, 2021

 15th INTERNATIONAL SEMINAR ON POWER SEMICONDUCTORS

ISPS 2021

Prague, 25 August – 27 August 2021

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Organised by	IET Czech Network in co-operation with the IEEE Czechoslovakia Section
Co-sponsored by	Faculty of Electrical Engineering, Department of Electrotechnology, Czech Technical University in Prague
Technical sponsor	ECPE European Center for Power Electronics e.V.
Conference website	http://technology.fel.cvut.cz/ISPS2021

BACKGROUND

The 15th International Seminar on Power Semiconductors (ISPS 2021) provides a forum for technical discussion in the area of power semiconductor devices and their applications. It is a small conference with the special flair of an atmosphere of searching deeper insight and intensive discussion.

AREAS OF INTEREST

• Power semiconductor devices (materials, physics, modelling, technology, diagnostics)
• Packaging, advanced device applications, reliability

Papers oriented in the field of power semiconductors are supposed to be presented in sessions on

• Device Physics and Technology
• Power Bipolar Devices
• Voltage-Controlled Power Devices
• Wide Bandgap Power Devices
• Power Integration
• Advanced Applications
• Packaging, Reliability & Modelling.

A round table discussion oriented on topical problems of research and education in the field of power semiconductors will be organised in the framework of the seminar.

PAPER SUBMISSION

A summary of 300–500 words (maximum two pages including figures and tables) is required for review. It should be uploaded in electronic format (.doc or .pdf files) to the ISPS 2021 easychair conference system:

http://easychair.org/conferences/?conf=isps2021

before April 30, 2021.

PUBLICATION

Presented papers will be published in the seminar proceedings, which will be distributed at the seminar registration. We are delighted to announce that the best papers presented at the conference will be invited for consideration in a special issue of the IET Power Electronics Journal dedicated to the ISPS 2021 seminar.

ORGANISING COMMITTEE

Chairman:	Prof Vítězslav Benda, FIET
Members:	Dr Vítězslav Jeřábek, MIET
	Dr Martin Molhanec
	Dr Ladislava Černá, MIET
	Dr Pavel Hrzina

Nine out of ten #chips used by #US industries are made outside the country

[https://t.co/iJTj8FNNaJ] Nine out of ten #chips used by #US industries, including automotive and defense, are made outside the country https://t.co/91uq9m2VLA#semi pic.twitter.com/jhWxs4YDy5

— Wladek Grabinski (@wladek60) March 16, 2021

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from Twitter https://twitter.com/wladek60

March 16, 2021 at 11:12AM
via IFTTT

[paper] 3D integrated GaN/RF-SOI SPST switch

Frédéric Drillet, Jérôme Loraine, Hassan Saleh, Imene Lahbib, Brice Grandchamp, Lucas Iogna-Prat, Insaf Lahbib, Ousmane Sow, Albert Kumar and Gregory U'Ren 

RF Small and large signal characterization of a 3D integrated GaN/RF-SOI SPST switch 

International Journal of Microwave and Wireless Technologies, pp. 1–6, 2021.

*X-FAB France, Corbeil-Essonnes (F)

Abstract: This paper presents the radio frequency (RF) measurements of an SPST switch realized in gallium nitride (GaN)/RF-SOI technology compared to its GaN/silicon (Si) equivalent. The samples are built with an innovative 3D heterogeneous integration technique. The RF switch transistors are GaN-based and the substrate is RF-SOI. The insertion loss obtained is below 0.4 dB up to 30 GHz while being 1 dB lower than its GaN/Si equivalent. This difference comes from the vertical capacitive coupling reduction of the transistor to the substrate. This reduction is estimated to 59% based on a RC network model fitted to S-parameters measurements. In large signal, the linearity study of the substrate through coplanar waveguide transmission line characterization shows the reduction of the average power level of H2 and H3 of 30 dB up to 38 dBm of input power. The large signal characterization of the SPST shows no compression up to 38 dBm and the H2 and H3 rejection levels at 38 dBm are respectively, 68 and 75 dBc.

Fig: X-FAB 3D integration proposal cross-section (left) and the picture of a GaN coupon (right).

Acknowledgement: We would like to acknowledge the Nano2022 program for partially funding this work.

Supplementary material: The supplementary material for this article can be found at DOI: 0.101/1759078721000076

#SMIC reported to regain license to receive process equipment

[https://t.co/4cRTlKFKn6] #SMIC reported to regain license to receive #14nm and older process equipment https://t.co/BR3CexZKHP #semi pic.twitter.com/xybYUjI6MM

— Wladek Grabinski (@wladek60) March 15, 2021

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from Twitter https://twitter.com/wladek60

March 15, 2021 at 11:46AM
via IFTTT

[ElectronicsB2B] #China Semiconductor Trade Association #CSIA Establishes Work Group With Semiconductor Industry Association #SIA #semi #feedly https://t.co/ZaWL8q2vqJ https://t.co/aZF0Ihuimb

[ElectronicsB2B] #China Semiconductor Trade Association #CSIA Establishes Work Group With Semiconductor Industry Association #SIA #semi #feedly https://t.co/ZaWL8q2vqJ pic.twitter.com/aZF0Ihuimb

— Wladek Grabinski (@wladek60) March 15, 2021

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from Twitter https://twitter.com/wladek60

March 15, 2021 at 11:36AM
via IFTTT

[lectronics Weekly] #TSMC said to be planning $35bn #Arizona #Gigafab #semi https://t.co/pYLE1kdtDb https://t.co/YflKAcwTaa

[lectronics Weekly] #TSMC said to be planning $35bn #Arizona #Gigafab #semi https://t.co/pYLE1kdtDb pic.twitter.com/YflKAcwTaa

— Wladek Grabinski (@wladek60) March 15, 2021

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from Twitter https://twitter.com/wladek60

March 15, 2021 at 11:22AM
via IFTTT

[C4P] ICMECE 2021 (virtual) on 27-28 November 2021

INTERDISCIPLINARY CONFERENCE ON MECHANICS, COMPUTERS AND ELECTRICS

ICMECE (virtual) 27-28 November 2021

www.icmece.org

Interdisciplinary Conference on Mechanics, Computers and Electrics (ICMECE 2021) will be held on 27-28 November 2021 as virtual. The goal of ICMECE-2021 is to gather scientists, engineers, researchers, technicians and industrial representatives to present the cutting-edge studies on Mechanical, Computer and Electrical Systems and form an interdisciplinary academic forum to discuss the scientific and engineering issues to arrive at more complete systems for the applications of future world.

The audience on the interdisciplinary issues can be M.Sc./Ph.D. students, post graduate Students, research Scholars, post-doc scientists and all other academicians related to Mechanical Engineering, Civil Engineering, Electrical, Electronics & Communication Engineering, Computer Science & Engineering, Communication Engineering, Mechatronics, and Natural Sciences. In addition, companies focusing on the entrepreneurship and research & development can participate, too. The conference will perform traditional research paper presentations as well as the keynote talks by prominent speakers focusing on the related state-of-the-art technologies in the interdisciplinary fields of the conference.

PUBLICATION

All accepted/presented papers will appear in ICMECE Conference Proceedings. Extended versions of the selected papers will be submitted to SCOPUS and SCI-indexed journals. Journal list will be improved till the conference time.

• Journal of Energy Systems (Scopus)
• Turkish Journal of Education (E-SCI)
• Journal of Polytechnic (E-SCI)
• International Journal of Automotive Science and Technology (TR Dizin)
• Applied Solar Energy (Scopus)
• Technology and Economics of Smart Grids and Sustainable Energy (Scopus) 

KEYNOTE SPEAKERS

• Prof. Dr. Peter R.N. Childs Imperial College London, UK
• Prof. Dr. Josep M. Guerrero Aalborg University, Denmark
• Prof. Dr. Adnan Sözen, Gazi University, Turkey
• Prof. Dr. Francesco Cottone Perugia University, Italy
• Prof. Dr. Nicu Bizon Pitesti University, Romania

Virtual Conference Days: 27-28 November 2021
Manuscript Submission Deadline: 1 September 2021

Your contribution is appreciated.

ICMECE 2021 Organizing Committee

www.icmece.org

IEEE CEDA Community Calls | March 2021

Community Calls Call for Papers: ICCAD 2021 2021 International Conference On Computer Aided Design 1-4 November 2021  |  Hilton Munich Park, Munich, Germany ICCAD is the premier conference devoted to technical innovations in Electronic Design Automation. Original technical submissions on, but not limited to, the following topics are invited: System-level CAD, Synthesis, Verification, Physical Design, Analysis, Simulation, and Modeling, and CAD for Emerging Technologies, Paradigms. Paper submissions must be made through the online submission system at the ICCAD website. Regular papers will be reviewed as finished papers; preliminary submissions will be at a disadvantage. Research papers with open-source software are highly encouraged where the software will be made publicly available (via GitHub or similar) with the camera-ready version if the paper has been accepted. For more information on ICCAD 2021, visit the conference website. Important Deadlines Abstract Submissions: 21 May Full Paper Submissions: 28 May   Call for Papers Call for Articles: D&T Special Issue on Testability and Dependability of AI Hardware Deadline to Submit: 15 April 2021 In recent years, there has been an expedited trend in embracing bold and radical innovation of computer architectures, aiming at the continuation of computing performance improvement despite the slowed-down physical device scaling. One new frontier in the field of computing architecture is about AI (Artificial Intelligence) hardware, including AI hardware accelerators and neuromorphic computing processors. AI hardware has undergone a transformation from general-purpose computing to domain-specific computing (especially for deep learning applications), from Von Neumann architecture to non-Von Neumann architecture, etc. While the main focus nowadays is still functional implementation, the testability and dependability of these new architectures need to be addressed before the mainstream adoption of any emerging technology. This special issue seeks original manuscripts that will cover innovative research proposing solutions for the testability and dependability challenges in the following fields: AI hardware accelerators and Neuromorphic computing. This special issue is organized by Fei Su, Intel Corporation, USA; Chunsheng Liu, Alibaba Inc., USA; and Haralampos-G. Stratigopoulos, Sorbonne Université, CNRS, LIP6, France. More information about the issue and related submission guidelines can be found here. The article submission deadline is on April 15, 2021. Call for Papers Call for Papers, Workshops, Tutorials, and Special Sessions: ESWEEK 2021 10-15 October 2021  |  Virtual Conference Embedded Systems Week (ESWEEK) is the premier event covering all aspects of hardware and software design for smart, intelligent and connected computing systems. By bringing together three leading conferences, one symposium, several workshops and tutorials, ESWEEK allows attendees to benefit from a wide range of topics covering the state of the art in embedded systems research and development. CASES CODES+ISSS EMSOFT NOCS Workshops Registered attendees can attend sessions in any of the ESWEEK conferences (CASES, CODES+ISSS, EMSOFT), the NOC symposium, tutorials and workshops. More information about participation, submission guidelines, and deadlines of the different events can be found on the conference website.   Important Deadlines Abstract Submissions: 2 April Full Paper Submissions: 9 April Workshop Proposals: 16 April Tutorial and Special Sessions: 30 April CASES, CODES+ISSS, EMSOFT, WiP Submissions: 4 June Author Notification: 5 July Call for Papers