Solid-State Electronics
Volume 146, August 2018, Pages 50–65
Invited Review
Volume 146, August 2018, Pages 50–65
Invited Review
S. Strangioa,b, F. Settinoa,b, P. Palestria, M. Lanuzzab, F. Crupib, D. Essenia, L. Selmia,c
bDIMES, Università della Calabria, Via P. Bucci, 41C, I-87036 Arcavacata di Rende (CS), Italy
cDipartimento di Ingegneria “Enzo Ferrari”, Università degli Studi di Modena e Reggio Emilia, I-41100 Modena, Italy
ARTICLE INFO: The review of this paper was arranged by Prof. S. Cristoloveanu
https://doi.org/10.1016/j.sse.2018.05.003
HIGHLIGHTS:
- We report simulations of basic analog and digital circuit blocks employing tunnel-FETs.
- Template III-V heterojunction tunnel-FETs are benchmarked against silicon FinFETs for the 10 nm node.
- Performance are evaluated down to VDD = 200 mV.
- Tunnel-FETs result advantageous with respect to silicon FinFET for VDD below approximately 400 mV.
ABSTRACT: In this work, we investigate by means of simulations the performance of basic digital, analog, and mixed-signal circuits employing tunnel-FETs (TFETs). The analysis reviews and complements our previous papers on these topics. By considering the same devices for all the analysis, we are able to draw consistent conclusions for a wide variety of circuits. A virtual complementary TFET technology consisting of III-V heterojunction nanowires is considered. Technology Computer Aided Design (TCAD) models are calibrated against the results of advanced full-quantum simulation tools and then used to generate look-up-tables suited for circuit simulations. The virtual complementary TFET technology is benchmarked against predictive technology models (PTM) of complementary silicon FinFETs for the 10nm node over a wide range of supply voltages (VDD) in the sub-threshold voltage domain considering the same footprint between the vertical TFETs and the lateral FinFETs and the same static power. In spite of the asymmetry between p- and n-type transistors, the results show clear advantages of TFET technology over FinFET for VDD lower than 0.4V. Moreover, we highlight how differences in the I-V characteristics of FinFETs and TFETs suggest to adapt the circuit topologies used to implement basic digital and analog blocks with respect to the most common CMOS solutions.
FIG: Sketch of n- and p-type TFET and FinFET device architectures. The red and blue colors indicate the n- and p-doping types, respectively (green: intrinsic semiconductor, transparent-grey: oxide). TFET dimensions are: LG=20nm, nanowire cross section (LS)=7nm, EOT=1nm. FinFET dimensions are: LG=14nm, tfin=8nm, hfin=21nm, EOT=0.88nm. (For interpretation of the references to colour in this figure legend, the reader is referred to the web version of this article.)
