[Report] 2nd Latin America MOS-AK Workshop at LAEDC

Recently the 2nd Latin America MOS-AK Workshop at LAEDC was reported in IEEE EDS Newsletter, July 2020 Vol. 27, No. 3 ISSN: 1074 1879 by Lluis Marsal and Benjamin Iñiguez:

The 2nd Latin American edition of the MOS-AK Workshop on Compact Modeling was held at LAEDC in San Jose, Costa Rica, was held in conjunction with the Latin American Symposium on Circuits and Systems (LASCAS 2020).. It was chaired by Prof. Benjamin Iñiguez (Universitat Rovira I Virgili, Tarragona, Spain). It included five talks. Prof. Antonio Cerdeira (CINVESTAV, Mexico) presented an "Analytical Current Voltage Model for Double Gate a-IGZO TFTs with Symmetric Structure." Prof. Alexander Kloes (THM, Giessen, Germany) addressed "Approaches for Analytical (Compact) Modeling of Tunneling Currents in MOS Transistors." Prof. Jean-Michel Sallese (EPFL, Switzerland) gave a talk about "Modeling the Junctionless Ion Sensitive Field Effect Transistor" Prof. Gilson Wirth (UFRGS, Porto Alegre, Brazil) targeted "The area scaling of charge trap induced time-dependent variability." Finally, Prof. Benjamin Iñiguez (URV, Tarragona, Spain) talked about "Characterization and modeling of 1/f noise in organic and IGZO TFTs". Over 70 academics, professionals and students attended these events and enjoyed the discussions with the speakers. 

Visit also <http://www.mos-ak.org/costa_rica_2020/>

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[mos-ak] Fwd: ESSCIRC ESSDERC 2020 | before going on holiday

Are you all set for your well deserved summer holiday? Before you go, have a look at ESSCIRC ESSDERC 2020 Educationals and do not forget to register! 1. TUTORIAL | Quantum Computing: Myth or Reality? 2. WORKSHOP | Emerging Solutions for Imaging Devices, Circuits and Systems 3. WORKSHOP | Non-Volatile Memories: Opportunities and Challenges from Devices to Systems 4. WORKSHOP | New 5G integration solutions, and related technologies (from materials to system) 5. WORKSHOP | Advances in device technologies for automotive industry (power devices, SiC, GaN) 6. WORKSHOP | Embedded monitoring and compensation design for energy or safety constrained applications 7. WORKSHOP | Edge AI and In-Memory-Computing for energy efficient AIoT solutions 8. WORKSHOP | Ab-initio simulations supporting new materials & process developments 9. WORKSHOP | RISC-V cooking session 10. DISSEMINATION WORKSHOP |  Toward sustainable IOT from rare materials to big data 11. DISSEMINATION WORKSHOP | High Density 3D CMOS Mixed-Signal Opportunities 12. MOS-AK WORKSHOP | Compact/SPICE Modeling and its Verilog-A Standardization 13. IPCEI on Microelectronics: Innovative Technologies for Shaping the Future REGISTER NOW! JOIN NOW OUR  ESSCIRC – ESSDERC LinkedIn group! ORGANIZING COMMITTEE Thomas Ernst (CEA-LETI, FR), General co-chair Dominique Thomas (STMicroelectronics, FR), General co-chair François Andrieu (CEA-LETI, FR), ESSDERC TPC Chair Maud Vinet (CEA-LETI, FR), ESSDERC TPC co-Chair Andreia Cathelin (STMicrolectronics, FR), ESSCIRC TPC Chair Sylvain Clerc (STMicrolectronics, FR),  ESSCIRC TPC co-Chair LOCAL EXECUTIVE SECRETARIAT Sandra Barbier (CEA-LETI, FR) | sandra.barbier@cea.fr ORGANIZING SECRETARIAT Sistema Congressi s.r.l. | essxxrc@sistemacongressi.com  ORGANIZERS TECHNICAL SPONSORSHIP FINANCIAL SPONSORSHIP WELCOME OUR DIAMOND SPONSOR! View this email in your browser Copyright © 2020 Sistema Congressi s.r.l., All rights reserved. You are receiving this email because you attended or expressed interest in ESSCIRC-ESSDERC events, or because you are involved in similar fields of research Our mailing address is: Sistema Congressi s.r.l. via Trieste, 26 Padova, PD 35121 Italy Add us to your address book Want to change how you receive these emails? You can update your preferences or unsubscribe from this list.

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Chipmaker #SMIC Eyes China’s Biggest Share Sale in a Decade https://t.co/x7fWlihi15 #semi https://t.co/W5DgoT4Kul

Chipmaker #SMIC Eyes China’s Biggest Share Sale in a Decade https://t.co/x7fWlihi15#semi pic.twitter.com/W5DgoT4Kul

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[paper] Compact Modeling of IGBT

Y. Miyaoku, A. Tone, K. Matsuura, M. Miura-Mattausch, H. J. Mattausch, and *D. Ikoma

Compact Modeling of IGBT Charging/Discharging

for Accurate Switching Prediction

IEEE J-EDS,  DOI:10.1109/jeds.2020.3008919 

Graduate School of Advanced Sciences of Matter, Hiroshima University, Japan

*Denso Corp., Aichi, Japan

Abstract: The trench-type IGBT is one of the major devices developed for very high-voltage applications, and has been widely used for the motor control of EVs as well as for power-supply systems. In the reported investigation, the accurate prediction of the power dissipation of IGBT circuits has been analyzed. The main focus is given on the carrier dynamics within the IGBTs during the switching-off phase. It is demonstrated that discharging and charging at the IGBT’s gate-bottom-overlap region, where electron discharging is followed by hole charging, has an important influence on the switching performance. In particular, the comparison of long-base and short-base IGBTs reveals, that a quicker formation of the neutral region within the resistive base region, as occurring in the long-base IGBT, leads to lower gatebottom-overlap capacitance, thus realizing faster electron discharging and hole charging of this overlap region.

Fig: Studied IGBT structure with indicated current flows

[paper] Vertical III-V Nanowire MOSFETs on Si

Olli-Pekka Kilpi, Markus Hellenbrand, Johannes Svensson, Axel R. Persson, Reine Wallenberg, Erik Lind, Member, IEEE, and Lars-Erik Wernersson

High-Performance Vertical III-V Nanowire MOSFETs on Si With gm > 3 mS/μm

in IEEE EDL vol. 41, no. 8, pp. 1161-1164, Aug. 2020

DOI: 10.1109/LED.2020.3004716

Abstract: Vertical III-V nanowire MOSFETs have demonstrated excellent performance including high transconductance and high Ion. One main bottleneck for the vertical MOSFETs is the large access resistance arising from the contacts and ungated regions. We demonstrate a process to reduce the access resistance by combining a gate-last process with ALD gate-metal deposition. The devices demonstrate fully scalable gm down to Lg = 25 nm. These vertical core/shell InAs/InGaAs MOSFETs demonstrate gm = 3.1 mS/μm and Ron = 190 μm. This is the highest gm demonstrated on Si. Transmission line measurement verifies a low contact resistance with RC = 115 μm, demonstrating that most of the MOSFET access resistance is located in the contact regions.

FIG: (a) of the MOSFET structure demonstrating benefit of the TiN gate metal;

(b )output characteristics of the vertical nanowire MOSFET 

with 90 nanowires, LG = 25 nm and diameter 17 nm.

Acknowledgment: This work was supported in part by the Swedish Research Council, in part by the Knut and Alice Wallenberg Foundation, in part by the Swedish Foundation for Strategic Research, and in part by the European Union H2020 Program INSIGHT under Grant 688784.

“Entrope” High-Frequency #HF #Noise Probe – Device Lab Inc. https://t.co/GSalqQAnX1 #semi https://t.co/rTU6actXHx

“Entrope” High-Frequency #HF #Noise Probe – Device Lab Inc. https://t.co/GSalqQAnX1 #semi pic.twitter.com/rTU6actXHx

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#European Research and Innovation #R&I #Days https://t.co/BR7YIsy2xO #semi https://t.co/qxbrrmOV1j

#European Research and Innovation #R&I #Days https://t.co/BR7YIsy2xO #semi pic.twitter.com/qxbrrmOV1j

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#SOI #Photonics for communication, sensing, and computing markets https://t.co/JFZNFHJkNb #semi https://t.co/fpfZqpGtfW

#SOI #Photonics for communication, sensing, and computing markets https://t.co/JFZNFHJkNb#semi pic.twitter.com/fpfZqpGtfW

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Jerzy Ruzyllo - Guide to Semiconductor Engineering

Guide to Semiconductor Engineering

Jerzy Ruzyllo¹ (Pennsylvania State University, USA)

World Scientific Book Series. March 2020

This Guide to Semiconductor Engineering is concerned with semiconductor materials, devices and process technologies which in combination are the driving force behind the unprecedented growth of our technical civilization over the last half a century. This book was conceived and written keeping in mind those who need to learn about semiconductor engineering, who are professionally associated with select aspects of this technical domain and want to see it in a broader context, or are simply interested in semiconductors. In its coverage of semiconductor engineering this Guide departs from textbook-style, monothematic in-depth coverage of topics such as the physics of semiconductors and semiconductor devices, the manufacturing of semiconductor devices and circuits, and the characterization of semiconductor materials. Instead, it covers the entire field of semiconductor engineering in one concise volume with synergistic interactions between various areas clearly identified. It is a holistic approach to the coverage of semiconductor engineering which makes this guide unique among books covering semiconductor related issues available on the market today. 

[Table of Contents]

¹Jerzy Ruzyllo is a Distinguished Professor Emeritus in the School of Electrical Engineering and Computer Science at the Pennsylvania State University. He joined Penn State in 1984 after completing his education, obtaining a PhD degree in 1977, and serving on the faculty of the Warsaw University of Technology in Poland. Throughout his career, Dr Ruzyllo was actively involved in research and teaching in the area of semiconductor science and engineering. Dr Ruzyllo is a Life Fellow of IEEE and Fellow of the Electrochemical Society.

Jan #Czochralski And The #Silicon #Revolution https://t.co/LMX4tiAuIQ #semi https://t.co/zKPirLDPji

Jan #Czochralski And The #Silicon #Revolution https://t.co/LMX4tiAuIQ #semi pic.twitter.com/zKPirLDPji

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[paper] Compact Source-Gated Sensor

Eva Bestelink, Student Member, IEEE, Kham M. Niang, Georgios Bairaktaris, Luca Maiolo, Francesco Maita, Kalil Ali, Andrew J. Flewitt, S. Ravi P. Silva

and Radu A. Sporea, Senior Member, IEEE

Compact Source-Gated Transistor Analog Circuits for Ubiquitous Sensors

In IEEE Sensors. Jul 18, 2020

Abstract: Silicon-based digital electronics have evolved over decades through an aggressive scaling process following Moore’s law with increasingly complex device structures. Simultaneously, large-area electronics have continued to rely on the same field-effect transistor structure with minimal evolution. This limitation has resulted in less than ideal circuit designs, with increased complexity to account for shortcomings in material properties and process control. At present, this situation is holding back the development of novel systems required for printed and flexible electronic applications beyond the Internet of Things. In this work we demonstrate the opportunity offered by the source-gated transistor’s unique properties for low-cost, highly functional large-area applications in two extremely compact circuit blocks. Polysilicon common-source amplifiers show 49 dB gain, the highest reported for a twotransistor unipolar circuit. Current mirrors fabricated in polysilicon and InGaZnO have, in addition to excellent current copying performance, the ability to control the temperature dependence (degrees of positive, neutral or negative) of output current solely by choice of relative transistor geometry, giving further flexibility to the design engineer. Application examples are proposed, including local amplification of sensor output for improved signal integrity, as well as temperature-regulated delay stages and timing circuits for homeostatic operation in future wearables. Numerous applications will benefit from these highly competitive compact circuit designs with robust performance, improved energy efficiency and tolerance to geometrical variations: sensor front-ends, temperature sensors, pixel drivers, bias analog blocks and high-gain amplifiers.

FIG: a) Photomicrograph of a typical polysilicon SGT fabricated; b) Driver M1 output characteristics (black curves, VGmax = -15 V, step 0.5 V) and superimposed M2 load line (orange, VG = 0 V). VSAT1 occurs as a result from pinch-off at the source and VSAT2 represents channel pinch-off of the parasitic FET. 

Acknowledgment: R.A.S. acknowledges the Royal Academy of Engineering of Great Britain for the support through the Research Fellowship (Grant No. 10216/110), the Royal Society of Great Britain through project ARES IES\R3\170059 and EPSRC for grants EP/R028559/1 and EP/R025304/1. K.M.N. and A.J.F. acknowledge the support of the Engineering and Physical Sciences Research Council (EPSRC) through project EP/M013650/1. R.A.S. thanks Prof John Shannon for technical discussions, Dr Nigel Young and Dr Michael Trainor for assistance with polysilicon device design and fabrication.

#Intel Plunges as It Weighs #Exit From Manufacturing Chips https://t.co/Yxg9KUq5iT #semi https://t.co/fJDOLaFTKD

#Intel Plunges as It Weighs #Exit From Manufacturing Chips https://t.co/Yxg9KUq5iT #semi pic.twitter.com/fJDOLaFTKD

— Wladek Grabinski (@wladek60) July 27, 2020

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[FOSSi] OpenLANE: Open Source 130nm PDK

Join Mohamed Shalan for the 2nd talk in the Free and Open Source Silicon (FOSSi) Foundation Dial-Up series is on Tuesday 28th July, he will talk about OpenLANE on the first-in-the-industry Open Source Manufacturable SkyWater 130nm PDK

Mohamed Shalan - OpenROAD on SkyWater 130nm

Unlike the wider software world, Electronic Design Automation (EDA) open-source landscape has been fragmented for a long time, requiring significant effort and knowledge in a variety of disciplines to assemble a working ASIC flow. This has changed with projects such as Qflow and OpenROAD that aim at developing open-source toolchain for digital layout generation from RTL. OpenLane is an automated RTL to GDSII flow based on available opensource EDA tools configured/tuned for the SkyWater 130nm PDK. OpenLane main objective is to generate a clean layout from RTL designs in less than 24-hours with zero human interventions. OpenLane has been used, successfully, to tape-out a family of test chips (striVe).

Join live on YouTube on Tuesday July 28 at 16:00GMT https://lnkd.in/gCyMuPp

[paper] Vectorizing Device Model Evaluation in Ngspice

Vectorizing Device Model Evaluation in Ngspice circuit simulator

Florian Ballenegger, Anamosic Ballenegger Design

Preprint July 2020

Abstract: A method improving the execution speed of electrical circuit simulation using vector processing is proposed. The BSIM3V32 semi-conductor device model for the open-source Ngspice simulator has been re-written for evaluating multiple device instances of the same model at once using Single Instruction Multiple Data (SIMD) processor instructions. While parallel evaluation of device model was already available using multiprocessing, the proposed method can achieve the same speed-up using less processor resources, thus allowing to do more parallel independent simulations for statistical analysis.

In Conclusion: Only the BSIM3V32 device model was modified to use vector processing. Other device models would of course also benefit from the proposed method. In particular interest would be the EKV model https://github.com/ekv26/model, as the calculations in this symmetric model are more linear with fewer conditional branches and could be vectorized more efficently.  The source code of the modified BSIM3V3 model is available at https://www.anamosic.com/pages/ngspice.html

Softbank talks to #Apple and #Nvidia about #Arm sale https://t.co/pgShLwpAz1 #semi https://t.co/KOS9UIIhO1

Softbank talks to #Apple and #Nvidia about #Arm sale https://t.co/pgShLwpAz1 #semi pic.twitter.com/KOS9UIIhO1

— Wladek Grabinski (@wladek60) July 24, 2020

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U.S. Senators C.Schumer and K.Gillibrand pushed through a massive semiconductor manufacturing incentive package worth as much as $25 #billion that could benefit #GF and #IBM, both are in the Capital Region and the Hudson Valley.https://t.co/lah21UaJsZ #semi https://t.co/Zxeyxds702

U.S. Senators C.Schumer and K.Gillibrand pushed through a massive semiconductor manufacturing incentive package worth as much as $25 #billion that could benefit #GF and #IBM, both are in the Capital Region and the Hudson Valley.https://t.co/lah21UaJsZ#semi pic.twitter.com/Zxeyxds702

— Wladek Grabinski (@wladek60) July 24, 2020

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#Intel conceding the battle to #ARM and #AMD as 7nm processors delayed even further https://t.co/FHOPn7AA0O #paper

#Intel conceding the battle to #ARM and #AMD as 7nm processors delayed even further https://t.co/FHOPn7AA0O#paper

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[paper] Symmetric Source and Drain Voltage Clamping Scheme

K. Xia¹ (Senior Member, IEEE)

Symmetric Source and Drain Voltage Clamping Scheme

for Complete Source-Drain Symmetry in Field-Effect Transistor Modeling

in IEEE Transactions on Electron Devices

DOI: 10.1109/TED.2020.3004799

¹NXP Semiconductors N.V., Chandler, AZ 85224 USA

Abstract: For structurally symmetric field-effect transistors with respect to the source and the drain, their models should be electrically symmetric about the source-drain interchange. This article shows that the commonly used drain-source voltage clamping technique breaks such a symmetry. This article then presents a symmetric source and drain voltage clamping scheme to solve the problem. The effectiveness of the new scheme is demonstrated by both the planar MOSFET model PSP and the FinFET model BSIM-CMG.

Fig: Fourth order derivative of I_x with respect to V_x during Gummel symmetry test for an n-MOSFET on a 130nm technology. V_g = 1.15V. Vb = 0V. W/L = 10.02μm/0.15μm. V_d = −V_s = V_x. T=27^◦C. V_x stepsize is 10mV in the measurement and 0.1mV in the simulation, respectively.

[paper] Compact Model of All-Optical-Switching Magnetic Elements

J. Pelloux-Prayer¹ and F. Moradi¹

Compact Model of All-Optical-Switching Magnetic Elements

IEEE TED, vol. 67, no. 7, pp. 2960-2965, July 2020

DOI: 10.1109/TED.2020.2991330.

¹Department of Engineering, Aarhus University, 8200 Aarhus, Denmark

Abstract: We present, for the first time, a Verilog-A compact model for an all-optically switchable magnetic tunnel junction (MTJ) using results of all-optical-switching (AOS) simulations. Our model is compatible with electronics and photonics design automation tools, and was tested using Cadence Specter and Virtuoso. This compact model can be used to design circuits and systems combining MTJs, photonic circuits, and electronic circuits giving the possibility to researchers working within this field to develop novel circuits and systems.

Fig: Equivalent circuit of the AOS model with LLGS module and LUT module.

Aknowledgement: This work was supported by the European Union’s Horizon 2020 Research and Innovation Programme under Grant 713481.

[paper] LF Noise Characterization of Ge n-Channel FinFETs

Alberto V. de Oliveira (Member, IEEE), Duan Xie (Member, IEEE), Hiroaki Arimura, Guillaume Boccardi, Nadine Collaert, Cor Claeys (Fellow, IEEE), Naoto Horiguchi (Member, IEEE)

and Eddy Simoen (Senior Member, IEEE_

Low-Frequency Noise Characterization of Germanium n-Channel FinFETs

IEEE Transactions on Electron Devices, vol. 67, no. 7, pp. 2872-2877, July 2020

DOI: 10.1109/TED.2020.2990714

Abstract: This article presents an experimental, room temperature, low-frequency noise characterization of germanium n-channel fin-field-effect transistors (finFETs) integrated on silicon. After determining the dominant mechanism in the noise spectrum, the main parameters associated with the noise mechanism are extracted and evaluated as a function of fin width from a planar-like (100 nm) up to narrow fin (20 nm) for 1-µm length devices. The main findings are that the 1/f noise plays an important role in the Ge n-finFETs, whereby the trap density profiles in the gate-stack are quite uniform and have a lower level than in n-/p-channel Ge planar MOSFETs. In addition, a generation-recombination (GR) component was found in 160-nm-length devices, which is caused by GR centers located in the depletion region.

Fig: (a) Schematic of the Ge  n-finFET structure 

and (b) gate-stack composition

Fig: Drain current noise power spectral density as a function of frequency 

for a 160nm long Ge n-finFET

Acknowledgment: The authors would like to thank the Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES) and the Logic IIAP program for the support. This work has been performed in the frame of the imec Core Partner program on Ge devices.

[paper] Thyristor Conduction-Insulated Gate Bipolar Transistor

Mengxuan Jiang¹ (Member, IEEE) and Longjiang Gao¹

Simulation Study of a Thyristor Conduction-Insulated Gate Bipolar Transistor (TC-IGBT) 

with a p-n-p Base and an n-p-n Collector for Reducing Turn-Off Loss," 

IEEE TED, vol. 67, no. 7, pp. 2854-2858, July 2020

DOI: 10.1109/TED.2020.2995343

¹School of Electrical Engineering, Chongqing University, Chongqing 400044, China

Abstract: This article proposes a thyristor conduction-insulated gate bipolar transistor (TC-IGBT) with a p-n-p base and an n-p-n collector to reduce turn-off loss. The parasitic p-collector/n-drift/floating p (FP)-layer/carrier stored (CS)-layer thyristor is activated by the double channel gate and the p-n-p base acts a hole barrier to increase hole concentration at the top side. The n-p-n collector is used for extracting electrons from the n-drift region to decrease hole concentration at the bottom side. Therefore, these two effects form linear and descending hole concentration distribution profile. As a result, the p-n-p base and the n-p-n collector in the TC-IGBT offers lower turn-off loss and turn-off fall time. TCAD numerical simulations show reductions up to 47% (3.15 mJ) and 52% (34 ns) in turn-off loss and turn-off fall time, respectively, when compared to a field stop (FS) IGBT with similar breakdown voltage, threshold voltage, and short circuit time. Therefore, this designed structure may be attractive for power electronics applications.

Fig: (a) Proposed TC-IGBT and (b) its equivalent circuit model

Acknowledgment: This work was supported in part by the National Natural Science Foundation of China under Grant 51707025 and in part by the Chinese Universities Scientific Fund under Grant 106112017 CDJXY150099.

[paper] Unified Analytical Model for SOI LDMOS

Baoxing Duan, Jingyu Xing, Ziming Dong and Yintang Yang¹ (Senior Member, IEEE)

Unified Analytical Model for SOI LDMOS With Electric Field Modulation

IEEE J-EDS, vol. 8, pp. 686-694, 2020

DOI: 10.1109/JEDS.2020.3006293

¹Key Laboratory of the Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices, School of Microelectronics, Xidian University, Xi’an 710071, China

Abstract: The unified analytical model is proposed for SOI LDMOS (Silicon On Insulator Lateral Double-diffused Metal Oxide Semiconductor) based on the electric field modulation in this paper for the first time. The analytical solutions of the surface electric field distributions and potential distributions are derived on the basis of the 2-D Poisson equation. The variation of the buried layer parameters modulates the surface electric field by the electric field modulation effect to optimize the surface electric field distribution of the device. Also, the simulation results obtained through the simulation software ISE are consistent with the expected results of the analytical model. This not only proves the feasibility of the electric field modulation theory, but also shows that the accurate analytical model will be of great guiding significance for designing and optimizing the same LDMOS based on SOI structures.

FIG: Cross-sectional view of electric field modulated SOI LDMOS

Acknowledgment: This work was supported in part by Science Foundation for Distinguished Young Scholars of Shaanxi Province under Grant 2018JC-017, and in part by the 111 Project under Grant B12026.

Fwd: IEEE-EDS SCV/SF Chapter July Distinguished Lecture (Webex only)

Dear IEEE EDS members in Santa Clara Valley/San Francisco Chapter

Please note that this seminar is now WEBEX participation only. 

Differentiated Fully Depleted SOI (FDSOI) Technology for Highly Efficient and Integrated mmWave Wireless Connectivity Solution

Speaker: Dr. Anirban Bandyopadhyay, Director, Strategic Marketing and Business Analytics, GLOBALFOUNDRIES, Inc., Santa Clara, CA

Friday, July 24, 2020 at 12PM – 1PM PDT

WEBEX ONLY: Click Here to Attend

Abstract:

The emergence of enhanced mobile broadband (eMBB) connectivity based on mmWave 5G and the emerging prospect of broadband internet to using non-terrestrial mmwave backhaul using low earth orbit (LEO) satellite generated huge interest in the entire telecommunication ecosystem. While mmwave allows huge bandwidth of channels to enable enhanced broadband, it also poses a lot of technical challenges in terms of coverage, generating enough transmitted power efficiently particularly in the uplink, system cost & scaling and long term reliability of the hardware system particularly for infrastructure including Satellite born systems. Current talk will focus on how Silicon technologies based on differentiated fully depleted SOI (FDSOI) can address the above challenges by enabling a highly efficient and integrated radio without compromising on the mmWave performance and reliability. Talk will highlight the technology Figures of Merits (FOMs) for a mmwave phased array system and how a differentiated FDSOI technology platform compares with other silicon technologies in terms of devices and circuits.

Speaker Bio:

Dr. Anirban Bandyopadhyay is the Director, Strategic Marketing and Business Analytics within the Mobility & Wireless Infrastructure Business Unit of GLOBALFOUNDRIES, USA. His work is currently focused on hardware architecture & technology evaluations for emerging RF and mmWave applications. Prior to joining GLOBALFOUNDRIES, he was with IBM Microelectronics, New York and with Intel, California where he worked on different areas like RF Design Enablement, Silicon Photonics, signal integrity in RF & Mixed signal SOC's. Dr. Bandyopadhyay did his PhD in Electrical Engineering from Tata Institute of Fundamental Research, India and Post-Doctoral research at Nortel, Canada and at Oregon State University, USA. He represents Global Foundries in different industry consortia on RF/mmWave applications and is a Distinguished Lecturer of IEEE Electron Devices Society.

More information at the IEEE EDS Santa Clara Valley-San Francisco Chapter Home Page

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[C4P] Advanced FETs: Design, Fabrication and Applications

Call for Papers: Special MDPI  Issue 

"Advanced Field Effect Transistors: Design, Fabrication and Applications"

Deadline for manuscript submissions: 31 July 2021.

Dear Colleagues,

Planar MOS Field Effect Transistors (MOSFETs) were invented by Atalla and Kahng in 1959. After a decade, the MOSFETs entered mass production, as basic building blocks of P-, N-, and CMOS integrated circuits (ICs). Until the end of the twentieth century, MOSFET performance was largely improved by the implementation of so-called scaling rules. An exponential growth in the time of the transistor number per chip (observation formulated as Moore law) was achieved. This, together with advantageous characteristics and a nice feature of the planar MOSFETs allowing one to design the ICs by defining a width/length ratio, led to the great success of the CMOS technology on Si and SOI substrates.

However, starting from the 90 nm node, it has been observed that the standard scaling does not sufficiently translate into MOSFET performance improvement. Moreover, some device characteristics become degraded, e.g. gate leakage, channel leakage, variability and reliability. This has led to the development of preventative measures (e.g. high-k dielectrics) or performance boosters (e.g. channel strain engineering and channel materials). Furthermore, 2D and 3D multi-gate FETs were introduced to improve gate control over the channel and increase the channel aspect ratio. Multi-gate FETs are the only option for the 5nm node, which is expected soon, whereas they will have to be replaced by surrounding gate FETs for the 3nm node. For the past few years, the attention of researchers has been attracted by steep-subthreshold slope devices, enabling the reduction of supply voltage. A need for devices for quantum computing has appeared. FETs and HEMTs, for very high frequency applications, GaN, SiC and FETs for high voltage, high power, high temperature applications, and many other FET types, are in use or under development as a micro- and nanoelectronics reply to electronics needs in different domains.

There are many issues regarding the design, fabrication and applications of advanced field effect transistors. It is my pleasure to invite you to share your expertise in this Special Issue. Full papers, communications and reviews are all welcome.

Dr. Daniel Tomaszewski, ITE, Warsaw (PL)
Special Issue Guest Editor

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#Free #software is what unites us [Free Software Foundation] https://t.co/EMNQwbkn5Q #opensource https://t.co/oLachje3z4

#Free #software is what unites us [Free Software Foundation] https://t.co/EMNQwbkn5Q#opensource pic.twitter.com/oLachje3z4

— Wladek Grabinski (@wladek60) July 17, 2020

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July 17, 2020 at 06:25PM
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[paper] Compact Modeling of NC FDSOI FETs

C. K. Dabhi, S. S. Parihar, A. Dasgupta and Y. S. Chauhan

Compact Modeling of Negative-Capacitance FDSOI FETs for Circuit Simulations

IEEE TED, vol. 67, no. 7, pp. 2710-2716, July 2020

DOI: 10.1109/TED.2020.2994018

Abstract: The compact model for negative capacitance FDSOI (NC-FDSOI) FET with metal–ferroelectric–insulator– semiconductor (MFIS) gate-stack is presented, for the first time, in this article. The model is developed based on the framework of BSIM-IMG, an industry-standard model (i.e., for zero thickness of a ferroelectric layer, the model mimics the behavior of BSIM-IMG). The developed NCFDSOI model is computationallyefficient and captures drain current and its derivatives accurately. The model shows an excellent agreement with numerical simulation and the measured data of NC-FDSOI FET. The proposed compact model is implemented in Verilog-A and tested for circuit simulations using commercial circuit simulators.

Fig: (a) Schematic of NC MFIS FDSOI FET - FE layer is sandwiched between the oxide layer and the top gate. (b) Gate-stack of MFIS FDSOI FET. (c) Gate-stack of MFMIS FDSOI FET.

Acknowledgment: This work was supported in part by the Swarnajayanti Fellowship and FIST Scheme of the Department of Science and Technology and in part by the Berkeley Device Modeling Center (BDMC). The authors would like to thank Dr. Sarvesh S. Chauhan for reading the manuscript and providing valuable feedback.

[paper] FD-SOI CMOS RF FoM

28-nm FD-SOI CMOS RF Figures of Merit Down to 4.2 K

Lucas Nyssens¹ (Graduate Student Member, IEEE), Arka Halder¹, Babak Kazemi Esfeh¹,
Nicolas Planes², Denis Flandre¹ (Senior Member, IEEE), Valeriya Kilchytska¹
and Jean-Pierre Raskin¹ (Fellow, IEEE)
IEEE J-EDS, vol. 8, pp. 646-654, 2020,
DOI: 10.1109/JEDS.2020.3002201

¹UCL, 1348 Louvain-la-Neuve (B) ²ST-Microelectronics, 38920 Crolles (F)

Abstract: This work presents a detailed RF characterization of 28nm FD-SOI nMOSFETs at cryogenic temperatures down to 4.2K. Two main RF Figures of Merit (FoMs), i.e., current-gain cutoff frequency (f_T) and maximum oscillation frequency (f_max), as well as parasitic elements of the small-signal equivalent circuit, are extracted from the measured S-parameters. An improvement of up to ∼130GHz in f_T and ∼75GHz in f_max is observed for the shortest device (25nm) at low temperature. The behavior of RF FoMs versus temperature is discussed in terms of small-signal equivalent circuit elements, both intrinsic and extrinsic (parasitics). This study suggests 28nm FD-SOI nMOSFETs as a good candidate for future cryogenic applications down to 4.2K and clarifies the origin and limitations of the performance.

FIG: Small-signal equivalent circuit of the RF MOSFETs

Aknowledgement: This work was supported in part by Eniac “Places2Be” and in part by Ecsel “Waytogofast” Projects. The work of Lucas Nyssens was supported by the Fonds de la Recherche Scientifique - FNRS. This paper is based on a paper entitled “28 FDSOI RF Figures of Merit Down to 4.2 K,” presented at the 2019 IEEE S3S Conference.

[FOSSi] #Free #chips courtesy of Google, SkyWater, eFabless https://t.co/sZOyCTuty4 #paper https://t.co/xqwS9nl3Ir

[FOSSi] #Free #chips courtesy of Google, SkyWater, eFabless https://t.co/sZOyCTuty4#paper pic.twitter.com/xqwS9nl3Ir

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July 16, 2020 at 04:15PM
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[paper] Power Side-Channel Attacks in NCFET

Knechtel, Johann, Satwik Patnaik, Mohammed Nabeel, Mohammed Ashraf,

Yogesh S. Chauhan, Jörg Henkel, Ozgur Sinanoglu, and Hussam Amrouch

Power Side-Channel Attacks in Negative Capacitance Transistor (NCFET)

IEEE Micro, DOI 10.1109/MM.2020.3005883

Preprint arXiv:2007.03987 (2020)

Abstract: Side-channel attacks have empowered bypassing of cryptographic components in circuits. Power side-channel (PSC) attacks have received particular traction, owing to their non-invasiveness and proven effectiveness. Aside from prior art focused on conventional technologies, this is the first work to investigate the emerging Negative Capacitance Transistor (NCFET) technology in the context of PSC attacks. We implement a CAD flow for PSC evaluation at design-time. It leverages industry-standard design tools, while also employing the widely-accepted correlation power analysis (CPA) attack. Using standard-cell libraries based on the 7nm FinFET technology for NCFET and its counterpart CMOS setup, our evaluation reveals that NCFET-based circuits are more resilient to the classical CPA attack, due to the considerable effect of negative capacitance on the switching power. We also demonstrate that the thicker the ferroelectric layer, the higher the resiliency of the NCFET-based circuit, which opens new doors for optimization and trade-offs.

Fig: (a) NCFET structure,with ferroelectric layer integrated inside the transistor’s gate stack;

(b) Equivalent caps series, where the internal voltage exhibits a greater voltage (V_int  > V_G)

Acknowledgments: This work was supported in part by the Center for Cyber Security (CCS) at New York University Abu Dhabi (NYUAD). The work of Satwik Patnaik was supported by the Global Ph.D. Fellowship at NYU/NYUAD. Besides, parts of this work were carried out on the HPC facility at NYUAD.

A Cambridge post-graduate student, Marian Rejewski rebuilds Polish Enigma-code-breaking box that paved the way for Turing ... and Victory! https://t.co/hPLDTC9Ocv #paper https://t.co/ZNrvrJN0Zd

A Cambridge post-graduate student, Marian Rejewski rebuilds Polish Enigma-code-breaking box that paved the way for Turing ... and Victory! https://t.co/hPLDTC9Ocv#paper pic.twitter.com/ZNrvrJN0Zd

— Wladek Grabinski (@wladek60) July 15, 2020

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July 15, 2020 at 02:21PM
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[paper] First Principles Based Compact Model for 2D-Channel MOSFETs

Das, Biswapriyo, and Santanu Mahapatra

First Principles Based Compact Model for 2D-Channel MOSFETs

researchgate.net online publication

Abstract: We propose a generalized compact model for any two-dimensional material channel-based metal-oxide-semiconductor field-effect transistors. Unlike existing ones, the proposed model is first principles based and thus has ability to predict the circuit performance only using the crystallographic information of the channel material. It is ‘core’ in nature and developed following the industry-standard drift-diffusion formalism based ‘top-down’ hierarchy employing the FermiDirac statistics. We also implement the model in professional circuit simulator and good convergence is observed in 15-stage ring oscillator simulation.

Fig: Synopsis of the modeling framework. First, certain material specific parameters are extracted employing density functional theory computations and Hamiltonian calibration, which thereafter are used to develop the compact device model of the 2D-channel MOSFET using drift-diffusion formalism. The drain current and terminal charges obtained henceforth are used to implement digital circuits in commercial circuit simulator using its Verilog-AMS interface. 

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[RG] research paper reached 500 citations

FOSS EKV2.6 Verilog-A Compact MOSFET Model

Wladek Grabinski¹, Marcelo Pavanello², Michelly de Souza², Daniel Tomaszewski³, Jola Malesinska³, Grzegorz Głuszko³, Matthias Bucher⁴, Nikolaos Makris⁴, Aristeidis Nikolaou⁴, Ahmed Abo-Elhadid⁵, Marek Mierzwinski⁶, Laurent Lemaitre⁷, Mike Brinson⁸, Christophe Lallement⁹, Jean-Michel Sallese¹⁰, Sadayuki Yoshitomi¹¹, Paul Malisse¹², Henri Oguey¹³, Stefan Cserveny¹³, Christian Enz¹⁰, François Krummenacher¹⁰ and Eric Vittoz¹⁰ 

in 49th European Solid-State Device Research Conference 

(ESSDERC; pp. 190-193)

DOI: 10.1109/essderc.2019.8901822 

FOSS EKV2.6 Verilog-A at GitHub https://github.com/ekv26/model

¹ MOS-AK Association (EU), 
² Centro Universitario FEI, Sao Bernardo do Campo (BR), 
³ Institute of Electron Technology, Warsaw (PL), 
⁴ Technical University of Crete, Chania (GR), 
⁵ Mentor Graphics (USA), 
⁶ Keysight Technologies (USA), 
⁷ Lemaitre EDA Consulting, 
⁸ London Metropolitan University (UK), 
⁹ ICube, Strasbourg University (F), 
¹⁰ EPFL Lausanne, 
¹¹ Toshiba (J), 
¹² Europractice/IMEC (B), 
¹³ CSEM S.A., Neuchatel (CH)