Aug 21, 2026

Fwd: The 4th Annual SemiX Summit - Registrations are open now

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Registrations are now open!

We are pleased to announce that the 4th Annual SemiX Summit will be held at IIT Bombay from October 14–17, 2026 and the registrations for the event are now open. 

Click the button to grab your spot: Register Now

This Summit is especially meaningful for us as it marks the year SemiX transforms from a Research Centre into an Academic Centre

Building on the success of the first three editions, and incorporating valuable feedback from past participants, we have redesigned the Summit program to deliver an even richer experience for students, researchers, entrepreneurs, and industry professionals. 

The key highlights of the 4th summit include: 

1. For the first time, we dedicate one day to students to learn the fundamentals of the semiconductor industry including applications, technologies, entrepreneurship, and career pathways they could potentially explore in the space. 

2. Focus on two key application segments (Power and Artificial Intelligence) to understand their markets, system requirements, and semiconductor technologies from design to manufacturing. 

3. In his keynote address, Raj Nair (SVP, Tata Electronics), will share the execution story of the Tata Fab at Dholera and his insights on the enabling ecosystem and talent for the success of Tata’s plans. 

4. An Entrepreneurship track that will focus on (among other aspects) pre-incubation and how SemiX supports current and future entrepreneurs.

5. A post-summit day for Special Interest Groups to dive deeper into exciting topics in semiconductors. 

The 4th Annual SemiX Summit will continue our tradition of fostering learning, collaboration, and meaningful networking across the semiconductor value chain. We look forward to welcoming you to IIT Bombay! 

Come, let us Realize India's Semiconductor Mission. Together!

Summit Banner

 

Aug 18, 2026

[paper] NetlistBench: SPICE Netlist Evaluation LLM Reliability

Ma, Jiarui, Jianghan Wang, Yuheng Ma, Ziyi Zhuang, and Xiaoguang Liu
"NetlistBench: Evaluating LLM Reliability in SPICE Netlist Recognition and Manipulation" 
In Proceedings of ACM, New York, NY, 8 pages
arXiv: 2608.12197 (2026)

* Southern University of Science and Technology, School of Microelectronics Shenzhen (CN)

Abstract: Large Language Models (LLMs) are increasingly used in circuit design workflows, yet their reliability on simulator-facing SPICE netlist recognition and manipulation remains poorly understood and is rarely separated from high-level design reasoning. Although netlists are textual, they encode structured circuit objects through topology and parameters. We present NetlistBench, a structure verified benchmark for SPICE netlist recognition and manipulation. NetlistBench contains 2,342 cases across 24 task families, covering parameter and connectivity recognition and edits, hierarchical operations, equivalence judgment, and long-horizon compound editing. Model outputs are evaluated by a deterministic structure aware oracle. Across six non-thinking LLMs, performance varies substantially with operation-level structural complexity. Simple local edits reach 96%–100% accuracy, while device addition drops to 41%–83% and equivalence judgment to 49%–90%. Enabling reasoning substantially improves weaker models but does not eliminate structure-preservation failures, with performance still degrading sharply as the edit horizon increases. NetlistBench identifies netlist reliability as a distinct bottleneck for trustworthy LLM-based circuit design automation.

Fig: SPICE netlists as a common representation layer in LLM-based circuit design workflows.



Aug 17, 2026

[C4P] IEEE 18th LASCAS 2027 Panamá City

Call for Papers 
2027 IEEE 18th Latin America Symposium on Circuits and Systems 
LASCAS 2027 Panamá City, Panama
February 23-26, 2027

LASCAS is the flagship symposium of the IEEE Circuits and Systems Society in Latin America. The 2027 edition will take place in Panamá City, a vibrant location known for the Panama Canal, Biomuseo, Amador Causeway, Ancon Hill, the ruins of Panamá Viejo, and the historic district of Casco Viejo.

Technical Areas

  • Analog and Digital Circuits
  • Mixed-Mode Circuits
  • Biomedical Electronics
  • Communication and RF Circuits
  • Wireless Sensor Networks
  • Nanoelectronics
  • Electronic Design Automation
  • VLSI Systems
  • FPGA Design
  • Circuit Testing and Fault-Tolerant Circuits
  • Circuits for Space and Nuclear Applications
  • Circuits for AI

Proceedings will be published by IEEE and available on IEEE Xplore. Selected best papers will be invited to special issues of the IEEE Open Journal of Circuits and Systems. Social activities and tourist tours will be organized for attendees and guests.

Organizing Committee

General Chairs

  • Ivan Armuelles Voinov, Universidad de Panamá, Panama
  • Fakhrul Zaman, Universiti Putra Malaysia, Malaysia

Program Chairs

  • Rafaella Fiorelli Martegani, IMSE‑CNM, Spain
  • Roberto La Rosa, STMicroelectronics, Italy
  • Luis Estrada Petrocelli, Universidad Latina de Panamá, Panama

Important Dates

Paper Submission September 1, 2026
Notification of Acceptance October 23, 2026
Camera‑Ready November 9, 2026

[ICMC] 2026 Award Winners

Thank you to all of the great paper and poster presentations at ICMC 2026!

Below the ICMC 2026 Best Paper Award Winners:
  • Best Paper Award
    Zhengxing Zhang & Substitute Presenter Xu Wang
    Cadence Design Systems, Port Moody, Canada
    “Compact Time-Domain Modeling of Parameterized Frequency-Dependent Photonic Components in Verilog-A”
  • Best Student Paper Award
    Tasnia Jahan
    Arizona State University, Tempe, USA
    “Physics-Informed Neural Networks for Predicting Characteristics of β-Ga2O3 based Devices”
  • Best Poster Award
    Dylan Ma & Substitute Presenter Lan Wei
    University of Waterloo, Waterloo, Canada
    “Virtual-Source-Based Cryogenic FET Model”
and more ICMC2026 photos

Aug 15, 2026

[program] 16th AEC at INAOE


16th Advanced Electronics Congress
<https://www-elec.inaoep.mx/~SEA/2026/>
National Institute of Astrophysics, Optics and Electronics
Luis Enrique Erro No. 1, Tonantzintla, Puebla, México
September 09 - 11, 2026

The Electronics Coordination of INAOE proudly organizes its traditional Advanced Electronics Congress, now in its 16th edition, with the valuable support of the IEEE Electron Devices Society (EDS), the IEEE Instrumentation and Measurement Society (I&M Society), and the IEEE Puebla Section.

Since its inception in 2008, the Congress has aimed to bring together undergraduate and graduate students, researchers, and faculty members in Mexico with internationally recognized experts in the fields of microelectronics, nanoelectronics, integrated circuit design, high-frequency systems, communications, and instrumentation. Guided by this objective, the invited speakers present the most significant recent advances in their respective areas of expertise.

Throughout the Congress’s long history, the program has not only covered specialized topics related to these fields but has also embraced interdisciplinary perspectives in areas such as optics, agriculture, medicine, and a wide range of computer systems applications.

In addition, the Advanced Electronics Congress serves as a forum for interaction among colleagues and students, fostering interinstitutional collaboration and networking opportunities in alignment with the mission and international vision of the IEEE Societies within the IEEE Puebla Section

16th Advanced Electronics Congress Program
(September 09 - 11, 2026)


Time

Topic

Speaker

Institute

08:00 - 09:00 Congress Registration
08:30 - 09:00 Inauguration

09:00 - 10:00

“Las herramientas que mueven el mundo” Dr. Guy Paic Instituto de Ciencias Nucleares (ICN), UNAM

10:00 - 11:00

“Desde la Ciencia de Frontera hasta el Desarrollo Tecnológico: Plataforma de Biosensado Multiespectral para Detección de Pesticidas” Dra. Daniela Díaz Alonso Ibero México, CD-MEMS INAOE

11:00 - 11:30

Break

11:30 - 12:30

“Diseño y caracterización de estructuras integradas para microondas” Dra. Gabriela Méndez Jeronimo CICESE, Ensenada, Baja California, Mexico, INAOE

12:30 - 13:30

“Modelado, prototipado y diseño ASIC para procesadores empleados en PLCs” Dr. Carlos Alberto Hernández Gutiérrez CINVESTAV, CDMX
08:00 - 09:00 Congress Registration

09:00 - 10:00

“Merging Smart Sensors, IoT, AI and Digital Twins Technologies for Digital Transformation in Agriculture” Dr. Octavian Postolache Instituto Universitario de Lisboa. Distinguished Lecturer IEEE Instrumentation and Measurement Society

10:00 - 11:00

“Electrodo de batería de ion litio a base de Silicio con recarga asistida por luz” Dr. Enrique Quiroga González Instituto de Física, BUAP

11:00 - 11:30

Break

11:30 - 12:30

“Aplicación del Control Predictivo a Convertidores CD-CD” Dr. Germán Ardul Muñoz Hernández BUAP, Tecnológico Nacional de México, Puebla.

12:30 - 13:30

“Exploring 22 nm FDSOI Transistors: Electrical Characterization, Reliability, and Temperature Effects” Dra. Paulina Mariana Maya Hernández INAOE
08:00 - 09:00 Congress Registration

09:00 - 10:00

“Processor Validation in Industry in the Age of AI: Challenges, Innovations, and Career Opportunities” Dr. Francisco Elías Rangel Patiño Intel Guadalajara

10:00 - 11:00

“Space Mapping Design Optimization: Power in Simplicity Rooted in Engineering Practice” Dr. José Ernesto Rayas Sánchez ITESO en Guadalajara

11:00 - 11:30

Break

11:30 - 12:30

“Visión por Computadora, FPGAs y Sistemas Embebidos para solución de problemas AgroIndustriales” Dr. Marco Aurelio Nuño Maganda Universidad Politécnica de Victoria
12:30 - 13:30 “Integración de Sensores IoT y Realidad Aumentada para Sistemas Ciberfísicos” Dr. Yehoshua Aguilar Molina Universidad de Guadalajara, Centro Universitario de Los Valles

13:30 - 14:00

Closure

Organizing Committee
  • Dr. Juan Manuel Ramírez Cortés
  • Dr. Roberto Stack Murphy Arteaga
  • Dr. José de Jesús Rangel Magdaleno
  • Dr. José Hugo Barrón Zambrano
  • Dra. Ma. Teresa Sanz Pascual
  • Dr. Mariano Aceves Mijares
  • Dr. Daniel Durini Romero

Contact

Valeria Rodríguez <vrdz@inaoep.mx>



 













© INAOE/AGC 2026

Aug 14, 2026

[release] OpenCircuitX - Free VHDL/Verilog EDA Tool

OpenLabX Launches OpenCircuitX
a Free VHDL/Verilog EDA Tool
<https://github.com/openlab-x/OpenCircuitX>


OpenLabX founder Ahmad Kataranjee has announced the first public release of OpenCircuitX, a permissively licensed electronic design automation suite for VHDL and Verilog FPGA projects. “OpenCircuitX is a free, open-source EDA platform for VHDL and Verilog, the hardware description languages (HDL) used to design digital logic,” Ahmad explains. "It is developed by OpenLabX and unifies an IDE-quality HDL editor, a visual circuit canvas, an RTL schematic viewer, a waveform viewer, and a full FPGA toolchain in one window, for hardware engineers, students, and FPGA hobbyists alike.

“OpenCircuitX is built to grow from digital-only into a full EDA platform,” the developer continues, while admitting that at launch only the digital design domain is available with analog and mixed-signal domains planned to be added in later updates. Ahmad’s creation builds on existing open-source projects including the GHDL VHDL simulator, the Icarus and Verilator Verilog simulators, the Yosys open synthesis suite, nextpnr place and route, and openFPGALoader for board programming. “OpenCircuitX targets FPGA design ([Lattice Semiconductor] iCE40, ECP5),” Ahmad adds, “not ASIC tapeout. That’s not a limitation to apologize for, it’s the space where open-source EDA already works.”

The project’s source code is available on GitHub under the permissive MIT licence.

[read more: https://www.librecores.org/]

[release] IHP Open ADK

IHP Open Assembly Design Kit 
(#OpenAKD)
https://github.com/IHP-GmbH/IHP-Open-ADK


is preview ready and officially available on the IHP GitHub. This release comes with several tools to enable the workflow, including the IHP open source interposer technology process (OpenIntM4TM2). It is Assembly-level Design Kit (OpenADK) for heterogeneous chiplet integration. The OpenADK operates one abstraction layer above all process‑specific PDKs, providing the rule set and assembly tooling that define chiplet placement, routing, and interposer‑level connectivity. The interposer and the chiplet dies remain ordinary PDKs.
Status Warning ADK is currently a preview release only! v0.2.0. The KLayout assembly DRC, its runner, the KiCad DRU generator, and the IHP interposer adapter are implemented and exercised by the regression suite.

● Current ADK documentation
https://ihp-open-adk-docs.readthedocs.io/en/latest/index.html
● Quick start ADK commands
https://ihp-open-adk-docs.readthedocs.io/en/latest/quickstart.html


Aug 13, 2026

[paper] Model for Scaled Cryo FETs

Hyewon Park, Dokyoung Lee, Hyeonsik Ahn, Jusung Kim and Sungho Kim
Physics-based model for scaled cryogenic FETs with band-tail-assisted carrier statistics
SciRep (2026)
DOI: 10.1038/s41598-026-65834-5

1. Division of Electronic and Semiconductor Engineering, Ewha Womans University (KR)
2. Institute for Multiscale Matter and Systems (IMMS), Ewha Womans University (KR)
3. Department of Electronic Engineering, Hanbat National University, Daejeon (KR)

Abstract: Accurate transistor models that remain predictive at cryogenic temperatures are essential for developing large-scale cryogenic complementary metal–oxide–semiconductor platforms that support quantum computing and other low-temperature electronic systems. However, existing cryogenic field-effect transistor (cryo-FET) models struggle to simultaneously reproduce threshold-voltage shifts, gradual subthreshold turn-on, and above-threshold transport in scaled devices because these behaviors originate from distinct physical mechanisms. This study presents a physics-based model for scaled cryo-FETs that integrates the temperature-dependent electrostatic alignment, continuous interface-trap energy distribution, band-tail-assisted carrier statistics, and effective field-dependent mobility degradation within a unified charge-based framework. The model explicitly incorporates bandgap widening and incomplete dopant ionization into the metal–semiconductor work-function difference while representing interface traps through a physically consistent continuous energy spectrum. The study further demonstrates that interface-trap electrostatics alone cannot account for the experimentally observed subthreshold broadening at deep cryogenic temperatures owing to the excessively sharp Maxwell–Boltzmann carrier response. To resolve this limitation, a band-tail-assisted statistical carrier formulation that broadens the subthreshold carrier formation while naturally recovering the conventional conduction-band transport in strong inversion is introduced. The model accurately reproduced the transfer characteristics of 65-nm silicon bulk transistors from 250 K to 12 K over multiple decades of drain current, with excellent agreement in both the threshold behavior and the subthreshold slope. These results establish a physically interpretable and quantitatively accurate modeling framework for scaled cryo-FETs, thereby providing a foundation for predictive cryogenic circuit design and future compact-model development.
Fig.1: Physical origin of transfer-characteristic deviations in scaled cryo-FETs and the corresponding model extensions. Schematic of the logarithmic ID–VG characteristics comparing the measured behavioral characteristics with those of the baseline cryo-FET model. At cryogenic temperatures, the baseline model shows three key mismatches: threshold-voltage shift, overly steep subthreshold turn-on, and inaccurate above-threshold current. These arise from distinct mechanisms. The threshold shift is linked to temperature-dependent electrostatics, including bandgap widening and incomplete ionization. The subthreshold mismatch reflects the sharp Maxwell–Boltzmann carrier response at low thermal voltages, motivating a band-tail-assisted formulation. The above-threshold error results from insufficient transport-field coupling, requiring effective-field-dependent mobility.

Acknowledgements: This work was supported by the National Research Foundation of Korea (NRF) grants funded by the Korean government (MSIT and MOE) (RS-2024-00449412 and RS-2025-16063688). Data supporting the findings of this study are available from the corresponding author upon reasonable request.

Aug 12, 2026

EDKCON 2026 at SMIT on Nov. 12-13

4th IEEE International Conference of Electron Devices Society Kolkata Chapter 
EDKCON 2026
12-13 November, 2026
Sikkim Manipal Institute of Technology (SMIT)
Majitar, 737136 Rangpo, (E) Sikkim, India

Organized by IEEE EDS Kolkata Chapter, EDKCON series of Conferences is expected to bring together researchers, educators, students from across academia, government, industry, and non-governmental organizations to discuss, share and promote current works and recent accomplishments across all aspects of Electron Devices, circuits, Nanotechnology and VLSI. This conference provides a platform for researchers and practitioners to explore how nanometer-scale CMOS transistor technology, advanced memory, displays, sensors, MEMS devices, novel quantum and nano-scale devices, optoelectronic devices, low power devices, high-speed devices, process technology, device modeling and simulation, VLSI and embedded system can drive disruptive advancements for the next generation.

EDKCON 2026 topics of interests:
  • Emerging Devices and Technology
  • Analog/Digital/ Mixed Mode Circuits and Systems
  • Memory Devices and Technology
  • Device Modeling and Simulations
  • Nano-electronic Devices and Technology
  • Advance Processing and Characterizations
  • Device and System Reliability
  • Optoelectronic Devices and Circuits, Displays and Imagers
  • Sensor and MEMS
  • Intelligent Electronic Device, Circuit, and System
  • VLSI System Design and Security
  • Computer-Aided Design for VLSI and Verification
Paper submission deadline: 31st July, 2026  15th August, 2026
Date for acceptance: 30th August, 2026
Registration deadline: 15th September, 2026
Camera-ready paper submission: 10th October, 2026
Conference dates: 12-13 November, 2026


EDKCON-2026 Committee
Chief Patron:
Prof. Dr. K. Ramnarayan, Pro Chancellor, Sikkim Manipal University (SMU)
Dr. Gopalakrishna Prabhu, Vice Chancellor, Sikkim Manipal University (SMU)
Patron:
Prof. Dr. Muralidhar V. Pai, Pro Vice Chancellor, Sikkim Manipal University (SMU)
Prof. Dr. Karma Sonam Sherpa, Registrar, Sikkim Manipal University (SMU)
Prof. Dr. Savitha G. Kini, Director, Sikkim Manipal Institute of Technology (SMIT)
University Advisory Committee: 
Dr. Kalpana Sharma, Director, Directorate of Research, SMU
Dr. Sangeeta Jha, Associate Director (Academics), SMIT
Dr. Chandrashekhar Bhuiyan, Associate Director (Research), SMIT
Dr. Pankaj Chettri, Associate Director (SA), SMIT
General Chairs:
Dr. Bikash Sharma, Head of the Department & Associate Professor,  Dept. of Electronics & Communication Engg., SMIT
Dr. Arpan Deyasi, Associate Professor Department of ECE RCC Institute of Information Technology Kolkata
Dr. Angsuman Sarkar, Professor & Head, ECE Dept., Kalyani Govt. Engg. College, Kalyani, West Bengal
Dr. Manash Chanda, Principal, Meghnad Saha Inst. of Technology, Kolkata

Aug 7, 2026

[mos-ak] [Final Program] 10th China MOS-AK International Conference on Device Modeling


10th China MOS-AK International Conference on Device Modeling
MOS-AK: Enabling Compact Modeling R&D Exchange
August 27-28, 2026 | SEU (Wuxi), Chin

The upcoming MOS-AK event is organized as the 10th China MOS-AK International Conference on Device Modeling and will be held at SEU (Wuxi), China, on August 27-28, 2026. The meeting continues MOS-AK's long-running mission of enabling R&D exchange in advanced electronic and photonic device modeling. The invited participants will cover two groups. The first follows the traditional MOS-AK focus on serving enterprise manufacturers and upstream/downstream model users by discussing practical model-related problems. The second initiative is to train students and professionals in open‑source (FOSS) CAD/EDA tools for integrated circuit (IC) design support.

With aggressive CMOS scaling and diverse emerging device technologies, accurate analytical and compact models have become essential for RF-THz, power, optical, FDSOI/SiGe HBT, 3D heterogeneous integration including OpenPDKs. This workshop offers a focused forum to present and discuss advances in device characterization, compact modeling, simulation, and validation across Si, GaN, IIIV, power, nanoscale, and emerging devices, reinforcing MOS‑AK’s role as a bridge between process technology manufacturing towards advanced circuit and system level designs.

Companies are welcome to showcase their latest tools, equipment, and modeling-related technologies, supporting practical exchange across the compact-modeling industry supply chain.


Important Dates
  • Latest Workshop Program Published: August 2026
  • China MOS-AK International Conference on Device Modeling: August 27-28, 2026
10th China MOS-AK/Wuxi Program is available online

Featured MOS-AK Experts Guests

Portrait of Wei Hong

Wei Hong

Southeast University, China

Portrait of Yue Hao

Yue Hao

Xidian University, China

Portrait of Hanming Wu

Hanming Wu

Zhejiang University, China

MOS-AK Sponsors and Supporting Organizations

We gratefully acknowledge the following sponsors and supporting organizations:

Sponsors

Southeast University logo

JITRI logo

APSTA logo

SiChip Technology logo


Wintech Nano logo

Primarius Technologies logo

PFTN Semiconductor logo


Technical Co-Sponsors

USTC Chapter logo

EDS Nanjing Chapter logo

Shanghai Chapter logo

Nanjing Chapter logo


Supporting Organization

IEEE Nanjing Section logo


Workshop Registration

Registration Fees


WeChat Registration Entry

  • Student RMB 300

  • Non-IEEE member RMB1,000

  • IEEE member RMB800


Registration deadline

August 12, 2026


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Registration QR code:

scan with WeChat

image.png

Mini Program code:

scan with WeChat


MOS-AK/Wuxi Organization Committee


Advisory Committee
Fujiang Lin (USTC)
Technical Program Committee
Yuehang Xu (UESTC)
General Chairs
Weifeng Sun (SEU)
Wladek Grabinski (MOS-AK)
International R&D Adviser
Min Zhang (XMOD)
Finance Chair
Chao Zhu (SEU)
Workshop Secretary
Sonny Lou (APSTA)

WG06082026