[mos-ak] MOS-AK/GSA India workshop on-line publications

MOS-AK/GSA India workshop on-line publications are available, 

visit: 

http://www.mos-ak.org/india/

The Workshop was co-organized by Indian National Academy of Engineering (INAE), supported by Ministry of Communication and IT (DIT), Government of India, Council of Scientific and Industrial Research (CSIR); Jaypee Institute of Information Technology (JIIT), Noida; with sponsorship provided by the microelectronic and semiconductor industry leaders: AMS, IBM, TI, STM, Cadence, Mentor Graphics and Masamb.

I would like to thank all MOS-AK/GSA speakers for sharing their compact modeling competence, R&D experience and delivering valuable MOS-AK/GSA presentations. I am sure, that our modeling event in Noida was a beneficial on to all the attendees as well as to all MOS-AK/GSA Group.

The MOS-AK India workshop press coverage is listed below

http://mos-ak.org/india/press.php

I hope, we would have a next chance to meet us with your academic and industrial partners at future MOS-AK/GSA modeling events (check the list below).

- with regards - WG (for the MOS-AK/GSA Committee) 

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MOS-AK/GSA Dresden April 26-27, 2012 

MIXDES Special Modeling Sesion Warsaw May 24-26, 2012 

MOS-AK/GSA Bordeaux Sept.21, 2012 

MOS-AK/GSA San Francisco Q4 2012 

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PhD course on Nano-scale MOS transistors

Semi-classical modeling and applications
Udine, May 28 - June 1, 2012

Luca Selmi, David Esseni, Pierpaolo Palestri
DIEGM, Università degli Studi di Udine

The course aims at giving a description (in terms accessible to both physicists and electronic engineers) of advanced models for modern nano-MOSFET architectures exploiting technology boosters (strain, high-k materials, etc.) for enhanced channel mobility and reduced leakage. The prerequisite knowledge in physics is limited to the basic concepts of classical electrostatics and electrodynamics and elementary notions of quantum mechanics.

All information dealing with the application for such a scholarship and the eligibility criteria can be found on
http://www.euro-dots.org/Students-rules.asp
and
http://www.euro-dots.org/Students-steps.asp

To register, please call +39 0432 558251 or e-mail it to palestri@uniud.it

DEADLINE FOR ADVANCED REGISTRATION: APRIL 28, 2012

4th Regional Seminar "Computer simulation and design of micro- nano- and microelectromechanical systems"

Natural Sciences Faculty FSEIHPE "State University - teaching, research and production complex"
Physics Department
Teaching and research laboratory instrument-technological modeling of micro-and nano-electronics 

March 30, 2012, Orel, Naugorskoe Av. 29

Seminar Program [translated by Google] 

1. S. Matyukhin ^1, Welcome to the participants
   ¹ State University-UNPK
2. ^A VO Turin, ² Zebra G.I.2 ³ Dorofeev, AA, Device-technological simulation of self-heating in GaN HEMT ,
   ^1-UNPK State University,
   ² NRNU "MiFi"
   ³ 3FGUP NPP "Pulsar"
3. ^A VO Turin, ² Zebra GI, ³ Inigez B3, ^4, Shur MS, Correct account of non-zero differential conductivity in a compact model of MOSFET in saturation due to self-heating effect and because korotkokanalnyh effects ,
   ^1-UNPK State University,
   ² NRNU "MiFi"
   ³ University of Rovira and Virginia, Spain,
   ⁴ Rensselaerovsky Polytechnic Institute, USA
4. Garanovich D. Drozdov, DG, EM Savchenko Design devices from electrostatic discharge protection for bipolar integrated circuits ,
   FSUE NPP "Pulsar"
5. Drozdov, DG, EM Savchenko, Siomko VO Study of models for the calculation of heterostructure transistors based on AlGaN / GaN
   FSUE NPP "Pulsar"
6. Siomko VO, Drozdov, DG, EM Savchenko, Research methods for calculating the breakdown voltage of transistors based on heterostructures AlGaN / GaN
   FSUE NPP "Pulsar"
7. A Kozil Z., S. Birner 2, 3 Dupuis, AR, Nextnano: device-technological modeling of transport in quantum well semiconductor lasers with a double restriction
   ^1-UNPK State University,
   ² Walter Schottky Institut, Technische Universität Munchen, Germany,
   ³ Matco Industries Inc., Scarborough, Ontario, Canada
8. Kozil Z., Differential resistance characteristics of the current-voltage characteristics of semiconductor lasers with a double restriction and optical efficiency
   State University-UNPK
9. Titushkin DA, Matyukhin SI, Modeling of electron-optical system, light-emitting diodes in the package Sentaurus TCAD software company Synopsys ,
   State University-UNPK
10. Makulevsky GR, Malyj DO, Matyukhin S., Investigation of the dependence of characteristics of RO DHS laser waveguide structure by taking into account the thermal effects ,
    State University-UNPK
11. Malyj DO, Makulevsky G.R, Matyukhin SI, Effect of heat on the electrical and optical characteristics of semiconductor lasers, DHS PO using the instrument-technological methods of modeling
    State University-UNPK
12. Tsyrlov AM, Cherkasov, MA, Technical requirements for analysis tools and simulation of high-power devices, switching equipment ,
    JSC «Proton»
13. Chernyshov, KN, Matyukhin S., Computer simulation of the diffusion technology of IGBT ,
    State University-UNPK
14. ^1.2 AA Pisarev, ^a Matyukhin SI, ² Stavtsev AV Computer simulation of the thyristor
    ^1-UNPK State University,
    ² ZAO "Proton-Electrotex"
15. ^A Stoudennikov AS, ^a Turin VO ² Tsyrlov AM, Compact modeling of silicon vertical MOSFET with double diffusion in the program Quite Universal Circuit Simulator
    ^1-UNPK State University,
    ² of "Proton"
16. ¹ Turin, VO, VV Ivanov ^{1, 2} Tsyrlov AM, ³ Martemyanov IS, Simulation of a silicon vertical MOSFET with double diffusion in the program Synopsys TCAD ,
    ^1-UNPK State University,
    ² of "Proton"
    ³ ETU "LETI" 

Job Offer for Compact Modeling (april, 2012)

Remember: we are only re-posting this information, and we're not related to the offer in any other form.

Device Modeling / Compact Modeling Lead / Manager

A top tier Research Group of Semiconductor MNC - Client of HanDigital - Bangalore (Bengaluru Area, India)

Job Description

• Manage and lead a strong technical team to effectively
• Develop compact models for FETs and passive devices like diodes, resistors, inductors , capacitors
• Design testsites and define test programs for RF/DCcharacterization
• Work closely with globally integrated team ofdevice modelers, technology developers and circuit designers
• Client interfacing to address concerns on device models, PDK or circuit performance.

Desired Skills & Experience

Experience : PhD with 10 to 12 Yrs / MS with 12 to 15 Yrs
 
Total Years of relevant experience :Minimum 5 or more years of experience in Device Modeling ; Hands-on experience with RF device / circuit design  and characterization.
 
Technical Knowhow required for the job

• Strong background in semiconductor device physics and characterization particularly in silicon platform is required
• Familiarity with industry standard BSIM or PSP models
• Experience with EDA tools like Cadence, Spectre, HSpice and ADS

Additional Details :

• Excellent written & oral communication skills
• Excellent Technical leadership skills
• Direct working experience with foundries ( Desired ,  Not a Mandatory )

Company Description

Our client is Bangalore based research center is responsible for the definition and development of industry leading technologies such as Copper Interconnect, Silicon onInsulator (SOI), High-Performance Logic-Based Embedded DRAM technologies, and SiGe for RF and analog applications, and high-k material technologies.
 
The research group is also the leading organization in defining the most advanced technologies forthe 45 nm and 22 nm nodes, including research in various aspects of Lithography, strained silicon, and Magnetic RAM (MRAM). The research center develops all of semiconductor technologies including SOI, Bulk CMOS, RFCMOS, HVCMOS,SiGe HBT BiCMOS, and nanodevice technologies.

Additional Information

Posted:

April 5, 2012

Type:

Full-time

Experience:

Mid-Senior level

Functions:

Research, Engineering, Design 

Industries:

Semiconductors 

Compensation:

Best in the Industry

Referral Bonus:

• Applicable

Employer Job ID:

Device / Compact Modeling Manager

Job ID:

2815431

Job Offer in SanDisk (april, 2012)

Remember: we are only re-posting this information, and we're not related to the offer in any other form.

IBIS Models Design Engineer

SanDisk - Bangalore, India (Bengaluru Area, India)

Job Description

In this position, the individual will work in the NAND Flash team to generate IBIS models for the NAND IO’s to be finally used by the internal System team & external customers. In this highly visible role you will perform the following duties:

• Develop IBIS models for the Legacy and DDR IO’s.
• Develop HSPICE models for Legacy and DDR IO’s.
• Interact with the US & the India team.
• Over a period of time develop a team for IBIS models.
• Develop an automated methodology on developing the models

Desired Skills & Experience

This position requires a Bachelor or Master Degree in Electrical/ (Micro) Electronics / VLSI Engineering or equivalent. 2 to 8 years of experience in IBIS models development for the complex Input/Output Buffers. Understanding about the functionality of complex IO’s.Should have deep understanding about HSPICE simulators & IBIS tools e.g Magma Silicon Smart. Excellent Team player.

Company Description

SanDisk Corporation is the global leader in flash memory cards - from research, manufacturing and product design to consumer branding and retail distribution. SanDisk's product portfolio includes flash memory cards for mobile phones, digital cameras and camcorders; digital audio/video players; USB flash drives for consumers and the enterprise; embedded memory for mobile devices; and solid state drives for computers. SanDisk is a Silicon Valley-based S&P 500 company, with more than half its sales outside the United States.

Additional Information

Posted:

April 4, 2012

Type:

Full-time

Experience:

Mid-Senior level

Functions:

Engineering 

Industries:

Semiconductors 

Job ID:

2809898