Will #China succeeds in its #semi strategy and, if so, when? https://t.co/gdbKWp0E3Y https://t.co/maXMpGOsYb
— Wladek Grabinski (@wladek60) Nov 30, 2022
from Twitter https://twitter.com/wladek60
November 30, 2022 at 10:34AM
via IFTTT
Nov 30, 2022
Will #China succeeds in its #semi strategy and, if so, when? https://t.co/gdbKWp0E3Y https://t.co/maXMpGOsYb
from Twitter https://twitter.com/wladek60
November 30, 2022 at 10:34AM
via IFTTT
Nov 29, 2022
#SMIC unveils #12inch #fab expansion project over next 5-7 years https://t.co/CYDh2O94Je #semi https://t.co/CyK7nbzKAK
#SMIC unveils #12inch #fab expansion project over next 5-7 years https://t.co/CYDh2O94Je #semi https://t.co/CyK7nbzKAK
— Wladek Grabinski (@wladek60) Nov 29, 2022
from Twitter https://twitter.com/wladek60
November 29, 2022 at 12:25PM
via IFTTT
#x86 giant says it will tweak spending for #Ohio, #Germany #plants based on ‘market needs’ https://t.co/S4KDODdSN9 #semi #wafers https://t.co/tSDzyQ9xI0
#x86 giant says it will tweak spending for #Ohio, #Germany #plants based on ‘market needs’ https://t.co/S4KDODdSN9 #semi #wafers https://t.co/tSDzyQ9xI0
— Wladek Grabinski (@wladek60) Nov 29, 2022
from Twitter https://twitter.com/wladek60
November 29, 2022 at 08:42AM
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Nov 28, 2022
SILIWIZ
<https://app.siliwiz.com/>
P SUB
nwell
ndiffusion
pdiffusion
pdcontact
ndcontact
nsubstratencontact
psubstratepcontact
polysilicon
polyres
polycontact
metal1
Preset:
Input voltage:
Min: 0V
Max: 5V
Pulse delay: 0 us
Rise time: 50 us
Min: 0V
Max: 5V
Pulse delay: 0 us
Rise time: 50 us
Cross Section View
DRC Errors
✅ DRC OK
#Infineon to use #TSMC #28nm #RRAM technology for next-generation automotive MCU https://t.co/AnfIGbOSLX #semi https://t.co/QSg61yBIJN
#Infineon to use #TSMC #28nm #RRAM technology for next-generation automotive MCU https://t.co/AnfIGbOSLX #semi https://t.co/QSg61yBIJN
— Wladek Grabinski (@wladek60) Nov 28, 2022
from Twitter https://twitter.com/wladek60
November 28, 2022 at 08:42PM
via IFTTT
[paper] Modeling of Nonlinear Thermal Effects in BJT
Analytical Modeling and Numerical Simulation of Nonlinear Thermal Effects in Bipolar Transistors
D'Alessandro, Vincenzo, Ciro Scognamillo, Antonio Pio Catalano, Markus Müller, Michael Schröter, Peter J. Zampardi, and Lorenzo Codecasa
28th THERMINIC (2022), pp. 1-7. IEEE, 2022
DOI: 10.1109/THERMINIC57263.2022.9950637
Abstract: This paper addresses the problem of modeling nonlinear thermal effects in bipolar transistors under static conditions. The impact of these effects on the thermal resistance is explained in detail and analytically modeled using the assumption of a single-semiconductor device. FEM thermal simulations of high-frequency transistors are performed to evaluate the accuracy of the single-semiconductor theory and of the thermal resistance formulations currently employed in the most popular compact transistor models. It is shown that these models do not correctly account for nonlinear thermal effects. Various implementations of the more accurate single-semiconductor theory are then suggested for their future releases.
FIG: (a) geometry of the InGaP/GaAs HBT under test and
(b) corresponding mesh
Acknowledgments: The authors wish to thank Dr. Klaus Aufinger for providing the technology/geometry details of the Si/SiGe HBT analyzed in the paper.
Markus Muller and Michael Schroter acknowledge partial financial support from the Deutsche Forschungsgemeinschaft (project SCHR695/21).
The funding for the Ph.D. activity of Ciro Scognamillo was generously donated by the Rinaldi family in the memory of Niccolo Rinaldi, a bright Professor and Researcher of University of Naples Federico II, prematurely passed away in 2018.
Nov 25, 2022
€45 billion European Chips Act
Envoys from the member states of the European Union #EU have agreed to an amended version of the €45 billion European #Chips #Act on Wednesday, according to Reuters.” https://t.co/P9qULkQYGZ #semi https://t.co/dffa8fHLJn
— Wladek Grabinski (@wladek60) Nov 25, 2022
from Twitter https://twitter.com/wladek60
November 25, 2022 at 03:11PM
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[paper] Quasi-Fermi-Based Charge Transport Scheme for Device Simulation in Cryogenic
Quasi-Fermi-Based Charge Transport Scheme for Device Simulation
in Cryogenic, Wide-Band-Gap, and High-Voltage Applications
Zlatan Stanojevic, Senior Member, IEEE, Jose Marıa Gonzalez-Medina, Member, IEEE,
Franz Schanovsky, Member, IEEE, Markus Karner, Member, IEEE
TechRxiv. Preprint (2022)
DOI:10.36227/techrxiv.21132637.v2
Abstract: We present a novel approach to solving the transport problem in semiconductors. We reformulate the drift-diffusion equations in terms of the quasi-Fermi-energies as solution variables; a drastic increase in numerical stability is achieved, which permits the simulation of devices at cryogenic temperatures as well as wide-band-gap devices using double precision arithmetic, instead of extended precision arithmetic which would otherwise be required to solve these applications using regular drift-diffusion.
FIG: MOSFET transfer characteristics from 300K down to 4K simulated using FVM/SG/QFT at VDS=0.8V; despite only relying on double precision arithmetic, FVM/SG/QFT is capable of calculating contact currents down to 1e-310A.
Nov 24, 2022
[Efabless Corporation] GF 180nm shuttle
[Efabless Corporation] Watch Matt Venn's video on how to submit your design for the #GF #180nm shuttle leaving Dec 5th. Enter for a chance to win a wafer! See video for details <https://t.co/uLP0eWOA6l> #GF #icdesign #hardwaredesign #opensourcecommunity #video #semi https://t.co/OkU562mb6D
— Wladek Grabinski (@wladek60) Nov 24, 2022
from Twitter https://twitter.com/wladek60
November 24, 2022 at 11:44AM
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Fwd: Invitación al seminario en línea
|
#Top10 #Semi Equipment Suppliers
#Top10 #Semi Equipment Suppliers https://t.co/VQ9nDs3ou9 https://t.co/7xqSNzFPd2
— Wladek Grabinski (@wladek60) Nov 24, 2022
from Twitter https://twitter.com/wladek60
November 24, 2022 at 08:47AM
via IFTTT
Nov 14, 2022
Papers Submission at Custom Integrated Circuits 2023
Dear Friends of the Electronics and Custom-Integrated Circuits Design comunity,
Many of our members do Volonteer for the IEEE Custom-Integrated Circuits Conference (CICC). Custom-Integrated Circuits is a strong point of our Academic and Industry landscape. The call for paper is due by 14th of November but is likely to be extended by another 2 weeks. CICC is one of the flagship conference of our professional societies, with a nice impact score (~3), which is a great opportuinity to showcase your research and recent Devellopments.
Topic of interest includes :
- Analog Circuits and Techniques
- Data Converters
- Digital Circuits, SoCs, and Systems
- Emerging Technologies, Systems, and Applications
- Next-generation technology and sensors
- Biomedical circuits, systems, and applications
- Foundation of System Design
- Power Management
- Wireless Transceivers and RF/mm-Wave Circuits and Systems
- Wireline and Optical Communication Circuits and Systems
The detailed call for paper is available online.
We are look forward to receiving contribution from the Switzerland section member through the regular paper submission channels.
Sincerly,
Prof. Taekwang Jang (Solid State Circuit Society Chapter Chair)
Prof. Shih-Chii Liu (Circuit and System and Electron Device Society Joint Chapter Chair)
Switzerland Section : https://ieee.ch/
Manage your IEEE Communication Preferences at the IEEE Privacy Portal
Nov 11, 2022
Fwd: Last Call: ECS 2023 - Boston
243rd ECS Meeting – Boston, May 28 – June 2, 2023
"H02 - Advanced CMOS-Compatible Semiconductor Devices 20"
Abstract Submission Deadline (750 words = 1 page): December 1, 2022
You can also use a single "Image Upload" to include Image, figures, equations, tables if necessary.
Abstract submission: https://ecs.confex.com/ecs/243/cfp.cgi
Do not forget to select H02 symposium for submission…
Full text manuscript: The authors of accepted abstracts should submit the full text manuscript for the ECS Transactions no later than March 16, 2023.
This symposium focuses on studies of new devices, circuits and applications for Moore and More-than-Moore technology, including:
I. More-Moore technology contributing to the semiconductor industry
(a) CMOS compatible devices, circuits and applications:
· SOI devices, advanced Bulk MOSFETs, scaled devices and simulations;
· Multi-gate devices (FinFET, triple gate, nanowire, nanosheet), Junctionless FET;
· high-power devices, semiconductor sensors, Tunnel-FET devices, memory devices;
(b) Device physics and process technology using new materials for noise issues of devices and circuits;
(c) Space applications including low-temperature electronics and radiation hardness
(d) CMOS co-integration of 2D materials (TMDs, etc.)
(e) Self-heating and reliability of scaled MOSFET
(f) Devices with high mobility materials, advanced gate stack
II. More-than-Moore technology
(a) New MEMS applications
(b) Carbon-nanotube and 2D device applications
(c) Sensing applications: Health, environment and security.
(d) Advanced packaging
(e) 2.5D/3D stacking integration
(f) Advanced material and device for Memory, Analog/RF and HV applications
Symposium Organizers:
*Joao Martino (Lead organizer), University of Sao Paulo, Brazil, email: martino@usp.br
*Jean-Pierre Raskin, Universite Catholique de Louvain, Belgium, email: jean-pierre.raskin@uclouvain.be
*Siegfried Selberherr, TU Wien, Austria, email: Selberherr@TUWien.ac.at
*Hiromu Ishii, Toyohashi University of Technology, Japan, email: ishii@ee.tut.ac.jp
*Francisco Gamiz, Universidad de Granada, Spain, email: fgamiz@ugr.es
*Bich-Yen Nguyen, Soitec, USA, email: Bich-yen.Nguyen@soitec.com
*Eddy Simoen, Imec, Belgium, email: eddy.simoen@ugent.be
----------------------------------------
Confirmed INVITED SPEAKERS in alphabetic order by first name:
[1] Dra Bernardette Kunert (Imec, Belgium)
"III-V on Si technologies for 6G electronics"
[2] Prof. Bogdan Cretu (Ensicaen, Caen, France)
"In-deep DC and low frequency noise characterization of double nanosheet FETs DC at room and cryogenic temperatures"
[3] Prof. Cor Claeys (KU Leuven, Leuven, Belgium) – Keynote Speaker
"Technological Challenges and Emerging Device Architectures for Future Semiconductor Micro and Nanoelectronics"
[4] Profa. Cristell Maneux (University of Bordeaux, France)
"RF and mmW technologies"
[5] Prof. Jose Alexandre Diniz (UNICAMP, Brazil)
"ISFET-based Sensors"
[6] Dr. Koen Martens (Imec, Belgium)
"Development of BioFETs based on SOI FinFETs"
[7] Prof. Mathieu Luisier (ETH Zurich, Swiss)
"Modeling of nanoscale devices"
[8] Prof. Prof. Max Fischetti (University of Texas at Dallas, USA)
"The future of nanoelectronics devices s from a theoretical point of view"
[9] Dr. Mikael Cassé (CEA-Leti, France)
"Cryo FD SOI for quantum computing"
[10] Dr. Rüdiger Quay (Fraunhofer Institute for Applied Solid State Physics, Germany)
"Sensor-technology concept and its resource-efficient realization"
[11] Prof. Salvador Gimenez (FEI University Center, Brazil)
"New Layout Styles to Boost the Electrical, Energy, and Frequency Response Performances of Analog MOSFETs"
[12] Dr. Theresia Knobloch (Institue for Microelectronics, TU Wien)
"High-Performance Field Effect Transistors Based on Two-Dimensional Materials"
[13] Prof. Toshihiko Noda (Toyohashi University of Technology, Japan)
"CMOS based multimodal sensing"
[14] Prof. Vihar Georgiev (University of Glasgow, Scotland)
"ISFET for Nano-Biosensing Application"
[15] Prof. Yasuhisa Omura (Kansai University, Japan)
"Potential of Silicon Oxide Films on Low-Cost and High-performance Resistive Switching Devices"
Joao Antonio Martino
Professor Titular
Escola Politécnica da USP
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