Sep 19, 2007
Out-of-Topic: Smiley emoticon
It is a very out-of-topic post, but I think that it is quite important, culturally speaking. Today (September 19th, 2007), this emoticon :-) becomes 25 years old. Visit the homepage of its creator ( Scott E. Fahlman ) for more information.
Sep 18, 2007
ISPSD'09
The 21st IEEE International Symposium on Power Semiconductor Devices and ICs will take place in Barcelona (Catalonia, Spain) on June 14-18.
The deadline for abstract submission is October 24 2008.
ISPSD is the main international conference on the areas of power semiconductor devices, power integrated circuits, their hybrid technologies, and applications.
Topics include: processes, materials, CAD/Simulation, devices, power ICs, packaging and applications.
For researchers interested in compact modeling of power semiconductor devices, ISPSD is a top event to present and get to know the last results in this field. "Device & circuit simulation" is explicitly mentioned as one of the subtopic in the "CAD/Simulation" topic. Compact modeling fits very well this subject. And of course, there is a subtopic of "Modeling" in the "Device" topic.
The Conference will take place mainly at the Axa Winterthur Auditorium but some parallel sessions will be held at the NH Constanza Hotel which is just beside the Auditorium.
Certainly Barcelona is a wonderful place to have such an important event. There are many superb attractions in Barcelona: historical landmarks, the well-known modernistic buildings in Gaudi-style, the "Barri Gòtic" (middle-age downtown), the Museum of Fine Arts, or the stadium of the Barça Football Club. And one can find nice beaches very close to Barcelona. The weather in June is usually very good, warm enough to go to the beach, without been too hot.
The last edition of ISPSD was a success.
The 20th IEEE International Symposium on Power Semiconductor Devices and ICs (ISPSD) was held May 18–22, 2008, in Orlando, Florida, USA.
The venue of ISPSD'08 was the Windham Orlando Resort, a tropical paradise located just outside the entrance to the Walt Disney World in Orlando, Florida.
The General Program Chairman was Professor T. Paul Chow, from the Rensselaer Polytechnic Institute (RPI), in Troy NY. Prof. Chow is a recognized authority in the field of power devices and circuits.
The deadline for abstract submission is October 24 2008.
ISPSD is the main international conference on the areas of power semiconductor devices, power integrated circuits, their hybrid technologies, and applications.
Topics include: processes, materials, CAD/Simulation, devices, power ICs, packaging and applications.
For researchers interested in compact modeling of power semiconductor devices, ISPSD is a top event to present and get to know the last results in this field. "Device & circuit simulation" is explicitly mentioned as one of the subtopic in the "CAD/Simulation" topic. Compact modeling fits very well this subject. And of course, there is a subtopic of "Modeling" in the "Device" topic.
The Conference will take place mainly at the Axa Winterthur Auditorium but some parallel sessions will be held at the NH Constanza Hotel which is just beside the Auditorium.
Certainly Barcelona is a wonderful place to have such an important event. There are many superb attractions in Barcelona: historical landmarks, the well-known modernistic buildings in Gaudi-style, the "Barri Gòtic" (middle-age downtown), the Museum of Fine Arts, or the stadium of the Barça Football Club. And one can find nice beaches very close to Barcelona. The weather in June is usually very good, warm enough to go to the beach, without been too hot.
The last edition of ISPSD was a success.
The 20th IEEE International Symposium on Power Semiconductor Devices and ICs (ISPSD) was held May 18–22, 2008, in Orlando, Florida, USA.
The venue of ISPSD'08 was the Windham Orlando Resort, a tropical paradise located just outside the entrance to the Walt Disney World in Orlando, Florida.
The General Program Chairman was Professor T. Paul Chow, from the Rensselaer Polytechnic Institute (RPI), in Troy NY. Prof. Chow is a recognized authority in the field of power devices and circuits.
Sep 17, 2007
ICCDCS'08
The 7th International Caribbean Conference on Devices, Circuits and Systems has just released the call for papers. This conference is biannually held in different locations near the Caribbean Sea, and is a very inspiring place to present new results. This edition will be held on 28-30 April, 2008, in Cancun, Quintana Roo, Mexico, which is near many interesting archaeological sites, as well as touristic resorts. If you want more information, visit their homepage, but I would not think twice about going there.... (the deadline is on January, 18, so you have plenty of time...)
Sep 16, 2007
New compact modeling papers published in IEEE Transactions on Electron Devices
The September issue of IEEE Transactions on Electron Devices includes an Special Issue on Simulation and Modeling of Nanoelectronics Devices, where most papers are about numeriocal modeling and simulations.
Among the regular papers, there are many about compact modeling. It is certainly a very hot topic!
My former and excellent Ph D student Hamdy Abd El Hamid has published a great work presenting a 3D analytical model for the subthreshold swing in FinFETs. This work was done in collaboration with researchers from the SOI group at the Universite catholique de Louvain: Prof. Denis Flandre and Dr Valeria Kilchytska.
J. Deng and H-S. P. Wong present very interesting analytical models of electrostatic gate capacitance of 1-D field-effect transistors (FETs) with multiple cylindrical conducting channels. The observed agreement with 3D numerical simulations is very good. The paper also shows that effective ways to improve device speed areincreasing the number of channels per gate and reducing the gate height.
R. Kaur et al. present a unified subthreshold model for sub-100-nm nonuniformly doped channel MOSFET. The model is shown to be valid for different lateral and transverse channel-engineered structures, by comparing with 2D simulations. Based on the results obtained, the authors propose a novel device architecture incorporating the benefits of asymmetric halo and LDD doping.
W. Bian et al. present an analytic potential-based model for the undoped surrounding-gate MOSFETs. It is based on the same approach as the paper by D. Jimenez et al,as well as the one by B. Iñiguez et al. but is written on a potential-based formulation.
S. Locci et al. present an analytical model for cylindrical thin-film transistors, which was validated by comparison with experimental results. The authors also compare the performances of cylindrical TFTs with those of planar TFTs.
S. Bayshia et al. propose an analytical subthreshold surface potential model for dual-material gate MOSFETs which considers a varying depth of the channel depletion layer. Good agreement was found with 2D numerical simulations.
A. S. Roy and C. C. Enz develop an analytical large-signal cyclo-stationary low-Frequency noise with arbitrary periodic input. They show that an averaged time constant and an averaged trap density can model the cyclo-stationarity of RTS and flicker noise, respectively.
R. Grazner, F. Schwierz and V. M. Polyakov present an analytical model describing the effects of 2D quantum–mechanical carrier confinement on the threshold voltage of undoped multiple-gate MOSFETs. This model was valiudated by a comparison with self-consistent solutions of 1-D and 2-D Schroedinger and Poisson equations.
M. I. B. Shams et al. show in their paper that in a C-V model of ultrathin gate dielectric MOS devices it is necessary to include the dependence on the barrier height at the Si–dielectric interface and the substrate doping density, and they propose an empirical equation which considers these effects.
S. Kristiansson, F. Ingvarsson and K. O. Jeppsson present a compact spreading resistance model for substrate noise coupling analysis which uses no fitting parameters and is also scalable with the resistivity and thickness of the substrate, as well as with the contact size.
Among the regular papers, there are many about compact modeling. It is certainly a very hot topic!
My former and excellent Ph D student Hamdy Abd El Hamid has published a great work presenting a 3D analytical model for the subthreshold swing in FinFETs. This work was done in collaboration with researchers from the SOI group at the Universite catholique de Louvain: Prof. Denis Flandre and Dr Valeria Kilchytska.
J. Deng and H-S. P. Wong present very interesting analytical models of electrostatic gate capacitance of 1-D field-effect transistors (FETs) with multiple cylindrical conducting channels. The observed agreement with 3D numerical simulations is very good. The paper also shows that effective ways to improve device speed areincreasing the number of channels per gate and reducing the gate height.
R. Kaur et al. present a unified subthreshold model for sub-100-nm nonuniformly doped channel MOSFET. The model is shown to be valid for different lateral and transverse channel-engineered structures, by comparing with 2D simulations. Based on the results obtained, the authors propose a novel device architecture incorporating the benefits of asymmetric halo and LDD doping.
W. Bian et al. present an analytic potential-based model for the undoped surrounding-gate MOSFETs. It is based on the same approach as the paper by D. Jimenez et al,as well as the one by B. Iñiguez et al. but is written on a potential-based formulation.
S. Locci et al. present an analytical model for cylindrical thin-film transistors, which was validated by comparison with experimental results. The authors also compare the performances of cylindrical TFTs with those of planar TFTs.
S. Bayshia et al. propose an analytical subthreshold surface potential model for dual-material gate MOSFETs which considers a varying depth of the channel depletion layer. Good agreement was found with 2D numerical simulations.
A. S. Roy and C. C. Enz develop an analytical large-signal cyclo-stationary low-Frequency noise with arbitrary periodic input. They show that an averaged time constant and an averaged trap density can model the cyclo-stationarity of RTS and flicker noise, respectively.
R. Grazner, F. Schwierz and V. M. Polyakov present an analytical model describing the effects of 2D quantum–mechanical carrier confinement on the threshold voltage of undoped multiple-gate MOSFETs. This model was valiudated by a comparison with self-consistent solutions of 1-D and 2-D Schroedinger and Poisson equations.
M. I. B. Shams et al. show in their paper that in a C-V model of ultrathin gate dielectric MOS devices it is necessary to include the dependence on the barrier height at the Si–dielectric interface and the substrate doping density, and they propose an empirical equation which considers these effects.
S. Kristiansson, F. Ingvarsson and K. O. Jeppsson present a compact spreading resistance model for substrate noise coupling analysis which uses no fitting parameters and is also scalable with the resistivity and thickness of the substrate, as well as with the contact size.
CMRF 2007
The 2007 Workshop on Compact Modeling for RF/Microwave Applications (CMRF'07), organized in conjunction with the IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM2007) will be held on October 3 2007 in Boston, Massachussets.
CMRF 2007 is sponsored by the Delft Institute for Micro-electronics and Submicrontechnology and technically co-sponsored by the IEEE Electron Devices Society.
CMRF is focused on the compact modeling for RF and microwave applications, but not only of bipolar devices. Papers on RF and microwave FET devices can also be presented at CMRF. In fact, CMRF has become a very useful event to get a good picture of the state-of-the-art in this field, and discuss the new trends on compact modeling for RF and microwave applications of all types of devices.
The 2007 edition of CMRF will consist on four sessions: SiGe Compact Modeling, Analog Circuit Verification, III-V compact modeling, and Advanced Characterization and Modeling for RF Power Applications.
Besides, this year CMRF will include a meeting of experts from advanced SiGe technology and from III-V technology.
CMRF 2007 is sponsored by the Delft Institute for Micro-electronics and Submicrontechnology and technically co-sponsored by the IEEE Electron Devices Society.
CMRF is focused on the compact modeling for RF and microwave applications, but not only of bipolar devices. Papers on RF and microwave FET devices can also be presented at CMRF. In fact, CMRF has become a very useful event to get a good picture of the state-of-the-art in this field, and discuss the new trends on compact modeling for RF and microwave applications of all types of devices.
The 2007 edition of CMRF will consist on four sessions: SiGe Compact Modeling, Analog Circuit Verification, III-V compact modeling, and Advanced Characterization and Modeling for RF Power Applications.
Besides, this year CMRF will include a meeting of experts from advanced SiGe technology and from III-V technology.
BCTM'07
The 2007 IEEE Bipolar and BiCMOS Circuits and Technology Meeting (BCTM2007) will be held in Boston, Massachussets, from September 30 to October 3 2007. The conference site will be the Marriot Long Wharf Hotel in Boston.
BCTM is the largest conference in bipolar and BiCMOS technologies and circuits, addressing fabrication, design, performance, testing and applications of bipolar and BiCMOS devices and circuits.
BCTM'07 will include three modeling sessions about bipolar devices: one large signal modeling session, one session about thermal effects, modeling and reliability, and one session about bipolar modeling and characterization. The power device session also incxludes one paper about compact thermal modeling.
In conjunction with BCTM'07, there will be a number of intersting BCTM short courses.
But for compact modeling researchers, the most interesting event held in conjunction with BCTM 2007 is the Workshop on Compact Modeling for RF/Microwave Applications, on October 3 2007.
BCTM is the largest conference in bipolar and BiCMOS technologies and circuits, addressing fabrication, design, performance, testing and applications of bipolar and BiCMOS devices and circuits.
BCTM'07 will include three modeling sessions about bipolar devices: one large signal modeling session, one session about thermal effects, modeling and reliability, and one session about bipolar modeling and characterization. The power device session also incxludes one paper about compact thermal modeling.
In conjunction with BCTM'07, there will be a number of intersting BCTM short courses.
But for compact modeling researchers, the most interesting event held in conjunction with BCTM 2007 is the Workshop on Compact Modeling for RF/Microwave Applications, on October 3 2007.
BMAS 2007
The 2007 IEEE International Behavioral Modeling and Simulation Conference (BMAS 2007) will be held in San Jose, CA, on September 20-21, in conjunction with the 2007 Custom Integrated Circuits Conference (CICC), in the Doubletree Hotel in San Jose, at the heart of Silicon Valley.
BMAS addresses behavioral modeling and simulation for analog electronic circuits and systems. Topics include the development and application of behavioral languages and simulators, modeling practices and automatic extraction of models. Particular focus is placed on the Verilog-AMS and VHDL-AMS languages are of particular interest. The General Chair is Colin C. McAndrew (from Freescale Semiconductor), a recognized authority in the field of compact and behavioral modeling.
This year the BMAS program consists of several interesting sessions: applications of behavioral modeling, behavioral modeling tools, two sessions about behavioral models, and one poster and exhibit session.
Among the models presented in BMAS 2007, we can highlight a liquid crystall cell macro-model with Verilog-A, a SPICE model for piezoelectric transducers, a MEMS accelerometer model, a phase change memory model using Verilog-A, and a behavioral simulation of biological neuron systems using VHDL and VHDL-A.
For compact and behavioral modeling researchers, BMAS is no doubt a very interesting conference to attend, and for circuit designers, it is a very good complement to CCIC.
BMAS addresses behavioral modeling and simulation for analog electronic circuits and systems. Topics include the development and application of behavioral languages and simulators, modeling practices and automatic extraction of models. Particular focus is placed on the Verilog-AMS and VHDL-AMS languages are of particular interest. The General Chair is Colin C. McAndrew (from Freescale Semiconductor), a recognized authority in the field of compact and behavioral modeling.
This year the BMAS program consists of several interesting sessions: applications of behavioral modeling, behavioral modeling tools, two sessions about behavioral models, and one poster and exhibit session.
Among the models presented in BMAS 2007, we can highlight a liquid crystall cell macro-model with Verilog-A, a SPICE model for piezoelectric transducers, a MEMS accelerometer model, a phase change memory model using Verilog-A, and a behavioral simulation of biological neuron systems using VHDL and VHDL-A.
For compact and behavioral modeling researchers, BMAS is no doubt a very interesting conference to attend, and for circuit designers, it is a very good complement to CCIC.
Sep 12, 2007
Paper on de-embedding RF FETs
In this month's issue of Electronics Letters, there is a paper titled "Simplified RF noise de-embedding method for on-wafer CMOS FET", by Xiong, Y.-Z. Issaoun, A. Nan, L. Shi, J. Mouthaan, K. . I think it is interesting enough for all those of you that are using measurements.
Sep 11, 2007
November 2007 issue of IEEE Transactions on Circuits and Systems, Part-I
This issue will be a special issue on circuits and computing architectures in the emerging area of Nanotechnology. Among other, I've found some papers that I think are worth a look:
Title: Modeling of the Electrical Conductivity of DNA
Authors: Vedrana Hodzic, Vildana Hodzic, Robert W. Newcomb
As they say in the abstract: "We have developed a PSpice model of the electrical behavior of DNA molecules for use in nanoelectronic circuit design. To describe the relationship between the current through DNA and the applied voltage we used published results of the direct measurements of electrical conduction through DNA molecules. The experimental dc current-voltage (I-V) curves show a nonlinear conduction mechanism as well as the existence of a temperature dependent semiconductive voltage gap. A weighted least-squares polynomial fit to the experimental data at one temperature, with fitted temperature dependent polynomial coefficient of the linear term, was used as a mathematical model of electrical behavior of DNA. An equivalent electrical circuit was created in PSpice in which DNA was modeled as a voltage-controlled current source described by the mathematical model that includes temperature dependence, GPOLY(T) . Using this model, PSpice simulations with this model generated current-voltage-curves at other temperatures that were in excellent agreement with experimental data"
Title: CNTFET Modeling and Reconfigurable Logic Circuit Design
Authors: Ian O'Connor, Junchen Liu, Frédéric Gaffiot, Fabien Prégaldiny, Christophe Lallement, Cristell Maneux, Johnny Goguet, Sebastien Frégonèse, Thomas Zimmer, Lorena Anghel, Trinh Dang, Régis Leveugle
This paper examines aspects of design technology required to explore advanced logic circuit design using CNTFET devices. An overview of current types of CNTFETs is given and highlights the salient characteristics of each. Compact modeling issues are addressed and new models are proposed implementing (i) a physics-based calculation of energy conduction sub-band minima to allow a realistic analysis of the impact of CNT helicity and radius on the dc characteristics and (ii) descriptions of ambipolar behavior in Schottky-Barrier CNTFETs and ambivalence in double-gate CNTFETs. Using the available models, the influence of the parameters on the device characteristics were simulated and analyzed. The exploitation of properties specific to CNTFETs to build functions inaccessible to MOSFETs is also described, particularly with respect to the use of double-gate CNTFETs in fine-grain reconfigurable logic.
Paper on Science
There is a paper on this month issue of Science from some people of IBM, stating that they have "seen" the dopant distribution in a nano-scale device. The point is, leaving apart the technique, that the dopant does not get an uniform distribution, even after annealing. See the paper: Imaging of Arsenic Cottrell Atmospheres Around Silicon Defects by Three-Dimensional Atom Probe Tomography, by Keith Thompson, Philip L. Flaitz, Paul Ronsheim, David J. Larson, and Thomas F. Kelly
Sep 10, 2007
IEEE Trans. on Electron Devices
This month's issue is a "Special Issue on Simulation and Modeling of Nanoelectronics Devices". That means that I will not look for papers, but I'll only say that all of them are quite interesting. There are papers on threshold voltage modeling, on modeling of statistical variations, on quantum effects,... So, have a look!
Papers on the Applied Physics Letters
I've found some interesting paper on this month's issue:
Estimation of electron traps in carbon-60 field-effect transistors by a thermally stimulated current technique, by Toshinori Matsushima, Masayuki Yahiro, and Chihaya Adachi
Ballistic quantum transport in a nanoscale metal-oxide-semiconductor field effect transistor, by Vijay K. Arora, Michael L. P. Tan, Ismail Saad, and Razali Ismail
Tuning of electrical characteristics in networked carbon nanotube field-effect transistors using thiolated molecules, by Chun Wei Lee, Keke Zhang, H. Tantang, Anup Lohani, S. G. Mhaisalkar, Lain-Jong Li, T. Nagahiro, K. Tamada, Y. Chen
These are three quite different topics, but I think that they are interesting enough.
Estimation of electron traps in carbon-60 field-effect transistors by a thermally stimulated current technique, by Toshinori Matsushima, Masayuki Yahiro, and Chihaya Adachi
Ballistic quantum transport in a nanoscale metal-oxide-semiconductor field effect transistor, by Vijay K. Arora, Michael L. P. Tan, Ismail Saad, and Razali Ismail
Tuning of electrical characteristics in networked carbon nanotube field-effect transistors using thiolated molecules, by Chun Wei Lee, Keke Zhang, H. Tantang, Anup Lohani, S. G. Mhaisalkar, Lain-Jong Li, T. Nagahiro, K. Tamada, Y. Chen
These are three quite different topics, but I think that they are interesting enough.
Sep 6, 2007
IEEE Awards
I've just received the list of the 2007 IEEE Awards, and I wanted to make a comment. First of all, many congratulations to dear Prof. Michael S. Shur, for his two (yes, TWO) awards. The first award is the Leon K. Kirchmayer Graduate Teaching Award, that goes to those able to show inspirational guidance of graduate students in all IEEE fields of interest. Prof. Shur obviously is a most than adequate recipient for this award. His second award (jointly with Arturas Zukauskas) is the Donald G. Fink Prize Paper Award, and goes to the authors of the most outstanding paper published by the IEEE.
I also want to congratulate Prof. Yannis P. Tsividis, who is the recipient of the 2007 Gustav Robert Kirchhoff Award, that goes to those providing outstanding contributions to the fundamentals of any aspect of electronic circuits and systems that has a long-term significance or impact. Again, Prof. Tsividis is a mythical figure in the field of Device Modeling.
In brief, many congratulations for them and for all the other recipients of the IEEE Awards!
I also want to congratulate Prof. Yannis P. Tsividis, who is the recipient of the 2007 Gustav Robert Kirchhoff Award, that goes to those providing outstanding contributions to the fundamentals of any aspect of electronic circuits and systems that has a long-term significance or impact. Again, Prof. Tsividis is a mythical figure in the field of Device Modeling.
In brief, many congratulations for them and for all the other recipients of the IEEE Awards!
Sep 5, 2007
Free Keithley Web Seminar on Measurement
This seminar covers precision test and measurement applications for an emerging class of low cost (<$1000 USD) 6½-digit digital multimeters. Learn how to assemble a testing error budget for various applications for electronic devices and products. Examples include simple test programming to support automatic acquisition and evaluation of measurement data, as well as basic front panel operation.
The seminar will be broadcasted over the internet and requires your registration prior to the event.
When is it?
To register for this FREE webcast seminar click here.
By participating in this seminar, you will learn and understand:
- How to establish a measurement accuracy budget for an application
- How to account for central and parasitic sources of error
- How to match your accuracy requirements with the appropriate DMM
- How to calculate system test uncertainties and errors
This seminar is recommended for development and test engineers and scientists who need to make high precision electrical measurements using widely available, highly accurate 6½-digit DMMs.
About the Presenter:
Chuck Cimino is the Marketing Director for Multi-Application Instruments at Keithley Instruments, Inc. in Cleveland, Ohio. He joined Keithley Instruments in 1981 and has held many positions, including Test Engineer, Design Engineer, Project Manager, and Product Marketer.The seminar will be broadcasted over the internet and requires your registration prior to the event.
When is it?
| Europe: | Thursday, September 13, 2007 15:00 Central European Time (UTC/GMT: 13:00) |
To register for this FREE webcast seminar click here.
Sep 2, 2007
Primer Seminario en Nanoelectrónica y Diseño Avanzado 2007
A friend of mine (Francisco J. Garcia Sanchez) has sent me the announcement of the first Seminar on Nanoelectronics and Advanced Design to be held at the INAOE in Puebla, Mexico. Here you have the link: http://www-elec.inaoep.mx/castour2007
The program is VERY interesting, with five stellar speakers, and, best of all, the admision is free...
P R O G R A M
Dr. Francisco J. Garcia Sanchez, /Universidad Simón Bolivar, Caracas, Venezuela
De la Microelectrónica a la Nanoelectrónica: Una Visión de la Evolución de los Dispositivos Electrónicos.
Prof. Krishnendu Chakrabarty, /Duke University, USA
Modular Testing of Core-Based System-on-Chip Integrated Circuits.
Prof. Rajendra Singh, /Clemson University, South Carolina, USA
Nanotechnology and Pathways to Green Energy Conversion
Prof. Naveen K. Yanduru , /Design Manager, Texas Instruments, Inc. Dallas, Tx, USA
Front-ends in deep sub-micron CMOS with an example of a WCDMA, GSM/GPRS/EDGE receiver front-end without inter-stage SAW filter in 90nm CMOS.
Dr. Mauricio Terrones, /Advanced Materials Department, IPICyT, San Luis Potosí, México.
Recent Advances on N-doped Carbon Nanotubes: Applications and Biocompatibility
For more information:
Dr. J. Alejandro Díaz
ajdiaz@inaoep.mx
Tel y Fax: (222) 2470517
The program is VERY interesting, with five stellar speakers, and, best of all, the admision is free...
P R O G R A M
Dr. Francisco J. Garcia Sanchez, /Universidad Simón Bolivar, Caracas, Venezuela
De la Microelectrónica a la Nanoelectrónica: Una Visión de la Evolución de los Dispositivos Electrónicos.
Prof. Krishnendu Chakrabarty, /Duke University, USA
Modular Testing of Core-Based System-on-Chip Integrated Circuits.
Prof. Rajendra Singh, /Clemson University, South Carolina, USA
Nanotechnology and Pathways to Green Energy Conversion
Prof. Naveen K. Yanduru , /Design Manager, Texas Instruments, Inc. Dallas, Tx, USA
Front-ends in deep sub-micron CMOS with an example of a WCDMA, GSM/GPRS/EDGE receiver front-end without inter-stage SAW filter in 90nm CMOS.
Dr. Mauricio Terrones, /Advanced Materials Department, IPICyT, San Luis Potosí, México.
Recent Advances on N-doped Carbon Nanotubes: Applications and Biocompatibility
For more information:
Dr. J. Alejandro Díaz
ajdiaz@inaoep.mx
Tel y Fax: (222) 2470517
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