[paper] Zener diode compact modeling and simulation

Mike Brinson

Modelling and simulation of Zener diode noise in the time domain

International Journal of Numerical Modelling Electronic Networks Devices and Fields

January 2023

DOI: 10.1002/jnm.3090

1 Centre for Communications Technology, London Metropolitan University, London, UK.

Abstract: This paper presents a new time domain Zener diode compact model for transient noise simulation. SPICE2 and SPICE3 use piece-wise linear time dependent sources for generating complex waveforms. This approach is not practical when applied to randomly generated noise. Today, through on-going improvements to freely available Circuit simulation tools, SPICE noise generation has moved to a new level. Ngspice, for example, computes white Gaussian noise ‘on-the-fly' as transient Simulation progresses. The proposed model has a simple behavioral structure that supports time domain shot, flicker, and thermal noise. The physical properties of the proposed model are introduced in the second section. This is followed by an evaluation of model performance in the third and fourth sections, including static DC, dynamic Charge, and transient noise characterization. Finally, the fifth section summarizes the conclusions of the research.

FIG: QuCS-S/Ngspice Zener diode behavioural model: subcircuit schematic drawing; intermediate equations and limexp function definition.

DATA AVAILABILITY STATEMENT: Data Sharing not applicable to this article as no datasets were generated or analyzed during the current study.

[paper] DMT-core: A Python Toolkit for Semiconductor Device Engineers

Mario Krattenmacher^1,2, Markus Müller^1,2, Pascal Kuthe^1,2, and Michael Schröter^1,2

DMT-core: A Python Toolkit for Semiconductor Device Engineers

Journal of Open Source Software, 7(75), 4298

DOI: 10.21105/joss.04298

1 CEDIC, TU Dresden, Dresden (D)

2 SemiMod GmbH, Dresden (D)

Abstract: Semiconductor device engineers are faced by a number of non-trivial tasks that can be solved efficiently using software. These tasks include, amongst others, data analysis, visualization and processing, as well as interfacing various circuit and Technology-Computer-Aided-Design (TCAD) simulators. In practice, custom ‘home-made’ scripts of varying quality are employed to solve these tasks. It is often found that fundamental software engineering concepts, such as Test-Driven-Development (Shull et al., 2010), or the use of state-of-the-art version control tools (e.g. Git) and practices (e.g. continuous integration, CI), are not utilized by these scripts. The issues inflicted by this practice include:

• The analysis/visualization/generation of data becomes difficult to reproduce.
• Device engineers work far from their maximum work-efficiency, as they are hindered, instead of empowered, by the software infrastructure.
• Knowledge built-up, possibly over decades, may be lost when developers leave a company or institution.

The Device Modeling Toolkit (DMT) presented here aims to solve these issues. DMT provides a Python library that offers:

• classes and methods relevant to commonly used device engineering tasks
• several abstract base classes for implementing new interfaces to various types of simulators
• concrete implementations of the abstract base classes for open-source simulators such as Ngspice (Vogt, 2022), Xyce (Keiter et al., 2014) or Hdev (Müller et al., 2022).

DMT-based simulations allow data generation, workflow implementation and visualization to be implemented in a single file, enabling more efficient cooperation and more reproducible research (Stodden et al., 2016). Basic principles in software engineering, such as unit testing,v ersion control, and documentation, are adhered to so that others can use and contribute to the software.

FIG: DMT interfacing a circuit simulator and corresponding data flow.

Related Publications: DMT is used internally by CEDIC staff in research and by SemiMod for commercial purposes. It has also been used by cooperating institutions and companies. The project has been used inthe following contexts:

• for circuit simulations (Weimer et al., 2022),
• for TCAD simulations and plotting (Markus Muller et al., 2021),
• for circuit and TCAD simulations (M. Muller et al., 2022),
• for model parameter extraction (Müller & Schröter, 2019) and
• for model parameter extraction and TCAD simulation (Phillips et al., 2022).

In addition, DMT has been cited in (Grabinski, 2019; Kuthe et al., 2020; Müller et al., 2019,

2021).

Related Projects: DMT directly uses the VerilogAE (Kuthe et al., 2020) for accessing all information in Verilog-AMS files. The TCAD simulator Hdev (Müller et al., 2022) uses the class DutHdev as its Python interface.

Acknowledgements: This project would not have been possible without our colleagues Dipl.-Ing. Christoph Weimer and Dr.-Ing. Yves Zimmermann. We particularly acknowledge Wladek Grabinski for his efforts to promote the use of open source software in the semiconductor community.

REF:

Shull, F., Melnik, G., Turhan, B., Layman, L., Diep, M., & Erdogmus, H. (2010). What do we know about test-driven development? IEEE Softw., 27(6), 16–19. https://doi.org/10.1109/MS.2010.152
Vogt, H. (2022). Ngspice, the open source Spice circuit simulator - Intro. http://ngspice. sourceforge.net/
Keiter, E. R., Mei, T., Russo, T. V., Schiek, R. L., Sholander, P. E., Thornquist, H. K., Verley, J. C., & Baur, D. G. (2014). Xyce Parallel Electronic Simulator Reference Guide , Version 6 . 2 (September). Sandia National Laboratories (SNL). https://doi.org/10.2172/1826862
Müller, M., Mothes, S., Claus, M., & Schröter, M. (2022). Hdev: A 1D and 2D Hydrodynamic/Drift-Diffusion solver for SiGe and III-V HBTs. J. Open Source Software
Stodden, V., McNutt, M., Bailey, D. H., Deelman, E., Gil, Y., Hanson, B., Heroux, M. A., Ioannidis, J. P. A., & Taufer, M. (2016). Enhancing reproducibility for computational methods. Science, 354(6317), 1240–1241. https://doi.org/10.1126/science.aah6168 
Grabinski, W. (2019). FOSS TCAD/EDA tools for compact modeling. Arbeitskreis Bipolar.
https://www.iee.et.tu-dresden.de/iee/eb/forsch/AK-Bipo/2019/7-MOS-AK-Association_wgr_BipAK19.pdf

[paper] ULTRARAM Memory on Silicon

Peter D. Hodgson, Dominic Lane, Peter J. Carrington, Evangelia Delli, 

Richard Beanland and Manus Hayne

ULTRARAM: A Low-Energy, High-Endurance, Compound-Semiconductor Memory 

on Silicon

First published: 05 January 2022

Adv. Electron. Mater. 2022, 8, 2101103

DOI: 10.1002/aelm.202101103

Abstract: ULTRARAM is a nonvolatile memory with the potential to achieve fast, ultralow-energy electron storage in a floating gate accessed through a triple-barrier resonant tunneling heterostructure. Here its implementation is reported on a Si substrate; a vital step toward cost-effective mass production. Sample growth using molecular beam epitaxy commences with deposition of an AlSb nucleation layer to seed the growth of a GaSb buffer layer, followed by the III–V memory epilayers. Fabricated single-cell memories show clear 0/1 logic-state contrast after ≤10ms duration program/erase pulses of ≈2.5V, a remarkably fast switching speed for 10 and 20µm devices. Furthermore, the combination of low voltage and small device capacitance per unit area results in a switching energy that is orders of magnitude lower than dynamic random access memory and flash, for a given cell size. Extended testing of devices reveals retention in excess of 1000 years and degradation-free endurance of over 107 program/erase cycles, surpassing very recent results for similar devices on GaAs substrates.

FIG: a) Schematic cross-section of ULTRARAM device concept with corresponding material layers. The floating gate (1: FG), triple-barrier resonant-tunneling structure (2: TBRT), and readout channel (3) are highlighted. Arrows indicate the direction of electron flow during program/erase operations; b) Scanning electron micrograph of a fabricated device of 10 µm gate length. 

Acknowledgements: P.D.H. and D.L. contributed equally to this work. This work was supported by the Engineering and Physical Sciences Research Council, UK, via the 2017–2020 Impact Acceleration Account funding allocation to Lancaster University under grant EP/R511560/1, a scholarship under grant EP/N509504/1, equipment funding under grant EP/T023260/1, and the Future Compound Semiconductor Manufacturing Hub grant EP/P006973/1, by the ATTRACT project funded by the EC under Grant Agreement 777222 and by the Joy Welch Educational Charitable Trust.

Mixed Signal SoC design Marathon using eSim & SKY130

Marathon Date : 23 Sept. - 8 Oct. 2022

The following submissions are adjudged as Outstanding, Excellent, Very good and Good by the FOSSEE and the VSD teams.

• Outstanding
• Excellent
• Very Good
• Good

List of Outstanding Circuits:

#	Participant	Circuit	Institute	GitHub
1	Milad Vafaieenezhad	Window Comparator Along with MOD-16 Counter for Counting Based Data Line Selection Operation	Shahed University	View Repo
2	Krunal Badlani	Crack Sensing Circuit	Indian Institute of Technology Hyderabad	View Repo
3	Karuppusamy V	Flash Type ADC	Bannari Amman Institute of Technology	View Repo
4	Inderjit Singh Dhanjal	32-bit SRAM implementation in eSim using Skywater 130nm CMOS technology	K. J. Somaiya College of Engineering	View Repo
5	Tanay Das	Design of a Class D Audio Amplifier IC Using Sliding Mode Control and Negative Feedback	Sikkim Manipal Institute of Technology	View Repo
6	Jayanth Nedunuri	Implementation of 4 bit Two Step Flash ADC	Jyothishmathi institute of Technology and Science	View Repo
7	Aishwarya Balkrishna Patil	Design and Implementation of Automatic Security Monitoring System	Kolhapur Institute of Technology’s College of Engineering, Kolhapur	View Repo
8	Swagatika Meher	3-bit CMOS based TIQ comparator Flash ADC	Odisha University of Technology and Research, Bhubaneswar, Odisha	View Repo
9	Surya V	3-bit Flash ADC using ROM-based Encoder	National Institute of Technology, Tiruchirapalli	View Repo
10	Sanket M Mantrashetti	Design of 8x8 SRAM based on 6T SRAM cell	R. V. College of Engineering	View Repo
11	Avishek Choudhary	10-bit C2C DAC	Thapar Institute of Engineering and Technology	View Repo
12	Nalinkumar S	Implementation of Quadruple - Window Comparator Along with Prioritized MOD-16 Counter for Data Line Multiplexing Operation	Madras Institute of Technology Campus, Anna University	View Repo
13	Rubankumar D	Astable Multivibrator Along with MOD-16 Counter for Counting Based Data Line Selection Operation	Madras Institute of Technology Campus, Anna University	View Repo
14	Vanshika Tanwar	Implementation of 3 Bit Flash ADC performed in eSim	Dronacharya Group Of Institutions, Greater Noida	View Repo
15	Ravi Prakash Vishwakarma	8 Bit Counter/Ramp Type ADC	Madan Mohan Malaviya University Of Technology	View Repo
16	E Balakrishna	Implementation of 4 Bit Flash ADC mixed signal circuit using 130nm performed in eSim	Dronacharya Group of Institution, Greater Noida	View Repo

Contact eSim-fossee:
For more information about the marathon, write to us at contact-esim[at]fossee[dot]in

Call for Papers - IEEE Special Issue of T-ED

Call for Papers - IEEE Special Issue of T-ED on #Semi #Device #Modeling for #Circuit and #System Design Submission Deadline: 30 April 2023 Learn More & Submit: https://t.co/GdNbNufQxH #ElectronDevicesSociety #ElectronDevices #semiconductor #emergingsem…https://t.co/iGSHSjXaxn

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#NIST and #Google to Create New Supply of #Chips for Researchers and Startups

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IEEE EDS MQ at NIT Silchar Silchar, Assam (IN)

IEEE EDS Mini-Colloquium 

on Micro/Nanoelectronics, Devices, Circuits and Systems, 

29-31 Jan 2023 (Hybrid Mode)

DATES	LOCATION	HOST	REGISTER
Date: 29 Jan 2023 Time:10:00AM to 06:00PM  (UTC+05:30)  Add Event to Calendar  iCal  Google Calendar	National Institute of Technology Silchar Dept of ECE, NIT Silchar Silchar, Assam India 788010 Building: ECE/CSE Building	National Inst of Technology - Silchar, ED15 Kolkata Section Chapter NANO42 Co-sponsored by Dr. Trupti R. Lenka	Starts Dec.1, 2022 Ends Jan.28,2023 No Admission Charge Register NOW

Agenda with following contribution Distinguished Lecturers: 

• Anil Kottantharayil (anilkg@ieee.org)
• Gananath Dash (gndash@ieee.org)
• Ajit Kumar Panda (akpanda62@hotmail.com)
• Manoj Saxena (msaxena@ieee.org)
• Brajesh Kumar Kaushik (bkkaushik23@gmail.com)
• Samar Saha (samar@ieee.org)
• Hiroshi Iwai (h.iwai@ieee.org)
• Taiichi Otsuji (taiichi.otsuji.e8@tohoku.ac.jp)
• Pei-Wen Li (pwli@nycu.edu.tw)
• Zhou Xing (EXZHOU@ntu.edu.sg)
• Albert Chin (albert_achin@hotmail.com)
• Mansun Chan (mchan@ust.hk)
• Chao-Sung LAI (cslai@mail.cgu.edu.tw)
• Wladek Grabinski, MOS-AK, EU (wladek@grabinski.ch)

Register NOW

Neural networks and machine learning approach for compact modeling

[NN] Wang, Qiuwei, Mao Ye, Yao Li, Xiaoxiao Zheng, Jiaji He, Jun Du, and Yiqiang Zhao. "MOSFET modeling of 0.18 μm CMOS technology at 4.2 K using BP neural network." Microelectronics Journal (2023): 105678. DOI: 10.1016/j.sse.2022.108580

Highlights

• The cryogenic characterization of SMIC CMOS technology at 4.2K is presented.
• An optimization model VCCS is proposed to calibrate the cryogenic characteristics.
• BP neural network is, for the first time, used in MOSFET modeling.
• The cryo-model can be applied to SPICE simulator and assist in cryo-CMOS circuit design and simulation.

Fig: The structure of graph-based compact model of FinFET. The model receives the input features such as voltages, geometries, etc. as a vector and predicts the drain current (Ids) and its derivatives as output features.

[ML] Gaidhane, Amol D., Ziyao Yang, and Yu Cao. "Graph-based Compact Modeling (GCM) of CMOS transistors for efficient parameter extraction: A machine learning approach." Solid-State Electronics (2023): 108580.

Highlights

• Developed a Graph-based compact model for FinFET.
• Model implemented in Verilog-A for SPICE simulation.
• Requires less number of model parameters and is computationally efficient than BSIM

[mos-ak] [Prennouncement] 7th Sino MOS-AK Workshop in Nanjing (CN)

Arbeitskreis Modellierung von Systemen und Parameterextraktion

Modeling of Systems and Parameter Extraction Working Group

7th Sino MOS-AK Workshop in Nanjing (CN)

scheduled for August 11-13, 2023 (online/onsite)

Preannouncement and Call for Papers

Together with local host, as well as all the Extended MOS-AK TPC Committee, would like to invite you to the 7th Sino MOS-AK Workshop in Nanjing (CN) which will be organized as the online/onsite event on August 11-13, 2023 providing an opportunity to meet the internation modeling experts, engineers and researchers. A training course related to SiC topic (device modeling, packaging models, circuits, modules and final application) is planned for the first MOS-AK day, following by two days of the MOS-AK compact/SPICE modeling and its Verilog-A discussions. 

Upcoming, subsequent 7th Sino MOS-AK Workshop in Nanjing (CN) aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring academic and industrial experts in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors, in particular using Free open source PDKs.

Topics to be covered include the following among other related to the compact/SPICE modeling and its Verilog-A standardization:

• Compact Modeling (CM) of the electron devices
• Advances in semiconductor technologies and processing
• Verilog-A language for CM standardization
• New CM techniques and extraction software
• Open Source (FOSS) TCAD/EDA modeling and simulation
• CM of passive, active, sensors and actuators
• Emerging Devices, Organic TFT, CMOS and SOI-based memory
• Microwave, RF device modeling, high voltage device modeling
• Nanoscale CMOS, BiCMOS, SiGe, GaN, InP devices and circuits
• Technology R&D, DFY, DFT and reliability/aging IC designs
• Foundry/Fabless Interface Strategies (eg: using Free open source PDKs)

Important Dates:

• Call for Papers - Jan 2023
• 2nd Announcement - April 2023
• Final Workshop Program - July 2023
• 7th Sino MOS-AK Workshop -  Aug. 11-13, 2023 (online/onsite)

[C4P] IEEE AUTOTESTCON 2023

Deadline to submit abstracts is 15 February 2023

View this email in your browser Call For Papers AUTOTESTCON is the world's premier conference that brings together the military/aerospace automatic test industry and government/military acquirers and users to share new technologies, discuss innovative applications, and exhibit products and services. It is sponsored annually by the Institute of Electrical and Electronic Engineers (IEEE).   AUTOTESTCON will be held at the Gaylord National Harbor Resort, National Harbor, MD, USA, on August 28-31, 2023. The technical program for AUTOTESTCON 2023 will be determined by the interests of those participants submitting for publication, presenting a technical paper, or organizing a technical session. Papers and sessions should cover appropriate topics dealing with increasing DoD systems availability and automatic test technology in particular. Learn More Key Topics » Spiral Development and Evolutionary Acquisition » Flexible Sustainment » Interoperability » Design-For-Test/Built-In-Test » Fault Tolerant Systems » Legacy ATE Challenges » Future Logistics Support Concepts » Contractor Logistics Support » Maintenance Repair & Overhaul » Multinational Integrated Support » Commercialization of Military Maintenance » Electronic Warfare Test and Applications » CMMI Application to ATE/TPS Development » DMSMS Approaches » Organizational, Intermediate, Depot Level Maintenance For The Future » Next Generation Test Systems » Test Program Set Development » Prognostics » Test Requirements Definition and Verification » Factory and Development Test » Software Testing and Research » Development in Instrumentation and Measurement Download CFP Submission Information Abstracts are to be submitted to EDAS no later than February 15, 2023. Submit Paper(s) Here Questions? Website Email Sponsors Copyright © 2023 IEEE, All rights reserved. You are receiving this email because of your membership in IEEE Aerospace & Electronics Systems Society. Our mailing address is: IEEE 445 Hoes Lane Piscataway, NJ 08854-4141 USA IEEE Private Policy Want to change how you receive these emails? You can update your preferences or unsubscribe from this list.

Untether #AI #SDK Allows Bare-Metal #Programming

Untether #AI #SDK Allows Bare-Metal #Programming https://t.co/bvY91RKIpi #semi https://t.co/9PjNvyah6G

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January 17, 2023 at 09:29PM
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UPCOMING – Winter School in III-Sb applications

UPCOMING

Winter School in III-Sb applications: non-volatile memories

A Modelling Perspective

QUANTIMONY’s Winter School in III-Sb Applications: non-volatile Memories: a Modelling Perspective will take place from February 27th to March 3rd 2023 at the premises of the Technical University of Berlin.

The 5-day event will focus on the design and scalable production of a new III-Sb patented memory device (ULTRARAM TM). There will be a combination of specialised lectures by international experts, and hands-on tutorials/lab sessions as well as live demonstrations of the latest TCAD/EDA tools organised by the Technical University of Berlin.

The event will provide with an excellent opportunity for networking with leaders in the field.

List of Confirmed Speakers Invited Speakers and Hands - on Session:

• Prof. Dr. Manus Hayne, Lancaster University Birth of the ULTRARAM TM Concept
• Prof. Dr. Dieter Bimberg, Technische Universität Berlin Quantum Dot-Based Flash Memories: The Holy Grail at Sunrise?
• Dr. Petr Klenovský, Masaryk University, Brno Modeling Electronic states of IlI-Sb guantum systems on GaP substrate
• Dr. Wladek Grabinski, MOS-AK (EU) FOSS TCAD/EDA Tools for Compact Modeling
• Prof. Vihar Georgiev, James Watt School of Engineering, Glasgow Nano-electronic Simulation Software (NESS): a flexible nano-device simulation platform
• PD Dr. Uwe Bandelow, WIAS Berlin TBA
• Prof. Claudia Dr.axl, Humboldt Universität Berlin Unsupervised learning for insight into high-throughput calculations
• Rabea Pons, Comsol, Göttingen Introduction into COMSOL and hands-on session
• Prof. Dr. Mathieu Luisier, ETH Zürich TBA
• Dr. Marc Bescond, Faculté des Sciences de Saint Jérôme, NQS group, Marseille TBA
• Dr. Chetan Gupta, Micron Technology (R&D) Industry perspective on memory technologies
• Prof. Dr. Jannik Wolters, Deutschen Zentrum für Luft- und Raumfahrt / TU Berlin Quantum Memories and Introduction into Quantum Technologie

More information 

33rd IEEE MIEL 2023

We would like to inform you that 33rd IEEE International Conference on Microelectronics (MIEL 2023) will be held in Niš from October 16th-18th, 2023.

Accepted papers will be published in the Proceedings of the MIEL 2023 Conference, and included in IEEE Xplore database, subject to regular registration of at least one of the authors before August 31st, 2023.

We are pleased to invite you, as an expert in the field of microelectronics, to submit a paper to MIEL 2023 Conference and to encourage colleagues to do it. The deadline for the submission of two page-extended summaries (including figures, tables, and references) is April 28th, 2023.

Important Dates

• December 31, 2022 First Announcement and Call for Papers
• April 28, 2023 Deadline for Receipt of Abstracts
• June 23, 2023 Notification on Acceptance of Papers
• August 31, 2023 Deadline for registration
• August 31, 2023 Deadline for Receipt of Papers
• September 22, 2023 Dispatch of Conference Programme

Looking forward to receiving your abstract for MIEL 2023 Conference, we remain with

Best regards,

Vojkan Davidović
Danijel Danković

http://miel.elfak.ni.ac.rs/
Please contact miel@elfak.ni.ac.rs for further information.

#TSMC is mulling an automotive #semi #fab in #Europe https://t.co/TDeiZXztLu https://t.co/MQ3nH0XlOR

#TSMC is mulling an automotive #semi #fab in #Europe https://t.co/TDeiZXztLu https://t.co/MQ3nH0XlOR

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[Paper] Time-Efficient Adaptive Procedure for Identification of Multitone X-Parameters

Konstanty Łukasik , Graduate Student Member, IEEE, Paweł Barmuta , Member, IEEE,

Troels S. Nielsen, Member, IEEE, Wojciech Wiatr , Life Member, IEEE,

and Dominique M. M.-P. Schreurs, Fellow, IEEE,

"Time-Efficient Adaptive Procedure for Identification of Multitone X-Parameters" 

in IEEE Transactions on Instrumentation and Measurement, 

vol. 72, pp. 1-9, 2023, Art no. 1000609,

DOI 10.1109/TIM.2022.3232171.

Abstract: A novel measurement procedure for the time-efficient identification of multitone X-parameters of active microwave devices and circuits is introduced. Over a given bandwidth, the procedure allows for an adaptive selection of key spectral components necessary for determining the X-parameters characteristics with a minimum measurement effort. The sequential selection is based on the divide-and-conquer algorithm. It results in a huge reduction of the measurement time in comparison to the situation when model coefficients at all spectral components are identified. To validate the procedure, an off-the-shelf broadband power amplifier (PA) was characterized under wideband large-signal excitation conditions. Moreover, small-signal terms at all relevant frequencies were collected as a reference and compared with the results provided by a time-efficient adaptive procedure (TEAP). The proposed method resulted in twenty times reduction in the number of samples required to characterize the PA. As an application example, the small-signal coefficients identified with the TEAP are used to correct characterization results for the measurement instrument’s output mismatch. The mismatch-corrected output signal of the PA under test was represented accurately with the error-vector-magnitude of only 0.132%.

FIG: Block diagram of the measurement setup used for performing experiments.

[paper] Discovery of Clustered-P1 Borophene and Its Application as the Lightest High-Performance Transistor

[paper] Sirsha Guha, Arnab Kabiraj, and Santanu Mahapatra; Discovery of Clustered-P1 Borophene and Its Application as the Lightest High-Performance Transistor; ACS Appl. Mater. Interfaces 2023, https://t.co/bXA5IFpJVZ https://t.co/ekkSO8Ru8T #semi https://t.co/pyinJ5fvMQ

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At the outer edges of Moore’s Law

At the outer edges of Moore’s Law, connecting components is increasingly the game https://t.co/7Tu0CgD60N #semi #interconnects https://t.co/OSFntG8sJ5

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A #Bayesian machine based on #memristors https://t.co/i3BwR9lwVH #semi https://t.co/UQS1FXiu4N

A #Bayesian machine based on #memristors https://t.co/i3BwR9lwVH #semi https://t.co/UQS1FXiu4N

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[ISSCC] First Annual EPFL and ETHZ Friend and Alumni Aperitif

This year at ISSCC 2023, EPFL and ETHZ will host our First Annual Friend and Alumni Aperitif! It is open to all our friends and those who wish to network with us. The event will also be a celebration of Prof. Christian Enz and Prof. Qiuting Huang's retirement, so please spread the word to your network :)

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Event Details

Time: Monday (Feb 20th) 5-8pm
Location: San Francisco Marriott Marquis, 2nd floor Foothill D

There will be food and an open bar!