[C4P] ICEE 2025

7th International Conference on Emerging Electronics (ICEE 2025)

Hilton Embassy Manyata Business Park, Bengaluru (IN)

December 13-16, 2025

Upcoming ICEE 2025 is a flagship IEEE EDS four-day conference, organized to foster cutting-edge discussions and collaborations in semiconductor technologies. ICEE 2025 will feature a diverse range of sessions, including, Technical and rump sessions, Industry-academia discussions, Plenary talks by distinguished experts, Policy sessions on the future of semiconductor technologies.

ICEE 2025 invites papers (4 page Abstract submission deadline: August 1st 2025) on a diverse and comprehensive range of topics that span materials, processes, devices, circuits, systems, modeling, and reliability. This program is curated by an international team of academic and industry leaders. This edition of ICEE is especially important, given the ambitions of major global economies (such as USA, EU, Japan, India, etc.) in semiconductor manufacturing. This focus is reflected in the composition of ICEE's technical program and organizing committee, with top industry leaders on board. ICEE'25 edition plans to offer 3 Plenary Talks, 5 Keynote Talks, 150+ Invited and Platform/Oral Talks, 100+ Posters, Tutorial Sessions, Evening Industry Sessions, and Industry Exhibits with 800+ International Audiences and Industry Participation. The conference will offer opportunities to contribute, network, learn, collaborate and grow in the areas listed below. For the contributed papers, please find below the call for paper, ICEE themes/tracks, submission guidelines and 4-page abstract templates. In case of questions, please feel free to write to us at secretary@ieee-icee.org. Please keep checking the website and our social media handles for new updates [read more]

[C4P] ICMC 2025

STRENGTHENING MODELING COLLABORATION WITH THE SEMICONDUCTOR INDUSTRY

International Compact Modeling Conference (ICMC 2025)

June 26-27, 2025; The Clift Royal Sonesta, San Francisco

IMPORTANT DATES Abstract Submission Deadline January 15, 2025 Acceptance Notifications March 10, 2025 Full Paper Submission Deadline April 20, 2025 ORGANIZING COMMITTEE General Chair Peter M. Lee Micron  Vice Chair Shahed Reza Sandia Lab Technical Program Chair Colin Shaw Silvaco Technical Program Vice Chair Gert-Jan Smit NXP  Treasurer Leigh Anne Clevenger Si2 Secretariat Conference Catalysts icmc@conferencecatalysts.com

The Compact Model Coalition (CMC) brings academia and industry partners together in the development and standardization of compact models for semiconductor devices. For 30 years now, the CMC has been instrumental in creating standardized and verified models for designers to use in their increasingly complex circuits for SPICE simulation. The CMC is organizing a new and innovative International Compact Modeling Conference. Cosponsored by IEEE EDS, it will focus uniquely on compact device models, their development and broad application in the semiconductor industry. You are invited to participate in the evolution of these models, guide model development to help circuit designers create the best circuit performance possible, and enable foundries to leverage the strength of their device fabrication to full extent. Join the world experts in design, process technology, and model development to discuss state-of-the-art semiconductor device modeling for a two-day in-person event in one location, offering a great opportunity to present and learn about this core element of circuit design and how to get the most from these global collaborations. We are seeking papers for oral or poster presentations in the following areas: APPLICATION OF DEVICE MODELS Innovative application of CMC standard device models Best practices, novel use, and benefits of standard device models in circuit design Use of compact models to demonstrate foundry device capabilities DEVICE MODEL DEVELOPMENT Modeling of physical phenomena: Statistical variation, reliability and aging, noise and fluctuations, high frequency effects, Electrostatic Discharge (ESD), self heating, layout effects, etc. Methodologies to assist in model development, practices for coding, quality assurance, circuit simulator integration, etc. Parameter extraction, measurement techniques, model calibration, validation, and verification methodologies, including solutions based on AI or Machine Learning. MODEL ENHANCEMENTS AND IMPLEMENTATIONS Model extensions to capture additional device features (leakage, noise, capacitance, second-order dependencies, …) or expand the operating range of existing devices (bias, power, temperature, frequency, etc.) Model enhancements to support the design of new or demanding circuits Model workflow, implementation, and integration into the design environment (PDK) Computing/simulation platforms, simulation algorithms, and methodologies to improve simulation performance (parallel processing, etc.) Models for established device types that currently lack standardization. MODELING FOR FUTURE/EMERGING TECHNOLOGIES AND APPLICATIONS Models for emerging device types or architectures on the horizon, such as, ferroelectric devices, silicon photonics, cryogenic, quantum computing, etc. Modeling of new physical phenomena in support of current and novel device technologies Novel device technologies currently being researched that could further revolutionize circuit performance, have implications in the design flow, and may become mainstream in the future Please submit your paper proposals in the form of a 2-page abstract for review by January 15, 2025 here 2025.si2-icmc.org. Acceptance notifications will be sent by March 10, 2025. Accepted contributions (for both oral and poster presentations) are expected to submit a camera-ready 4-page draft version of their papers by April 20, 2025 and final version by May 23, 2025 for publication in IEEE Xplore®.

[C4P] International Compact Modeling Conference

STRENGTHENING MODELING COLLABORATION WITH THE SEMICONDUCTOR INDUSTRY

International Compact Modeling Conference (ICMC 2025)

June 26-27, 2025; The Clift Royal Sonesta, San Francisco

IMPORTANT DATES Abstract Submission Deadline January 15, 2025 Acceptance Notifications March 10, 2025 Full Paper Submission Deadline April 20, 2025 ORGANIZING COMMITTEE General Chair Peter M. Lee Micron  Vice Chair Shahed Reza Sandia Lab Technical Program Chair Colin Shaw Silvaco Technical Program Vice Chair Gert-Jan Smit NXP  Treasurer Leigh Anne Clevenger Si2 Secretariat Conference Catalysts icmc@conferencecatalysts.com

The Compact Model Coalition (CMC) brings academia and industry partners together in the development and standardization of compact models for semiconductor devices. For 30 years now, the CMC has been instrumental in creating standardized and verified models for designers to use in their increasingly complex circuits for SPICE simulation. The CMC is organizing a new and innovative International Compact Modeling Conference. Cosponsored by IEEE EDS, it will focus uniquely on compact device models, their development and broad application in the semiconductor industry. You are invited to participate in the evolution of these models, guide model development to help circuit designers create the best circuit performance possible, and enable foundries to leverage the strength of their device fabrication to full extent. Join the world experts in design, process technology, and model development to discuss state-of-the-art semiconductor device modeling for a two-day in-person event in one location, offering a great opportunity to present and learn about this core element of circuit design and how to get the most from these global collaborations. We are seeking papers for oral or poster presentations in the following areas: APPLICATION OF DEVICE MODELS Innovative application of CMC standard device models Best practices, novel use, and benefits of standard device models in circuit design Use of compact models to demonstrate foundry device capabilities DEVICE MODEL DEVELOPMENT Modeling of physical phenomena: Statistical variation, reliability and aging, noise and fluctuations, high frequency effects, Electrostatic Discharge (ESD), self heating, layout effects, etc. Methodologies to assist in model development, practices for coding, quality assurance, circuit simulator integration, etc. Parameter extraction, measurement techniques, model calibration, validation, and verification methodologies, including solutions based on AI or Machine Learning. MODEL ENHANCEMENTS AND IMPLEMENTATIONS Model extensions to capture additional device features (leakage, noise, capacitance, second-order dependencies, …) or expand the operating range of existing devices (bias, power, temperature, frequency, etc.) Model enhancements to support the design of new or demanding circuits Model workflow, implementation, and integration into the design environment (PDK) Computing/simulation platforms, simulation algorithms, and methodologies to improve simulation performance (parallel processing, etc.) Models for established device types that currently lack standardization. MODELING FOR FUTURE/EMERGING TECHNOLOGIES AND APPLICATIONS Models for emerging device types or architectures on the horizon, such as, ferroelectric devices, silicon photonics, cryogenic, quantum computing, etc. Modeling of new physical phenomena in support of current and novel device technologies Novel device technologies currently being researched that could further revolutionize circuit performance, have implications in the design flow, and may become mainstream in the future Please submit your paper proposals in the form of a 2-page abstract for review by January 15, 2025 here 2025.si2-icmc.org. Acceptance notifications will be sent by March 10, 2025. Accepted contributions (for both oral and poster presentations) are expected to submit a camera-ready 4-page draft version of their papers by April 20, 2025 and final version by May 23, 2025 for publication in IEEE Xplore®.

VLSID 2024 Conference

PULP Platform @pulp_platform (5h)

Cheers to 2024! The 37th International Conference on VLSI Design will start in Kolkata on Monday. @LucaBenini will give a banquet talk titled "Open Platform for the Embodied AI Era" at 7:10 PM (IST) on January 9. Check out the conference website for tutorials and schedule: https://vlsid.org

In the present era of automation and connected things, VLSI technology armed with AI and Quantum could be pivotal in changing the VLSI landscape starting from manufacturing to devices to design. To elaborate on this paradigm shift, the theme 2024 VLSI Design conference is aptly chosen to be “VLSI meets AI and Quantum for Cyber Physical Systems”.

Over a span of five-days of VLSID2024, the summit will feed brains and nurture minds with state-of-the-art exhibitors, presentations, panel discussions, innovation forums, and tutorials by established technologists.

[C4P] 36th ICMTS 2024

36th International Conference on Microelectronic Test Structures

April 15-18, 2024, Edinburgh, Scotland

Looking for the best opportunity to present and discuss your ideas and results about test structures, measurements and characterization? This is your chance! Join the 36th ICMTS conference. A Tutorial Short Course will precede the main conference. Several of the best measurement, equipment design, and manufacturing experts, will participate in the equipment exhibition and presentations. The conference will bring together designers and users of test structures to discuss recent developments and future directions, in a one-track program, with convivial breaks allowing attendees to discuss and exchange viewpoints and challenges.

A Best Paper award will be presented by the Technical Program Committee. The conference is co-sponsored by the IEEE Electron Devices Society and all accepted papers, if presented, will be submitted for possible inclusion on IEEEXplore®. Original papers are solicited presenting new developments in topics relevant to ICMTS, including but not limited to, test structures, measurements, and results, in the following areas:

• Design
• Methodologies, Verification
• Within-die circuits for process characterization/monitoring
• Design enablement – Characterization and validation of digital and analog libraries
• Devices and Circuit Modelling
• Measurement techniques
• DC, AC and RF measurements: setup, test and analysis
• Reliability test - including thermal stability, failure analysis etc.
• Statistical analysis, variability, throughput increase, smart test strategies
• Use of machine learning and AI in analysis of data sets - parameter extraction etc.
• Wafer probing, within-die measurements, in-line metrology
• Throughput, testing strategies, yield enhancement and process control tests
• Applications
• Emerging memory technologies (single cell, arrays, and application in neural networks)
• Emerging transistor technologies for digital/analog/power applications
• Photonic devices - silicon integration, new displays (OLED, μ-displays)
• Flexible electronics and sensors (organic and inorganic materials)
• M(N)EMS, actuators, sensors, PV cells and other emerging devices

The author’s abstract submission consists of up to four pages in PDF format (font-embedded). The first page should include a title, a 50-word summary, author name(s), full address, contact number and e-mail of the lead author, and any preference for oral or poster session presentation. The body of the abstract should consist of one page of text (800 to 1000 words) and up to two pages of major figures and tables. The selection process will be based on the technical merit and will be highly weighted in favour of abstracts with high test structure content, giving a clear illustration of the test structure and including measurements and data analysis.

The abstract submission deadline is October 27th, 2023.

Abstracts can be submitted via the ICMTS 2024 website www.icmts.net using the “Abstract Submission” link on the front page. Notice of paper acceptance will be sent to the selected authors by 12th January 2024, with instructions for the expanded manuscript preparation for the conference proceedings. The deadline for submission of the final paper will be Early March, 2024 (TBC).

Please join the ICMTS LI group, if you have interest in all things test and measurement.

Details of the venue, hotel, registration, etc. will be posted when available at the ICMTS 2024 official website.

For further technical information, please contact the technical program chair:

Francesco Driussi, Università di Udine

[conference] 10th Micro Nano 2023

10th International Conference "Micro Nano 2023"

Location: Demokritos Congress Center

Dates: November 2nd-5th 2023

The Micro Nano 2023 Organizing Committee is looking forward to welcoming you to Athens to the 10th International Conference on Micro-Nanoelectronics, Micro-Nanosciences and Nanotechnologies (https://2023.micro-nano.gr), our annual event that brings together Academia, Research and Industry to discuss the latest advancements of the field.

We are happy to announce that the abstract submission is already open and would like to prompt you to submit your work by September 18th. Also, take advantage of the early bird registration discounts, which are open until October the 9th

Visit https://2023.micro-nano.gr/call-for-paper/ to submit your abstract 

and https://2023.micro-nano.gr/fees-registration/ for registration details.

We would like to remind you that this year’s conference includes a Celebratory Special Event for the conference’s 10th Anniversary, scheduled as an Opening Ceremony on the first day (November 2nd, 2023) to commemorate and celebrate 40 years of Microelectronics in Greece. We are also excited about this year’s 

plenary speakers: https://2023.micro-nano.gr/plenary-speakers/

and invited https://2023.micro-nano.gr/invited-speakers/

Check our website for more information on the stimulating presentations that lie ahead.

Dates to remember:

• Abstract submission deadline: September 18th, 2023
• Early-bird registration: October 9th, 2023
• Late poster presentation: October 23rd, 2023

Venue:

• Special Event: Main Hall of the National and Kapodistrian University of Athens (Panepistimiou 30)
• Special Event (Nov.2): “40 years of Microelectronics in Greece”
  https://2023.micro-nano.gr/special-event/

Technical Program: 

• Demokritos Congress Center, NCSR “Demokritos”
  https://2023.micro-nano.gr/final-program/

We are looking forward to seeing you all in November!

On behalf of the Organizing Committee,

Prof. Margarita Chatzichristidi, Conference Chair

Dr. Eleni Makarona, Conference Co-chair

Conference e-mail address: MicroNano2023@chem.uoa.gr

 

[C4P] EDTM Conference 2024, Bangalore

8th IEEE Electron Devices Technology and Manufacturing

EDTM Conference 2024

Theme: Strengthening Globalization in Semiconductors

Hilton Bangalore, India, March 3rd- 6th, 2024

https://ewh.ieee.org/conf/edtm/2024/

Call for Paper: We cordially invite you to submit ORIGINAL 3-page Camera-Ready papers to the 2024 IEEE Electron Devices Technology and Manufacturing (IEEE EDTM 2024) Conference for possible presentations. Original papers are sought on any topic within the scope of IEEE EDTM 2024. There are 14 R&D Tracks for IEEE EDTM 2024, among them:

TRACK 9. Modeling and Simulation (MS)

Advances in modeling/simulation of devices, packages and processes; Technology CAD and benchmarking; Atomistic process and device simulation; Compact models for DTCO and STCO; AI/ML-augmented modelling; Material and interconnect modeling; Models for photonic devices.

Important Dates for Authors

• Three-page camera-ready paper submission starts: August 1,2023
• Paper submission deadline: October 15, 2023 October 30, 2023 
• Notification for Acceptance: December 15, 2023

Accepted IEEE EDTM 2024 papers will be considered for competition for the Best Paper Award, Best Student Paper Awards and Best Poster Awards.

More details on paper submission can be found at the Paper Submission webpage.

[Proceedings] MNDCS 2023

Micro and Nanoelectronics Devices, Circuits and Systems

Select Proceedings of MNDCS 2023

Part of the book series: Lecture Notes in Electrical Engineering (LNEE, volume 1067) DOI: 10.1007/978-981-99-4495-8

Editors: Trupti Ranjan Lenka, Samar K. Saha, Lan Fu

This book presents select proceedings of the International Conference on Micro and Nanoelectronics Devices, Circuits and Systems (MNDCS-2023). The book includes cutting-edge research papers in the emerging fields of micro and nanoelectronics devices, circuits, and systems from experts working in these fields over the last decade. The book is a unique collection of chapters from different areas with a common theme and is immensely useful to academic researchers and practitioners in the industry who work in this field.

[C4P] 17th ITC at the University of Surrey

FIRST CALL FOR PAPER

The 17th International Thin-Film Transistor Conference (ITC2022) is dedicated to TFT related technologies for displays, sensors and general large area and flexible electronics. As TFT applications broaden and expand beyond traditional markets, the 17th ITC will provide a platform for sharing the research progress and discussing the challenges in this field. It will be between 14-16 September, hybrid format, online and on site at the University of Surrey (UK).

Areas of Interest include, but are not limited to:

• Semiconductor materials and processing for high performance TFTs
• Understanding and addressing instabilities of TFTs
• TFT based functional devices (e.g., sensors, memories, synapse)
• Scaling of TFTs for high resolution integration
• TFT compact models for circuit simulation
• TFT backplane integration for displays and sensors
• Flexible and stretchable TFT devices and circuits
• Circuit design and implementations of TFTs

Student Fee Waiver: Top student submissions will be awarded a full registration fee waiver (in person or online), supported by EPSRC Project ALPACA teamsporea.info/alpaca/. Visit the conference website for instructions on how to be considered

Important Dates:

• 17 May 2022 Two-page Abstract Submission Deadline
• 28 June 2022 Notification of Acceptance
• 19 July 2022 Registration Opens
• 14-16 September 2022 Conference dates

For further information, please visit: itc2022.net

Chip in the Fields: SBCCI and SBMicro Conferences

Chip in the Fields

C̶a̶m̶p̶i̶n̶a̶s̶,̶ ̶S̶P̶,̶ ̶B̶r̶a̶z̶i̶l̶ ̶ 

Virtual

August 24 to 28, 2020

Due to the COVID-19 pandemic the Chip in the Fields is changed to a virtual event. In 2021 we plan to have again the normal live Chip in the Fields events to be held in Hotel Premium, Campinas, SP, Brazil

The conferences SBCCI and SBMicro started in the early 80’s and since the year 2000 they joined forces, organizing them at the same venue and under a unified fantasy name “Chip in Somewhere”. The somewhere could be the name of the city or a fantasy name related to the region. It started with the name of “Chip in the Jungle”, because it was held in Manaus, the heart of the Amazon forest. 

Along these 21 years of Chip in, gradually other conferences joined the common venue and organization. Nowadays, we are composed of five sister conferences: SBCCI, SBMicro, WCAS, INSCIT and Sforum, as described in the respective call for papers. Due to the COVID-19 pandemic the Chip in the Fields is changed to a virtual event. Detalhes of the program and access link will be made available in the near future. Please follow the conference website for future up-dates.

Keynote Speakers

Kenneth K. O

Texas Analog Center of Excellence and Dept. of ECE,
The University of Texas at Dallas, Richardson, TX

Rajiv V. JoshiT. J. Watson research center, IBM                                         

Mohammad Al Faruque

University of California Irvine (UCI)

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Sponsored by:	Co-sponsored by:	Organized by: Supported by:
Silicon Sponsors:	Platinum Sponsors:	Silver Sponsors:

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Events:

• SBMicro 2020
• SBCCI 2020
• INSCIT 2020
• WCAS 2020
• SForum 2020
• Business Forum
  • Youtube
• Women in Microelectronics
  • Youtube
• SBMicro Assembly
  • Google Meet
  • Youtube
• CA-ME Meeting
  • Google Meet
• Thesis Contest

33rd IEEE ICMTS, Edinburgh, Scotland.

IEEE 33rd International Conference on Microelectronic Test Structures April 6-9, 2020, Edinburgh, Scotland

It is our great pleasure to invite you to the 33rd IEEE International Conference on Microelectronic Test Structure (ICMTS) which will be held April 6-9, 2020, in Edinburgh, Scotland.     ICMTS is the leading measurement and characterisation conference for micro- and nano-fabrication processes including integrated circuits, photonics, and micro- and nano-system technologies.   Registration for the conference is now open at the conference website: http://www.icmts.net/conf_reg    For advance prices please register for the conference before the 24th of February.     ICMTS 2020 South Hall Complex The University of Edinburgh Pollock Halls, 18 Holyrood Park Road  Edinburgh, EH16 5AR Scotland, UK   W3W: https://w3w.co/proper.marked.sums     Hotel booking information is also available:  http://www.icmts.net/hotel_reg     Tutorials: April 6, 2020 Conference: April 7 - 9, 2020   Please contact the conference organisers at icmts@ed.ac.uk for more information.   Find the ICMTS group on LinkedIn https://www.linkedin.com/groups/3804498/  Follow us on Twitter at https://twitter.com/IEEE_ICMTS

EKV2.6 conference paper reached 50 reads

W. Grabinski et al., "FOSS EKV2.6 Verilog-A Compact MOSFET Model," 

ESSDERC, Krakow, Poland, 2019, pp. 190-193.

doi: 10.1109/ESSDERC.2019.8901822

[postponed]: EUROSOI-ULIS 2020

6th EUROSOI-ULIS

Caen, Normandy, France

The EUROSOI-ULIS organizers have announced that the conference 

and of the associated satellite events will be postponed to 

August 31st - September 4th

The sixth joint EUROSOI-ULIS conference will be hosted by Normandy University (ENSICAEN, UNICAEN, ESIGELEC) in Caen, inside the William the Conqueror Castel, in the auditorium of Museum of Fine Arts. The organizing committee invites scientists and engineers working on SOI technology and advanced nanoscale devices to actively participate by submitting high quality, original contributions (2-page abstracts).

The sixth joint EUROSOI-ULIS conference will be hosted by Normandy University (ENSICAEN, UNICAEN, ESIGELEC) in Caen, inside the William the Conqueror Castel, in the auditorium of Museum of Fine Arts. The organizing committee invites scientists and engineers working on SOI technology and advanced nanoscale devices to actively participate by submitting high quality, original contributions (2-page abstracts).

Important dates :

• abstract submission deadline : January 30, 2020
• notification of acceptance : February 3, 2020
• postponed confernce dates : August 31st - September 4th 2020

Papers in the following areas are solicited:
• Advanced SOI materials and structures: physical mechanisms and innovative SOI-like devices
• New channel materials for CMOS: strained Si, strained SOI, SiGe, GeOI, III-V and high mobility materials on insulator, carbon nanotubes, graphene and other two-dimensional materials
• Properties of ultra-thin films and buried oxides: defects, interface quality, thin gate dielectrics, high-κ materials for switches and memory.
• Nanometer scale devices: technology, characterization techniques and evaluation metrics for high performance, low power, reliability, high frequency and memory applications
• Alternative transistor architectures: FDSOI, Nanowire, FinFET, MuGFET, vertical MOSFET, FeFET and Tunnel FET, MEMS/NEMS, Beyond-CMOS nanoelectronic devices
• New functionalities in silicon-compatible nanostructures and innovative devices representing the More than Moore domain: nanoelectronic sensors, biosensor devices, energy harvesting devices, RF devices, imagers, etc.
• CMOS scaling perspectives: device/circuit level performance evaluation, switches and memory scaling; three-dimensional integration of devices and circuits, heterogeneous integration
• Transport phenomena: compact modeling, device simulation, front- and back-end process simulation
• Advanced test structures and characterization techniques: parameter extraction, reliability and variability assessment techniques for new materials and novel devices

Need help or information : eurosoiulis2020@sciencesconf.org
Conference Chair: Bogdan Cretu