The Compact Modeling Council (CMC) has started the Process for the Selection of the Next Generation SOI MOSFET Compact Models.
The CMC is soliciting SOI models for both partially-depleted (PD) and dynamic depletion (DD) applications. DD refers to SOI devices which exhibit PD behavior forsome bias regions, but are fully-depleted (FD) for others.
The deadline for candidate submission is May 5 2008. CMC officers will invite a number of selected model developers to the CMC Meeting in Boston, MA on 6/5/2008.
A new selection will be done after CMC members have had time to review the presentations given by model developers.
A SOI MOSFET model recommended by CMC will make lots of money!
Who wants to compete?
Apr 30, 2008
Training Course on SOI for analog,digital and RF SOCs and microsystems applications
This training course on SOI for analog,digital and RF SOCs and microsystems applications will take place at IMEC (Heverlee, Belgium) on May 15-16 2008.
This course is organized by the IMEC Training Center in collaboration with Prof. Denis Flandre (UCL, Louvain-la-Neuve, Belgium).
The course will address topics such as SOI MOSFET specific behaviors and performance assessments, SOI MOS analog design, micromachined SOI MEMS, on-wafer wideband characterization, and SOI FinFET integration and circuits.
The lecturers are prestigeous researchers from IMEC and UCL, all of them experts in SOI technologies.
It seems a very interesting course for SOI MOS circuit designers!
This course is organized by the IMEC Training Center in collaboration with Prof. Denis Flandre (UCL, Louvain-la-Neuve, Belgium).
The course will address topics such as SOI MOSFET specific behaviors and performance assessments, SOI MOS analog design, micromachined SOI MEMS, on-wafer wideband characterization, and SOI FinFET integration and circuits.
The lecturers are prestigeous researchers from IMEC and UCL, all of them experts in SOI technologies.
It seems a very interesting course for SOI MOS circuit designers!
Course: "New Trends in Nanoelectronics" in Lausanne
The course "New Trends in Nanoelectronics" will be organized by Prof. Adrian M. Ionescu, from EPFL (Lausanne, Switzerland). This two-day course will take place in Lausanne on May 22-23 2008.
The purpose of the course is to provide a general knowledge about emerging nanoelectronics including technology, nanowires and nanotubes, memory device architectures, nanoelectromechanical devices, and benchmarking for circuit and system applications.
The lecturers that will participate will be A. M. Ionescu, K. E. Moselund (EPFL) and H. -S. Philip Wong (stanford University).
The purpose of the course is to provide a general knowledge about emerging nanoelectronics including technology, nanowires and nanotubes, memory device architectures, nanoelectromechanical devices, and benchmarking for circuit and system applications.
The lecturers that will participate will be A. M. Ionescu, K. E. Moselund (EPFL) and H. -S. Philip Wong (stanford University).
Apr 29, 2008
Open Ph D Student position in nanoelectronic device modeling
We offer one fellowship for a Ph D student position in the Department of Electronic Engineering in the Universitat Rovira i Virgili (URV), in
The duration of the grant will be at least three years, possibly four. The monthly salary will be 1000 Euro/month.
The candidate should have a Bachelor or Master degree in Electrical Engineering, Electronic Engineering, Telecommunication Engineering or Physics. A good background in Semiconductor Physics, Semiconductor Devices, or Integrated Circuit Design will be highly appreciated.
The work to be done by the candidate will be focused on the development of new techniques of characterization and modeling of novel nanoscale semiconductor devices. It will be related to two European projects in which the hosting group participates.
To get more information about our areas of research in the DEEEA, you can visit the website:
http://sauron.etse.urv.es/DEEEA/angles/recerca/nephos/scholarships.htm
And
http://sauron.etse.urv.es/DEEEA/angles/recerca/nephos
Required documents for applicants
Applicants are required to send to the address specified below the following documents (in English or Spanish):
1) a full Curriculum Vitae (as complete as possible)
2) Copy of their diploma
3) copy of their passport
4) Academic certificate including their marks (it is important that the number of hours of each subject). It is also very important that the document specifies what is the minimum mark for passing a given subject and what is the maximum mark that can be awarded.
Candidates can send their documents by e-mail, but in fact we will need original and copy documents (or authenticated copy) of them; therefore we suggest to send the documents by postal mail.
Applications should be sent to:
Prof. Benjamin Iñiguez
Department of Electronic, Electrical and Automatic Control Engineering
Universitat Rovira i Virgili (URV)
Avinguda Països Catalans, 26
43007
Email: benjamin.iniguez@urv.cat
Tel: +34977558521 Fax:+34977559610
Deadline:
You can contact Prof. Benjamin Iñiguez (Benjamin.Iniguez@urv.cat) for more information
Apr 21, 2008
MIGAS'08 Summer School
The 11 session of the MIGAS Summer School (International Summer School on Advanced Microelectronics) will be dedicated to Nanoscale CMOS and Si-Based Beyond CMOS Nanodevices.
MIGAS 2008 will take place in Autrans (French Alps) from June 28 to July 4 2008.
MIGAS is addressed to PhD students, engineers and researchers coming both from the university and from industry of the semiconductors.
The attendees will be able to improve their knowledge on nanoelectronic devices by means a set of lectures conducted by top international scientists.
The scienfific programme will consists of the following lectures:
Besides, MIGAS includes a great social programme, with activities such as excursions the day before the beginning of the school, wine tastings, and copious dinners based on the excellent Dauphinoise and Vercors cuisine, and with great wines. Of course, the area around Autrans offers excellent opportunities for hiking, mountaineering, mountain-biking, lake swimming and more.
Registration includes accomodation in the resort as well as all meals.
MIGAS 2008 will take place in Autrans (French Alps) from June 28 to July 4 2008.
MIGAS is addressed to PhD students, engineers and researchers coming both from the university and from industry of the semiconductors.
The attendees will be able to improve their knowledge on nanoelectronic devices by means a set of lectures conducted by top international scientists.
The scienfific programme will consists of the following lectures:
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Registration includes accomodation in the resort as well as all meals.
Apr 18, 2008
TFT Symposium in the ECS Meeting in Hawaii
The 214th Electrochemical Society (ECS) Meeting will be held in Honolulu, Hawaii, on October 12-17 2008, in the Hilton Hawaiian Village.
The ECS Meeting includes a number of Symposia.
For the TFT community, I want to highlight the TFT 10 Symposium.
The TFT symposium is an intersting forum for the presentation and discussion of
the latest developments in all types of thin film transistors (TFTs) and
related fields. This symposium is chaired by Prof Yue Kuo (Texas A&M University)
Papers can deal with all aspects of fabrication processes, materials, device
physics, characterization, structures, and applications of TFTs. This TFT symposium will address the following topics:
(1.) new TFT Structures; (2.) novel or new processes; (3.) organic, inorganic, oxide, etc. thin film materials; (4.) device physics, modeling, characterization, and reliability; (5.) applications in LCDs, imagers, sensors, biochips, MEMS, etc.; (6.) applications in circuits; and (7.) integration of TFTsto large area displays, VLSIC, and other complex systems.
Abstracts should be submitted electronically to ECS headquarters by May 30.
Being this TFT Symposium in Hawaii, no doubt it will be a big success!
The ECS Meeting includes a number of Symposia.
For the TFT community, I want to highlight the TFT 10 Symposium.
The TFT symposium is an intersting forum for the presentation and discussion of
the latest developments in all types of thin film transistors (TFTs) and
related fields. This symposium is chaired by Prof Yue Kuo (Texas A&M University)
Papers can deal with all aspects of fabrication processes, materials, device
physics, characterization, structures, and applications of TFTs. This TFT symposium will address the following topics:
(1.) new TFT Structures; (2.) novel or new processes; (3.) organic, inorganic, oxide, etc. thin film materials; (4.) device physics, modeling, characterization, and reliability; (5.) applications in LCDs, imagers, sensors, biochips, MEMS, etc.; (6.) applications in circuits; and (7.) integration of TFTsto large area displays, VLSIC, and other complex systems.
Abstracts should be submitted electronically to ECS headquarters by May 30.
Being this TFT Symposium in Hawaii, no doubt it will be a big success!
SINANO Device Modeling Summer School
The Third SINANO Device Modeling Summer School will be held in the historic Bertinoro Castle (Bertinoro (FC), Italy) on September 1-5 2008.
The SINANO Summer School was held in 2005 and 2006 in the framework of the former SINANO European Network of Excellence, and is currently continued under the umbrella of the new NANOSIL Network of Excellence and of the Integrated Project PULLNANO.
The goal of the SINANO Summer School is to increase the knowledge of PhD students and postdoctoral researchers in the fields of advanced modeling, simulation and characterization techniques for conventional and nanoscale CMOS devices. The lectures use to address topics such as device physics, device models, numerical techniques, device simulation tools, and experimental characterization techniques.
Regarding the topic of "Analytical and compact models", Dr Raphaël Clerc (IMEP, France), will talk about “Device technology oriented analytical models”
Peter Baumgartner (Infineon) will give a lecture entitled: “RF and noise characterization of transistors and circuits”
Prof Paolo Pavan will talk about “Current trends in non-volatile memories”
Besides, there will also be a great social program which will include dinners, hiking and other outdoor activities..
The registration form should be sent before July 30.
The SINANO Summer School was held in 2005 and 2006 in the framework of the former SINANO European Network of Excellence, and is currently continued under the umbrella of the new NANOSIL Network of Excellence and of the Integrated Project PULLNANO.
The goal of the SINANO Summer School is to increase the knowledge of PhD students and postdoctoral researchers in the fields of advanced modeling, simulation and characterization techniques for conventional and nanoscale CMOS devices. The lectures use to address topics such as device physics, device models, numerical techniques, device simulation tools, and experimental characterization techniques.
The 5 days program of the School will be dedicated to the following topics:
Prospects for further development of CMOS technology
Transport models for device simulation
Experimental electrical device characterization
Analytical and compact models
Post CMOS devices
Silicon technology for photo-voltaic energy conversion
Regarding the topic of "Analytical and compact models", Dr Raphaël Clerc (IMEP, France), will talk about “Device technology oriented analytical models”
Peter Baumgartner (Infineon) will give a lecture entitled: “RF and noise characterization of transistors and circuits”
Prof Paolo Pavan will talk about “Current trends in non-volatile memories”
Besides, there will also be a great social program which will include dinners, hiking and other outdoor activities..
The registration form should be sent before July 30.
Apr 15, 2008
Article in EDN: Modeling gaps in state-of-the-art mixed-signal SOC design
I've recently found an old (2006) paper on the EDN: Electronics Design, Strategy, News website. (I cannot reproduce it here because of the copyrights).
They discuss a bit about standardization efforts on Compact Modeling, and the different aspects that must be taken into account. I think it is a nice paper, even though it is slightly biased towards BSIM (only a bit: PSP, EKV and HiSIM are also mentioned... but not so extensively....).
They discuss a bit about standardization efforts on Compact Modeling, and the different aspects that must be taken into account. I think it is a nice paper, even though it is slightly biased towards BSIM (only a bit: PSP, EKV and HiSIM are also mentioned... but not so extensively....).
Papers in Volume 52, Issue 5, Pages 597-838 (May 2008) of Solid-State Electronics
It seems that this month's harvest has been quite good. There are some quite interesting papers
Low-frequency noise properties of double channel AlGaN/GaN HEMTs
S.K. Jha, C. Surya, K.J. Chen, K.M. Lau and E. Jelencovic
A fully 2-dimensional, quantum mechanical calculation of short-channel and drain induced barrier lowering effects in HEMTs
G. Krokidis, J.P. Xanthakis and N.K. Uzunoglu
Subthreshold characteristics of polysilicon TFTs
Wanling Deng, Xueren Zheng, Rongsheng Chen and Yuan Liu
Physics-based 1/f noise model for MOSFETs with nitrided high-κ gate dielectrics
Tanvir Hasan Morshed, Siva Prasad Devireddy, Zeynep Çelik-Butler, Ajit Shanware, Keith Green, J.J. Chambers, M.R. Visokay and Luigi Colombo
Modeling non-quasi-static effects in channel thermal noise and induced-gate noise in MOS field-effect transistors
Abhay Deshpande and R.P. Jinda
Mobility model for compact device modeling of OTFTs made with different materials
M. Estrada, I. Mejía, A. Cerdeira, J. Pallares, L.F. Marsal and B. Iñiguez
Hot-carrier effects as a function of silicon film thickness in nanometer-scale SOI pMOSFETs
Sung Jun Jang, Dae Hyun Ka, Chong Gun Yu, Won-Ju Cho and Jong Tae Park
Modeling of potentials and threshold voltage for symmetric doped double-gate MOSFETs
A. Cerdeira, O. Moldovan, B. Iñiguez and M. Estrada
Low-frequency noise properties of double channel AlGaN/GaN HEMTs
S.K. Jha, C. Surya, K.J. Chen, K.M. Lau and E. Jelencovic
A fully 2-dimensional, quantum mechanical calculation of short-channel and drain induced barrier lowering effects in HEMTs
G. Krokidis, J.P. Xanthakis and N.K. Uzunoglu
Subthreshold characteristics of polysilicon TFTs
Wanling Deng, Xueren Zheng, Rongsheng Chen and Yuan Liu
Physics-based 1/f noise model for MOSFETs with nitrided high-κ gate dielectrics
Tanvir Hasan Morshed, Siva Prasad Devireddy, Zeynep Çelik-Butler, Ajit Shanware, Keith Green, J.J. Chambers, M.R. Visokay and Luigi Colombo
Modeling non-quasi-static effects in channel thermal noise and induced-gate noise in MOS field-effect transistors
Abhay Deshpande and R.P. Jinda
Mobility model for compact device modeling of OTFTs made with different materials
M. Estrada, I. Mejía, A. Cerdeira, J. Pallares, L.F. Marsal and B. Iñiguez
Hot-carrier effects as a function of silicon film thickness in nanometer-scale SOI pMOSFETs
Sung Jun Jang, Dae Hyun Ka, Chong Gun Yu, Won-Ju Cho and Jong Tae Park
Modeling of potentials and threshold voltage for symmetric doped double-gate MOSFETs
A. Cerdeira, O. Moldovan, B. Iñiguez and M. Estrada
Apr 14, 2008
MOS-AK
I copy a mail from Wladek Grabinski:
The MOS-AK Eindhoven Workshop's presentations are available on-line
please visit: www.mos-ak.org/eindhoven
I would like to take this opportunity and thank all speakers and presenters for
their valuable contribution to the MOS-AK Meeting at MiPlaza. Selected MOS-AK
publications are recommended for further publications: www.mos-ak.org/eindhoven
Let me also acknowledge the workshop sponsors (MiPlaza, Agilent and Cascade) for
their generous financial support as well as local meeting organizers for their
support, smooth organization and perfect logistic of our modeling event. Such
events are unique platform for continuous promotion of local, European compact
modeling activities.
You are more than welcome to attend and contribute to coming modeling events:
* WCM'08 Workshop June 1-5, 2008, Boston, Massachusetts
* MIXDES'08 June 19-21, 2008 Poznan www.mixdes.org/Special_sessions.htm
* MOS-AK/ESSDERC/ESSCIRC Workshop September 19, 2008 www.mos-ak.org/edinburgh/
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