[DATE2026] Open Source Related Talks

DATE 2026 Verona, Italy

Open Source Related Talks

Monday, 20 April - Wednesday, 22 April 2026

<https://date26.date-conference.com/programme>

Label	Title	Authors
TS02.8	ML-DSA-OSH: An Efficient, Open-Source Hardware Implementation of ML-DSA	Quinten Norga; Suparna Kundu; Ingrid Verbauwhede
LK03	Democratizing Silicon: The Rise of Open-Source EDA and Europe’s Strategic Roadmap	Luca Benini
TS10.1	PICOSNN: Partially Incoherent Configurable Optical Computing Architecture for SNN Acceleration	Bowen Duan; Zhenhua Zhu; Zhengyang Duan; Huazhong Yang; Yuan Xie; Yu Wang
TS16.1	Non-Volatile Spintronic Flip-Flops with Checkpoint Preservation Supported in RISC-V Platform	Jiongzhe Su; Mingtao Chen; Zhanpeng Qiu; Bo Liu; Hao Cai
LBR01.4	Float Fight - Verifying Floating-Point Behavior In Risc-V Simulators	Katharina Ruep, Manfred Schlaegl and Daniel Grosse
LBR01.7	Hybrid Virtual Platform + FPGA Co-Emulation Framework	Lorenzo Ruotolo; Giovanni Pollo; Mohamed Amine Hamdi; Matteo Risso; Yukai Chen; Enrico Macii; Massimo Poncino; Sara Vinco; Alessio Burrello; Daniele Jahier Pagliari
TS20.1	Fault-Tolerance Mapping of Spiking Neural Networks to RRAM-Based Neuromorphic Hardware	Yuqing Xiong; Chao Xiao; Zhijie Yang; Lei Wang; Mengying Zhao
TS21.4	Substrate: A Statically Typed Framework for Designing Highly Configurable Analog and Mixed-Signal Circuit Generators	Rahul Kumar; Rohan Kumar; Borivoje Nikolic
SD03	Open-Source Hardware Landscape
SD03.1	Open Silicon Fabrication – Made in Europe	Gerhard Kahmen, IHP GmbH, DE
SD03.2	From Schematic To Silicon: Mixed Signal Ic Design In Open Source Flows	Harald Pretl, JKU Linz, AT
SD03.3	Bringing Software Design Thinking To Chip Design	Tomi Rantakari, ChipFlow, GB

[paper] Memristors SPICE Compact Modeling

Thomas Günkel1,2, Aleix Barrera1, Lluís Balcells1, Narcís Mestres1, 

Enrique Miranda2, Anna Palau1, Jordi Suñé2

SPICE-Compatible Compact Modeling of Cuprate-Based Memristors Across

a Wide Temperature Range 

Advanced Electronic Materials (2026): e00861

DOI: https://doi.org/10.1002/aelm.202500861

1 Institut de Ciència de Materials de Barcelona, ICMAB-CSIC, Bellaterra (SP)
2 Departament d’Enginyeria Electrònica, Universitat Autònoma de Barcelona (SP)

ABSTRACT: Cryogenic memristors based on the high-temperature superconductor YBa2 CuO7−δ offer significant potential as nonvolatile memory elements or unit cell for analog artificial neural networks for future applications such as control units for quantum processors, cryogenic data centers or space-related electronics. In this work, the experimental switching capabilities of cuprate-based memristors are analyzed in terms of the material-specific physics. This work investigates the experimental switching behavior of cuprate-based memristors across temperatures from cryogenic to room temperature. The underlying interpretation, namely the trapping of injected charge carriers at a metal interface and field-induced detrapping, is incorporated into a physically inspired compact model. The core equations of this model consist of a differential balance equation and a current equation, which is derived from space-charge limited conduction. Comparison with experimental data shows that the model successfully reproduces the key features of the measured switching behavior across a wide temperature range, spanning from 80 to 300 K. Additionally, we implement the model in SPICE, enabling circuit-level simulations. The resulting compact model provides a useful framework for guiding experimental studies, capturing key features of the switching behavior, and bridging the gap between device-levelcharacterization and circuit-level design.

FIG: LTspice Simulations: (a) Implementation of the compact model into a LTspice schematic. The diagram is explained in more detail in the main text. Simulation results of the hysteron V(r) and the 𝐼𝑉 -characteristics abs(I(B2)) depending on the input signal V(v) are given for a simple sinusoidal input signal in (b) and a damped waveform in (c).

 

Acknowledgments: The authors acknowledge financial support from the Spanish Ministry of Science and Innovation MCIN/ AEI /10.13039/501100011033/ through CHIST-ERA PCI2021-122028-2A co-financed by the European Union Next Generation EU/PRTR, the “Severo Ochoa” Programme for Centres of Excellence CEX2023-001263-S, HTSUPERFUN PID2021-124680OB-I00,and HTS-4ICT PID2024-156025OB-I00, co-financed by ERDF A way of making Europe. The Spanish Nanolito networking project (RED2022-134096-T). The European COST Action SUPERQUMAP (CA 21144). EMand JS would like to thank the support the Spanish Ministerio deCiencia e Innovación (MCIN) / Agencia Española de investigación (AEI)10.13039/501100011 033 (Under project No. PID2022-139586NB-C41). TG acknowledge support from AGAUR Catalan Government Predoctoral Fellowship (2022 FISDU 00115). J.S. and E. M. acknowledge the support of the EU through the HORIZON Chips-JU 101194172 NeAIxt Project and the Agencia Española de Investigación (AEI)/10.13039/501100011033 under Project PCI2025-163216. The authors acknowledge the Scientific Servicesat ICMAB and the UAB PhD program in Materials Science.

[GitHub] Heat Map of Developers in Africa

Commonwealth Report "Open Source Africa" 

by OpenUK

The heatmap illustrates the distribution of developers with GitHub accounts across Africa. It shows that accounts are dispersed in multiple regions throughout the continent. Among the countries highlighted in the OpenUK report, Nigeria has the largest number of users with approximately 1.8 million accounts, followed by Kenya with 666,020 accounts and Rwanda with 85,978 accounts.
[Read More] in recent Commonwealth Report "Open Source Africa" by OpenUK

[paper] ULTRARAM Neuromorphic Memory Device

Abhishek Kumar, Peter D. Hodgson, Manus Hayne, and Avirup Dasgupta

Artificial synapse based on ULTRARAM memory device for neuromorphic applications

Journal of Applied Physics 139, no. 12 (2026)

DOI: 10.1063/5.0314826

1. Department of Electrical Engineering and Computer Sciences, UCB (USA)

2. Department of Physics, Lancaster University, Lancaster LA1 4YB (UK)

3. Quinas Technology Limited, Lancaster LA1 4YB, (UK)

4. Department of Electronics and Communication Engineering, IIT Roorkee (IN)

Abstract: The memory demands of large-scale deep neural networks (DNNs) require synaptic weight values to be stored and updated in off-chip memory, such as dynamic random-access memory, which reduces energy efficiency and increases training time. Monolithic crossbar or pseudo-crossbar arrays using analog non-volatile memories, which can store and update weights on-chip, present an opportunity to efficiently accelerate DNN training. In this article, we present on-chip training and inference of a neural network using an ULTRARAM memory device-based synaptic array and complementary metal–oxide–semiconductor (CMOS) peripheral circuits. ULTRARAM is a promising emerging memory exhibiting high endurance (⁠> 10E7P/E cycles), ultrahigh retention (⁠>1000 years), and ultralow switching energy per unit area. A physics-based compact model of ULTRARAM memory device has been proposed to capture the real-time trapping/de-trapping of charges in the floating gate and utilized for the synapse simulations. A circuit-level macro-model is employed to evaluate and benchmark the on-chip learning performance in terms of area, latency, energy, and accuracy of an ULTRARAM synaptic core. In comparison with CMOS-based design, it demonstrates an overall improvement in area and energy by 1.8x and 1.52x⁠, respectively, with 91% of training accuracy.

FIG: Schematic of an ULTRARAM memory cell and the corresponding transmission electron microscope image of the device’s epilayers

Acknowledgments: This work was supported in part by the Quinas Technology Limited, Lancaster, United Kingdom; Indian Institute of Technology Roorkee, India; and Prime Minister’s Research Fellowship, Ministry of Education, Government of India under Grant No. PM-31-22-773-414.

Data Availability: The data that support the findings of this study are available within the article.

[github] NVC: VHDL compiler and simulator

 

https://cameron-eda.com/

NVC is a VHDL compiler and simulator

https://github.com/kev-cam/nvc

NVC supports almost all of VHDL-2008 with the exception of PSL, and it has been successfully used to simulate several real-world designs. Experimental support for Verilog and VHDL-2019 is under development. NVC has a particular emphasis on simulation performance and uses LLVM to compile VHDL to native machine code. NVC is not a synthesizer. That is, it does not output something that could be used to program an FPGA or ASIC. It implements only the simulation behaviour of the language as described by the IEEE 1076 standard. NVC supports popular verification frameworks including OSVVM, UVVM, VUnit and cocotb. See below for installation instructions.

Vendor Libraries

NVC provides scripts to compile popular verification frameworks and the simulation libraries of common FPGA vendors

• For OSVVM use nvc --install osvvm
• For UVVM use nvc --install uvvm
• For Xilinx ISE use nvc --install ise
• For Xilinx Vivado use nvc --install vivado and additionally nvc --install xpm_vhdl
  if you require simulation models of the XPM macros
• For Altera Quartus use nvc --install quartus
• For Lattice iCEcube2 use nvc --install icecube2
• For Free Model Foundry common packages use nvc --install fmf