[mos-ak] Fwd: MIXDES 2026 – Extended Paper Submission Deadline & Workshop Information

Dear Colleagues,

On behalf of the MIXDES 2026 organizing committee, we would like to inform you that the regular paper submission deadline for the MIXDES 2026 Conference has been extended to 15 March 2026. The additional time should be especially helpful for contributors who may also be interested in the full‑day IHP‑Open‑PDK workshop accompanying this year's event.

If you intend to submit a paper, please register it as soon as possible via the MIXDES Conference website (www.mixdes.org) by selecting the "Submit a paper" link. Early registration greatly assists us in initiating the reviewer assignment process. You will be able to update all paper details and upload revised versions of the manuscript until May 15th, 2026.

We are also pleased to announce the workshop "Analog IC Design Using Open Source Tools and IHP OpenPDK", which will take place on June 24th, 2026, at Poznan University of Technology. The workshop will provide practical, hands-on experience with open-source tools such as Xschem, Ngspice, and KLayout, covering core aspects of analog schematic design, simulation, layout, and process fundamentals. Due to the limited number of seats, participation is on a first-come, first-served basis. Requests for attendance should be sent to: mixdes2026@dmcs.p.lodz.pl

More information is available here: https://www.mixdes.org/Mixdes3/tekst/view/openpdk-analog

You are welcome to forward this information to colleagues who may be interested in the conference or workshop. The main conference details can be found in the Call for Papers: https://www.mixdes.org/downloads/call2026.pdf

If you have any questions, do not hesitate to contact directly:

Mariusz Orlikowski, MIXDES 2026 Conference Secretary

Important dates: 

• Paper submission deadline (extended): 15 March 2026 
• Notification of acceptance: 30 April 2026 
• Final paper versions: 15 May 2026
• IHP OpenPDK Workshop: 24 June 2026, Poznań, Poland
• MIXDES 2026 Conference: 25–27 June 2026, Poznań, Poland 

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[paper] Threshold Engineering in 2D FETs

Dipanjan Sen, Harikrishnan Ravichandran, Safdar Imam, Subir Ghosh, Krishnendu Mukhopadhyay, Md Yasir Bashir, Thomas S. Ie, Vlastimil Mazanek, Jan Luxa, Chen Chen, Joan M. Redwing, Zdenek Sofer, Shubham Sahay, Mercouri G. Kanatzidis and Saptarshi Das

van der Waals dielectrics for threshold engineering in two-dimensional field effect transistors

Nature Communications (2026)

DOI: 10.1038/s41467-026-69089-6

1. Engineering Science and Mechanics, Penn State University, University Park, PA 16802, USA
2. Department of Chemistry, Northwestern University, Evanston, IL 60208, USA
3. Electrical Engineering, Indian Institute of Technology, Kanpur, India
4. Department of Inorganic Chemistry, University of Chemistry and Technology Prague, CzechRepublic
5. 2DCC, Penn State University, University Park, PA 16802, USA
6. Materials Science and Engineering, Penn State University, University Park, PA 16802, USA
7. Electrical Engineering, Penn State University, University Park, PA 16802, USA

Abstract: Two-dimensional (2D) semiconductors are promising for next-generation field-effect transistors (FETs), but their integration into complementary-metal-oxide-semiconductors (CMOS) logic is hindered by improper threshold voltages (Vth), leading to excessive power consumption. While past efforts have focused on improving electrostatics and near-ideal subthreshold swing (𝑺𝑺), systematic Vth engineering in 2D FETs remains unexplored. Here, we investigate high-κ van der Waals (vdW) dielectrics including metal oxyhalides such as LaOBr, BiOBr, and BiOCl, and bimetallic thiophosphates such as LiInP2S6 (LIPS), LiInP2Se6 (LIPSe) and CuInP2S6 (CIPS) and demonstrate that bimetallic thiophosphates enable programmable and non-volatile Vth tuning in both n-type monolayer MoS₂ and p-type bilayer WSe2 FETs. Leveraging ion-mediated Vth tuning, we realize 2DCMOS inverters with nearly three orders of magnitude reduction in static power while maintaining high switching speed. Combining experiments with industry-compatible SPICE modeling, we identify an optimal Vth window that minimizes power without significant delay penalty, enabling built-in power gating and improved power–performance–area metrics without additional sleep transistors.

Fig: LiInP2S6 as a top-gate dielectric for 2D field-effect transistors (FETs). a) angled scanning electron microscope (SEM) image of dual-gated 2D FET with LiInP2S6(LIPS) as top-gate dielectric and 25 nm thick Al2O3 as the back-gate dielectric. Dual-sweep top-gate transfer characteristic of a b) WSe2 FET obtained by sweeping the VTG from -8 V to 8 V at a constant 𝑉𝐵𝐺 = -4 V and 𝑉𝐷𝑆 = 1 V, both exhibiting a counterclockwise (CCW) hysteresis.

Acknowledgements: SD acknowledges funding support from the National Science Foundation for NSF Career under grant number ECCS-2042154, NSF Fuse, under grant number ECCS-2328741, ONR under grant number N00014-24-1-2565, and ARO under grant number W911NF-23-1-0279. The MOCVDTMD films were grown in the 2D Crystal Consortium–Materials Innovation Platform (2DCC-MIP) facility which is supported by the National Science Foundation under cooperative agreement DMR-2039351. The work at Northwestern was supported in part by the National Science Foundation under award number DMR-2305731. ZS was supported by ERC-CZ program (project LL2101) from the Ministry of Education Youth and Sports (MEYS) and by the project Advanced Functional Nanorobots (reg. No. CZ.02.1.01/0.0/0.0/15_003/0000444 financed by the EFRR). JL was supported by Czech Science Foundation (GACR No. 24-11465S). VM was supported by project LUAUS23049 from Ministry of Education Youth and Sports (MEYS). SS acknowledges the Ministry of Education’s Scheme for Transformational and Advanced Research in Sciences (STARS) Project under Grant MoE-STARS/STARS-2/2023-0023, DST Indo-Korea Research Grant INT/Korea/P-66 under Grant E-47691 and the University Grant Commission, Government of India, through the Senior Research Fellowship, student ID: 200510263123

[paper] Ion-Sensitive FET Memory

Henrique Lanfredi Carvalho, Pedro Henrique Duarte, Ricardo Cardoso Rangel 

and Joao Antonio Martino

“Effect of gate capacitance ratio on ion-sensitive FET memory”

Solid-State Electronics (2026) Art. no. 109350.

doi: 10.1016/j.sse.2026.109350

* LSI/PSI/USP, University of Sao Paulo, Sao Paulo, Brazil

Abstract: This paper introduces the ISFET Memory device, which combines nonvolatile memory capabilities with the traditional ISFET functionality for pH sensing applications. The device’s performance is evaluated in both writing and erasing modes, with particular emphasis on how adjusting the gate capacitance ratio (GCR) influences the operating voltages and sensitivity. Results show that optimizing the GCR to 0.43 significantly reduces the voltages required for writing and erasing operations, while also enhancing sensitivity across a broader pH range. The device achieves maximum sensitivities of 1609 mV/pH in the writing state and 940 mV/pH in the erasing state, far exceeding the ideal ISFET sensitivity of 58.2 mV/pH. Furthermore, the device demonstrates adaptability to different pH ranges: the writing mode is better suited for pH values from 2 to 10, whereas the erasing mode is more effective for the remaining pH range.

Fig: Cross section of ISFET Memory (a) and with optimized structure (b)

Acknowledgment: The authors acknowledge CNPq, CAPES (Coordenação de Aperfeiçoamento de Pessoal de Nível Superior – Brazil - Finance Code 001) and São Paulo Research Foundation - FAPESP (under grant #2020/04867-2) for the financial support.

[+] This article is part of a special issue entitled: ‘EuroSOI-ULIS 2025’ published in Solid State Electronics.

[paper] Compact Modeling of Ferroelectric Devices

J. Lee, J. Kim, M. Kim, H. Kim, C. Ra, H. Choi, and J. Jeon,

“Asymmetry-Aware Compact Modeling of Ferroelectric Devices for Circuit-Level Simulation,”

ACS Applied Electronic Materials, Feb. 2026,

doi: 10.1021/acsaelm.5c02300

* Department of Electrical and Computer Engineering, Sungkyunkwan University (SKKU), Suwon 16419 (KR)

Abstract: This paper presents a unified compact model that comprehensively captures nonideal behaviors such as asymmetric hysteresis and minor loops of ferroelectric devices based on hafnium zirconium oxide (HfO2–ZrO2, HZO). The proposed model, based on the Preisach framework, integrates branch-dependent slopes, asymmetric coercive voltages, imprint-induced loop shifts, and low-voltage minor-loop responses into a unified analytical form. Implemented in Verilog-A, the proposed model reproduces measured polarization–voltage (P–V) characteristics of a ferroelectric capacitor (FeCAP) with higher accuracy than conventional symmetric models. Furthermore, using an identical parameter set, it consistently scales from a single device to logic, memory, and neuromorphic circuits, enabling prediction of operating characteristics and read/write margins. Owing to these capabilities, the model serves as a reliable predictive tool for circuit-level design and provides a practical pathway for process–design feedback and co-optimization.

[paper] Cryo FD SOI LNA Design

Giovani Britton, Salvador Mir, Estelle Lauga-Larroze, Benjamin Dormieu, Jose Lugo, Joao Azevedo, Sebastien Sadlo, Quentin Berlingard, Mikael Casse, Philippe Galy

Using DC transistor characterization measurements for LNA design at cryogenic temperatures

(2026) researchsquare.com

DOI: 10.21203/rs.3.rs-7754596/v1

1. STMicroelectronics, Crolles (F)
2. Univ. Grenoble Alpes, CNRS, Grenoble-INP, TIMA, Grenoble (F)
3. Univ. Grenoble Alpes, CEA-Leti, Grenoble (F)
4. Univ. Grenoble Alpes, CNRS, Grenoble-INP, IMEP-LAHC, Grenoble (F)

Abstract: The design of Radio Frequency (RF) cryogenic circuits has attracted much interest in recent years due to applications such as quantum computers. Interface electronics with ultra-low levels of power consumption at temperatures as low as 4 K are required. Silicon technologies are being considered for implementation because of the possibility of large-scale qubit integration with energy-efficient readout and control interfaces. However, the design of RF cryogenic circuits is complicated because of the lack of standard design kits with the corresponding component models for their simulation at these temperatures. Alternative approaches to avoid costly design and fabrication cycles are possible, in particular the use of Look-Up-Table (LUT) based techniques that exploit characterization data of circuit components at cryogenic temperature. In this paper, we make use of this approach for the design of a RF Low Noise Amplifier (LNA) using a 28 nm FD-SOI technology that has been characterized at cryogenic temperatures1using DC measurements. Furthermore, we also experimentally demonstrate that the DC measurements used are valid to extract the transistor noise parameters used in the LUT-based analysis.

Fig: Measurement of: (a) transconductance gm, and (b) threshold voltage Vth 

for the 28nm FD-SOI technology, from 300K down to 4K.

Acknowledgements: This work was supported by the French CIFRE program and the Labex MINOS of French program ANR-10-LABX-55-01.