[paper] Memristors SPICE Compact Modeling

Thomas Günkel1,2, Aleix Barrera1, Lluís Balcells1, Narcís Mestres1, 

Enrique Miranda2, Anna Palau1, Jordi Suñé2

SPICE-Compatible Compact Modeling of Cuprate-Based Memristors Across

a Wide Temperature Range 

Advanced Electronic Materials (2026): e00861

DOI: https://doi.org/10.1002/aelm.202500861

1 Institut de Ciència de Materials de Barcelona, ICMAB-CSIC, Bellaterra (SP)
2 Departament d’Enginyeria Electrònica, Universitat Autònoma de Barcelona (SP)

ABSTRACT: Cryogenic memristors based on the high-temperature superconductor YBa2 CuO7−δ offer significant potential as nonvolatile memory elements or unit cell for analog artificial neural networks for future applications such as control units for quantum processors, cryogenic data centers or space-related electronics. In this work, the experimental switching capabilities of cuprate-based memristors are analyzed in terms of the material-specific physics. This work investigates the experimental switching behavior of cuprate-based memristors across temperatures from cryogenic to room temperature. The underlying interpretation, namely the trapping of injected charge carriers at a metal interface and field-induced detrapping, is incorporated into a physically inspired compact model. The core equations of this model consist of a differential balance equation and a current equation, which is derived from space-charge limited conduction. Comparison with experimental data shows that the model successfully reproduces the key features of the measured switching behavior across a wide temperature range, spanning from 80 to 300 K. Additionally, we implement the model in SPICE, enabling circuit-level simulations. The resulting compact model provides a useful framework for guiding experimental studies, capturing key features of the switching behavior, and bridging the gap between device-levelcharacterization and circuit-level design.

FIG: LTspice Simulations: (a) Implementation of the compact model into a LTspice schematic. The diagram is explained in more detail in the main text. Simulation results of the hysteron V(r) and the 𝐼𝑉 -characteristics abs(I(B2)) depending on the input signal V(v) are given for a simple sinusoidal input signal in (b) and a damped waveform in (c).

 

Acknowledgments: The authors acknowledge financial support from the Spanish Ministry of Science and Innovation MCIN/ AEI /10.13039/501100011033/ through CHIST-ERA PCI2021-122028-2A co-financed by the European Union Next Generation EU/PRTR, the “Severo Ochoa” Programme for Centres of Excellence CEX2023-001263-S, HTSUPERFUN PID2021-124680OB-I00,and HTS-4ICT PID2024-156025OB-I00, co-financed by ERDF A way of making Europe. The Spanish Nanolito networking project (RED2022-134096-T). The European COST Action SUPERQUMAP (CA 21144). EMand JS would like to thank the support the Spanish Ministerio deCiencia e Innovación (MCIN) / Agencia Española de investigación (AEI)10.13039/501100011 033 (Under project No. PID2022-139586NB-C41). TG acknowledge support from AGAUR Catalan Government Predoctoral Fellowship (2022 FISDU 00115). J.S. and E. M. acknowledge the support of the EU through the HORIZON Chips-JU 101194172 NeAIxt Project and the Agencia Española de Investigación (AEI)/10.13039/501100011033 under Project PCI2025-163216. The authors acknowledge the Scientific Servicesat ICMAB and the UAB PhD program in Materials Science.

[GitHub] Heat Map of Developers in Africa

Commonwealth Report "Open Source Africa" 

by OpenUK

The heatmap illustrates the distribution of developers with GitHub accounts across Africa. It shows that accounts are dispersed in multiple regions throughout the continent. Among the countries highlighted in the OpenUK report, Nigeria has the largest number of users with approximately 1.8 million accounts, followed by Kenya with 666,020 accounts and Rwanda with 85,978 accounts.
[Read More] in recent Commonwealth Report "Open Source Africa" by OpenUK

[paper] ULTRARAM Neuromorphic Memory Device

Abhishek Kumar, Peter D. Hodgson, Manus Hayne, and Avirup Dasgupta

Artificial synapse based on ULTRARAM memory device for neuromorphic applications

Journal of Applied Physics 139, no. 12 (2026)

DOI: 10.1063/5.0314826

1. Department of Electrical Engineering and Computer Sciences, UCB (USA)

2. Department of Physics, Lancaster University, Lancaster LA1 4YB (UK)

3. Quinas Technology Limited, Lancaster LA1 4YB, (UK)

4. Department of Electronics and Communication Engineering, IIT Roorkee (IN)

Abstract: The memory demands of large-scale deep neural networks (DNNs) require synaptic weight values to be stored and updated in off-chip memory, such as dynamic random-access memory, which reduces energy efficiency and increases training time. Monolithic crossbar or pseudo-crossbar arrays using analog non-volatile memories, which can store and update weights on-chip, present an opportunity to efficiently accelerate DNN training. In this article, we present on-chip training and inference of a neural network using an ULTRARAM memory device-based synaptic array and complementary metal–oxide–semiconductor (CMOS) peripheral circuits. ULTRARAM is a promising emerging memory exhibiting high endurance (⁠> 10E7P/E cycles), ultrahigh retention (⁠>1000 years), and ultralow switching energy per unit area. A physics-based compact model of ULTRARAM memory device has been proposed to capture the real-time trapping/de-trapping of charges in the floating gate and utilized for the synapse simulations. A circuit-level macro-model is employed to evaluate and benchmark the on-chip learning performance in terms of area, latency, energy, and accuracy of an ULTRARAM synaptic core. In comparison with CMOS-based design, it demonstrates an overall improvement in area and energy by 1.8x and 1.52x⁠, respectively, with 91% of training accuracy.

FIG: Schematic of an ULTRARAM memory cell and the corresponding transmission electron microscope image of the device’s epilayers

Acknowledgments: This work was supported in part by the Quinas Technology Limited, Lancaster, United Kingdom; Indian Institute of Technology Roorkee, India; and Prime Minister’s Research Fellowship, Ministry of Education, Government of India under Grant No. PM-31-22-773-414.

Data Availability: The data that support the findings of this study are available within the article.

[github] NVC: VHDL compiler and simulator

 

https://cameron-eda.com/

NVC is a VHDL compiler and simulator

https://github.com/kev-cam/nvc

NVC supports almost all of VHDL-2008 with the exception of PSL, and it has been successfully used to simulate several real-world designs. Experimental support for Verilog and VHDL-2019 is under development. NVC has a particular emphasis on simulation performance and uses LLVM to compile VHDL to native machine code. NVC is not a synthesizer. That is, it does not output something that could be used to program an FPGA or ASIC. It implements only the simulation behaviour of the language as described by the IEEE 1076 standard. NVC supports popular verification frameworks including OSVVM, UVVM, VUnit and cocotb. See below for installation instructions.

Vendor Libraries

NVC provides scripts to compile popular verification frameworks and the simulation libraries of common FPGA vendors

• For OSVVM use nvc --install osvvm
• For UVVM use nvc --install uvvm
• For Xilinx ISE use nvc --install ise
• For Xilinx Vivado use nvc --install vivado and additionally nvc --install xpm_vhdl
  if you require simulation models of the XPM macros
• For Altera Quartus use nvc --install quartus
• For Lattice iCEcube2 use nvc --install icecube2
• For Free Model Foundry common packages use nvc --install fmf

[Open Source Survey] From RTL to Fabrication

Emilio Isaac Baungarten-Leon

From RTL to Fabrication: Survey of Open-Source EDA Tools and PDKs

Electronics 2026, 15(5), 1048;

DOI: 10.3390/electronics15051048

* Departamento de Electromecánica, Universidad Autónoma de Guadalajara, Zapopan 45129, Mexico

Abstract: This article aims to synthesize the current ecosystem of open-source tools for Integrated Circuit (IC) design, covering the entire digital design flow from Register-Transfer Level (RTL) description to fabricable layouts. The survey categorizes and analyzes tools across major stages of design, including code-generation tools, logic synthesis, simulation, and physical design flow. Special emphasis is given to the fabricable open-source Process Design Kit (PDK), which enables the physical realization of open-hardware projects. By examining interoperability, limitations, and maturity across this toolchain, the article provides a comprehensive overview of the Electronic Design Automation (EDA) landscape and identifies the research and educational opportunities that arise from democratizing silicon design through open and reproducible workflows.

Fig: (a) IC design flow illustrating the complete process from RTL specification through logic synthesis, physical design (floorplanning, placement, clock tree synthesis, routing), verification, and final GDSII generation for fabrication. (b) FPGA design flow showing the progression from RTL description to synthesis, technology mapping, placement-and-routing on the target FPGA fabric, bitstream generation, and device configuration.

Acknowledgments: The APC was funded by Universidad Autónoma de Guadalajara (UAG), financial support provided through its Fondo Semilla. The author gratefully acknowledges the Universidad Autónoma de Guadalajara (UAG) for the financial support provided through its Fondo Semilla program, which covered the article processing charges and enabled the publication of this work. During the preparation of this manuscript, the authors utilized GPT-5.2 solely to enhance the clarity, grammar, and overall quality of the English text. The author reviewed and edited all AI-assisted content and takes full responsibility for the accuracy, originality, and integrity of the final manuscript.

Table A1. Main open-source EDA tools and their official repositories

Category	Tool	Official Link
Code-Generation Tools	PandA Bambu HLS	https://github.com/ferrandi/PandA-bambu (accessed on 20 January 2026)
	Kiwi Compiler	https://www.cl.cam.ac.uk/~djg11/kiwi/ (accessed on 20 January 2026)
	LegUp HLS	https://github.com/LegUpComputing/legup-examples?tab=readme-ov-file (accessed on 20 January 2026)
	ROCCC	http://roccc.cs.ucr.edu/ (accessed on 20 January 2026)
	PyMTL3	https://github.com/pymtl/pymtl3 (accessed on 20 January 2026)
	Chisel	https://www.chisel-lang.org/ (accessed on 20 January 2026)
	SpinalHDL	https://github.com/SpinalHDL/SpinalHDL (accessed on 20 January 2026)
	Pyverilog	https://github.com/PyHDI/Pyverilog (accessed on 20 January 2026)
	Amaranth HDL	https://github.com/amaranth-lang (accessed on 20 January 2026)
LLM-Based Code Generation	RTLCoder	https://github.com/hkust-zhiyao/RTL-Coder (accessed on 20 January 2026)
	Spec2RTL-Agent	https://cirkitly.kernex.sbs/ (accessed on 20 January 2026)
	OriGen	https://github.com/pku-liang/OriGen (accessed on 20 January 2026)
	AutoChip	https://github.com/shailja-thakur/AutoChip (accessed on 20 January 2026)
	CodeV	https://github.com/cluesmith/codev (accessed on 20 January 2026)
	VeriCoder	https://github.com/Anjiang-Wei/VeriCoder (accessed on 20 January 2026)
	StarCoder	https://github.com/bigcode-project/starcoder (accessed on 20 January 2026)
	CodeLlama	https://github.com/meta-llama/codellama (accessed on 20 January 2026)
	DeepSeek-Coder	https://github.com/deepseek-ai/DeepSeek-Coder (accessed on 20 January 2026)
	CodeQwen	https://github.com/QwenLM/qwen-code (accessed on 20 January 2026)
	Gemini	https://gemini.google.com/ (accessed on 20 January 2026)
	GPT	https://chatgpt.com/ (accessed on 20 January 2026)
	ChatEDA	https://github.com/wuhy68/ChatEDA (accessed on 20 January 2026)
Synthesis Tools	Yosys	https://yosyshq.net/yosys/ (accessed on 20 January 2026)
	ABC (Berkeley)	https://people.eecs.berkeley.edu/~alanmi/abc/ (accessed on 20 January 2026)
	ODIN II (VTR)	https://docs.verilogtorouting.org/en/latest/odin/ (accessed on 20 January 2026)
	GHDL-Yosys Plugin	https://github.com/YosysHQ/yosys (accessed on 20 January 2026)
	Synlig	https://github.com/chipsalliance/synlig (accessed on 20 January 2026)
	Mockturtle (EPFL)	https://github.com/lsils/mockturtle (accessed on 20 January 2026)
Simulation & Verification Tools	Verilator	https://www.veripool.org/verilator/ (accessed on 20 January 2026)
	Icarus Verilog	https://steveicarus.github.io/iverilog/ (accessed on 20 January 2026)
	cocotb	https://www.cocotb.org/ (accessed on 20 January 2026)
	GTKWave	https://gtkwave.sourceforge.net/ (accessed on 20 January 2026)
	Yosys-SMTBMC	https://symbiyosys.readthedocs.io/en/latest/reference.html (accessed on 20 January 2026)
	EQY	https://github.com/YosysHQ/eqy (accessed on 20 January 2026)
	CoSA	https://github.com/cristian-mattarei/CoSA (accessed on 20 January 2026)
	OpenSTA	https://github.com/The-OpenROAD-Project/OpenSTA (accessed on 20 January 2026)
	OpenTimer	https://github.com/OpenTimer/OpenTimer (accessed on 20 January 2026)
	Tatum (VTR)	https://github.com/verilog-to-routing/tatum (accessed on 20 January 2026)
Physical Design Flow Tools	OpenROAD	https://theopenroadproject.org/ (accessed on 20 January 2026)
	OpenLane	https://github.com/The-OpenROAD-Project/OpenLane (accessed on 20 January 2026)
	iEDA	https://github.com/OSCC-Project/iEDA (accessed on 20 January 2026)
	SiliconComp	https://github.com/siliconcompiler/siliconcompiler (accessed on 20 January 2026)
Fabricable PDKs	SKY130	https://github.com/gdsfactory/skywater130 (accessed on 20 January 2026)
	GF180MCU	https://github.com/google/gf180mcu-pdk (accessed on 20 January 2026)
	IHP SG13G2	https://github.com/IHP-GmbH/IHP-Open-PDK (accessed on 20 January 2026)
	ICsprout55	https://github.com/openecos-projects/icsprout55-pdk (accessed on 20 January 2026)