[paper] Open-Source SkyWater 130 nm MOSFETs at 77K

F. Beall1, A. Rimal1, O. Seidel1, Y. Mei1, A. D. McDonald3, I. Parmaksiz5,1 V. A. Chirayath1, J. Asaadi1, D. Braga2, J. B. R. Battat4

DC Cryogenic Modeling of Open-Source SkyWater 130 nm MOSFETs at 77K Using BSIM4

arXiv:2604.21625v1 [cond-mat.mes-hall] 23 Apr 2026

1 The University of Texas at Arlington, Physics Department, Arlington, TX 76019, USA
2 Fermi National Accelerator Laboratory, Microelectronics Department, Batavia, IL 60510, USA
3 Instrumentation Frontier Scientific, Arlington, TX 76019, USA
4 Wellesley College, Physics and Astronomy Department, Wellesley, MA 02481, USA
5 Rice University, Physics Department, Houston, TX 77005, USA

Abstract: Cryogenic applications in high-energy physics (HEP) demand reliable, low-power CMOS electronics capable of operating at liquid nitrogen temperatures (77K). The open-source SkyWater 130nm (SKY130) CMOS process has previously been shown to operate at temperatures as low as 4K making it a promising candidate for HEP applications. In this work, we characterize and model SKY130 low-threshold voltage transistors at 77K, which is a temperature commonly used in modeling applications for liquid argon detectors. DC characteristic measurements were performed at both room temperature and liquid nitrogen temperature. We created a cryogenic modeling approach to produce a SPICE-compatible, isothermal BSIM4-based model for select transistor sizes at 77K. The resulting model agrees with data at 77K with an average error on the order of 20% (relative RMS) and shows no dependence on drain voltage. Due to the open-source nature of SKY130, we have made our models publicly available on Github. We hope this work will continue the trend for democratizing circuit design at cryogenic temperatures in high-energy physics by enabling open access to accurate cryogenic CMOS device models at 77K.

Fig: Hardware setup used for I-V measurements: (a) Schematic of the I-V measurement

system (b) Wirebonded SKY130 chip mounted on PCB

Acknowledgments: The authors would like to thank various engineers in the microelectronics department at FNAL for their guidance and assistance on this project: Albert Dyer for help operating the cryo-cooler, and Louis Dal Monte and Pamela Klabbers for PCB design. The authors would also like to extend gratitude to Andy Pender from Synopsys for assistance with the modeling software, Mystic™. This material is also based upon work supported by U.S. Department of Energy, Office of Science, Office of High Energy Physics under Award Number DE-SC0022296 and DE-SC00253485 as well as support from the University of Texas at Arlington’s Center for Advanced Detector Technologies.

[paper] Multi-Agent Self-Evolved ABC

Cunxi Yu and Haoxing Ren

Autonomous Evolution of EDA Tools: Multi-Agent Self-Evolved ABC

In 63rd ACM/IEEE Design Automation Conference (DAC ’26)

July 26–29, 2026, Long Beach, CA

DOI: 10.1145/3770743.3804221

Abstract: This paper introduces the first self-evolving logic synthesis framework, which leverages Large Language Model (LLM) agents to autonomously improve the source code of ABC, the widely adopted logic synthesis system. Our framework operates on the entire integrated ABC codebase, and the output repository preserves its single-binary execution model and command interface. In the initial evolution cycle, we bootstrap the system using existing prior open-source synthesis components, covering flow tuning, logic minimization, and technology mapping, but without manually injecting new heuristics. On top of this foundation, a team of LLM-based agents iteratively rewrites and evolves specific sub-components of ABC following our “programming guidance“ prompts under a unified correctness and QoR-driven evaluation loop. Each evolution cycle proposes code modifications, compiles the integrated binary, validates correctness, and evaluates quality-of-results (QoR) on multi-suite benchmarks including ISCAS 85/89/99, VTR, EPFL, and IWLS 2005. Through continuous feedback, the system discovers optimizations beyond human-designed heuristics, effectively learning new synthesis strategies that enhance QoR. We detail the architecture of this self-improving system, its integration with ABC, and results demonstrating that the framework can autonomously and progressively improve EDA tool at full million-line scale.

Fig: Overview of the multi-agent self-evolving framework for ABC. Specialized LLM agents evolve distinct subsystems (flow optimization, core algorithms, and mapping), with each iteration undergoing compilation, formal CEC verification, and full QoR evaluation. A planning agent coordinates global decisions, a coding agent implements edits, and all agents follow a shared rulebase and unified evaluation pipeline to enable coordinated, correctness-preserving improvements.

Acknowledgment: The authors would like to thank Prof. Zhiru Zhang and his students for their valuable feedback and insightful discussions.

May 2026 Event "ISHI Kai 3rd Anniversary Event

May 2026 Event ISHI Kai 3rd Anniversary Event 

Gift to Students, Newcomers, and Semiconductor Beginners!

Tokyo Venue

Contents

The ISHI Association has finally celebrated its third anniversary!
This time, we have collected content for students, newcomers, and semiconductor beginners. What should university teachers and those who have done open source semiconductors do to step up for students and newcomers? And what means are there? This time, there are also on-site participation slots in Tokyo and Fukuoka, so please join us. This is only available for applications for the Tokyo venue.

Click here to apply for the Fukuoka venue >> https://ishikai.connpass.com/event/381975/

The activity is done on Discord. We hope you will join us!
(If it is disabled, please contact Noritsuna Atmark ishi-kai.org) 
https://discord.gg/Sj47dJk8x7

Participation fee >> Free

[papers] Charge-Based MOSFET Compact Models with ACM-2

IEEE 17th Latin America Symposium on Circuits and System 

LASCAS, Arequipa, Peru

24-27 February 2026

[1] R. Fiorelli, M. Miguez and J. Núñez, "Exploring Charge-Based Mosfet Compact Models with ACM-2 as a Design-Oriented Paradigm," 2026 IEEE 17th Latin America Symposium on Circuits and System (LASCAS), Arequipa, Peru, 2026, pp. 1-5, doi: 10.1109/LASCAS67804.2026.11457086.

Abstract: Charge-based MOSFET compact models provide a physically consistent framework to describe transistor charges and capacitances across operating regimes. Unlike current-based approaches, they enforce charge conservation and yield reliable predictions of dynamic and RF behavior. This paper reviews the main charge-based formulations, ranging from industrial standards (BSIM, PSP, HiSIM) to academic compact models such as EKV and the recent ACM-2 five-parameter approach. We contrast their philosophies, complexity, and accuracy, highlighting the trade-offs between highly parameterized industrial models and compact analytical formulations oriented to design and education. Representative applications in analog/RF design, digital timing and power estimation are discussed. Particular attention is given to the lightweight ACM-2 model as a paradigmatic example of simplicity and analytical clarity. We conclude by outlining current challenges-advanced device architectures, quantum effects, and automated parameter extraction-and perspectives for future compact modeling in deeply scaled technologies.

[2] C. A. Dobrin, D. G. A. Neto, D. Gaidioz, P. Cathelin, S. Bourdel and M. J. Barragan, "RF Design-Oriented ACM Model Generation Using Parametric Test and Machine Learning Regression in 28nm FD-SOI CMOS Technology," 2026 IEEE 17th Latin America Symposium on Circuits and System (LASCAS), Arequipa, Peru, 2026, pp. 1-5, doi: 10.1109/LASCAS67804.2026.11457152.

Abstract: This paper presents a methodology for extracting design-oriented MOS transistor models from wafer-level parametric test (PT) data, enabling accurate post-fabrication circuit characterization that inherently accounts for process variability. Leveraging an advanced compact MOSFET (ACM) model, the approach employs a neural network regressor to predict critical RF transistor parameters, including DC characteristics, parasitic capacitances, and excess noise factor, from standard PT measurements routinely collected during production. The regressed parameters are gathered into a Verilog-A component that faithfully represents the electrical behavior of fabricated transistors, facilitating variability-aware simulation and performance analysis of RF integrated circuits without requiring additional test structures or any measurement overhead. Validation on 28 nm FD-SOI technology shows high prediction accuracy for NMOS devices, confirming the effectiveness of the methodology as a tool for supporting post-fabrication circuit simulations and process variability management.

[3] D. G. A. Neto, M. C. Schneider, M. J. Barragan, S. Bourdel and C. Galup-Montoro, "Benchmarking the Symmetry of MOSFET Compact Models with Emphasis on ACM2," 2026 IEEE 17th Latin America Symposium on Circuits and System (LASCAS), Arequipa, Peru, 2026, pp. 1-5, doi: 10.1109/LASCAS67804.2026.11457119.

Abstract: The symmetrically built MOS transistors of integrated circuits exhibit symmetric electrical behavior if the source and drain terminals are interchanged. Additionally, a series association of transistors is electrically “equivalent” to a single transistor. However, some of the compact MOSFET models do not comply with the requirements of symmetry and transistor equivalence. This paper reports tests of symmetry and of series association of transistors of some compact models available in circuit simulators. We show that the ACM2, a chargebased model in which the terminal voltages are referred to the substrate, is fully compliant with the transistor symmetry, but that some popular models are not. To test the symmetry property, we show examples of transistor current-voltage characteristics and derivatives up to the fifth order, and capacitance-voltage characteristics, all tests around  VDS=0 . A MOSFET binary current divider is employed to test the consistency of the model applied to a series association of transistors.

[paper] ATMAD: Compact Modeling with Parameter Extraction

Yuhang Zhang, Qing Zhang, Yang Shen, Bingyi Ye, Xiaojin Li, Yabin Sun, Yanling Shi, Yong‑Fu Li

ATMAD: Agile Transistor Compact Modeling with Parameter Extraction 

Based on Automatic Differentiation

ACM 1084-4309/2026/04-ART103

DOI: 10.1145/3797484

1. School of Integrated Circuits, East China Normal University, Shanghai, China
2. Department of Micro‑Nano Electronics, Shanghai Jiao Tong University, Shanghai, China
3. East China Normal University, Shanghai, China
4. Shanghai Jiao Tong University, Shanghai, China

Abstract: Compact models of transistors are essential for simulating and optimizing circuits with the use of SPICE simulation tool. Parameter extraction, which is calibrating these models, is essential to ensure their alignment with measured or simulated data. However, conventional parameter extraction methods are generally iterative and experience-dependent, requiring significant time and effort from modeling engineers. Moreover, as semiconductor devices and compact models become increasingly advanced, the need for a tailored extraction process for each model has become increasingly inefficient. To address the above challenges, this work proposes an agile transistor compact modeling framework, ATMAD. The proposed framework takes a compact model file and a set of electrical characteristic data as inputs, producing a calibrated model with minimal human intervention. ATMAD automatically retrieves the equations in the compact model and converts them into computational flow graphs, thus supporting different compact models with a generalized process. A graph unlooping technique is proposed to support automatic differentiation for compact models with implicit functions (e.g., series resistance and surface potential solving). Based on the computational flow graph, ATMAD adopts automatic differentiation technique to achieve automatic and parallel optimization of model parameters. The proposed ATMAD framework is validated on commonly-used compact models in academia and industry, showing its effectiveness for compact modeling for both 𝐼𝑉 and 𝐶𝑉 characteristics.

Fig. The overall flow of ATMAD framework

Acknowledgements: This work is supported in part by the Shanghai Explorer Program under Grant No. 25TS1410300 and 24TS1400200 and in part by the National Natural Science Foundation of China under Grants No. 62304133 and 62350610271.