IEEE 17th Latin America Symposium on Circuits and System
LASCAS, Arequipa, Peru
24-27 February 2026
[1] R. Fiorelli, M. Miguez and J. Núñez, "Exploring Charge-Based Mosfet Compact Models with ACM-2 as a Design-Oriented Paradigm," 2026 IEEE 17th Latin America Symposium on Circuits and System (LASCAS), Arequipa, Peru, 2026, pp. 1-5, doi: 10.1109/LASCAS67804.2026.11457086.Abstract: Charge-based MOSFET compact models provide a physically consistent framework to describe transistor charges and capacitances across operating regimes. Unlike current-based approaches, they enforce charge conservation and yield reliable predictions of dynamic and RF behavior. This paper reviews the main charge-based formulations, ranging from industrial standards (BSIM, PSP, HiSIM) to academic compact models such as EKV and the recent ACM-2 five-parameter approach. We contrast their philosophies, complexity, and accuracy, highlighting the trade-offs between highly parameterized industrial models and compact analytical formulations oriented to design and education. Representative applications in analog/RF design, digital timing and power estimation are discussed. Particular attention is given to the lightweight ACM-2 model as a paradigmatic example of simplicity and analytical clarity. We conclude by outlining current challenges-advanced device architectures, quantum effects, and automated parameter extraction-and perspectives for future compact modeling in deeply scaled technologies.
[2] C. A. Dobrin, D. G. A. Neto, D. Gaidioz, P. Cathelin, S. Bourdel and M. J. Barragan, "RF Design-Oriented ACM Model Generation Using Parametric Test and Machine Learning Regression in 28nm FD-SOI CMOS Technology," 2026 IEEE 17th Latin America Symposium on Circuits and System (LASCAS), Arequipa, Peru, 2026, pp. 1-5, doi: 10.1109/LASCAS67804.2026.11457152.
Abstract: This paper presents a methodology for extracting design-oriented MOS transistor models from wafer-level parametric test (PT) data, enabling accurate post-fabrication circuit characterization that inherently accounts for process variability. Leveraging an advanced compact MOSFET (ACM) model, the approach employs a neural network regressor to predict critical RF transistor parameters, including DC characteristics, parasitic capacitances, and excess noise factor, from standard PT measurements routinely collected during production. The regressed parameters are gathered into a Verilog-A component that faithfully represents the electrical behavior of fabricated transistors, facilitating variability-aware simulation and performance analysis of RF integrated circuits without requiring additional test structures or any measurement overhead. Validation on 28 nm FD-SOI technology shows high prediction accuracy for NMOS devices, confirming the effectiveness of the methodology as a tool for supporting post-fabrication circuit simulations and process variability management.
Abstract: The symmetrically built MOS transistors of integrated circuits exhibit symmetric electrical behavior if the source and drain terminals are interchanged. Additionally, a series association of transistors is electrically “equivalent” to a single transistor. However, some of the compact MOSFET models do not comply with the requirements of symmetry and transistor equivalence. This paper reports tests of symmetry and of series association of transistors of some compact models available in circuit simulators. We show that the ACM2, a chargebased model in which the terminal voltages are referred to the substrate, is fully compliant with the transistor symmetry, but that some popular models are not. To test the symmetry property, we show examples of transistor current-voltage characteristics and derivatives up to the fifth order, and capacitance-voltage characteristics, all tests around VDS=0 . A MOSFET binary current divider is employed to test the consistency of the model applied to a series association of transistors.
