[C4P] SBCCI2027 Florianópolis

40th SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN

SBCCI2027

August 23 to 27, 2027, Florianópolis (BR)

General Chair José Luís Güntzel, UFSC, Brazil Ney Calazans, UFSC, Brazil Program Chairs Fernando Moraes, PUCRS, Brazil Samuel Pagliarini, Carnegie Mellon, USA Exhibition Chairs Marcelo Lubaszewski, UFRGS, Brazil Paulo Butzen, UFRGS, Brazil Finance Chair Fabian Cabrera Riaño, UFSC, Brazil Panels Chair Omar Paranaiba Vilela Neto, UFMG, Brazil Local Arrangements Chairs César Rodrigues, UFSC, Brazil Walter Carpes Jr., UFSC, Brazil Publicity Chair Ricardo Reis, UFRGS, Brazil

SBCCI is an international forum dedicated to integrated circuits and systems design, test and electronic design automation (EDA), held annually in Brazil. The 40th SBCCI will take place in Florianópolis, State of Santa Catarina, Brazil. The symposium brings together researchers in EDA, IC design and test. It includes technical sessions, tutorials, panels, an exhibition and working group meetings. Proceedings will be published in IEEE Xplore. Best papers will be invited to submit extended versions to IEEE Design & Test, IEEE OJCAS, and JICS. Call for Papers www.sbcci.org.br Important Dates Paper Submission Deadline: April 5, 2027 Notification of Acceptance: May 14, 2027 Camera-Ready Deadline: June 4, 2027 Sponsored by SBC – Brazilian Computer Society SBMicro – Brazilian Microelectronics Society IEEE Circuits & Systems Society IEEE CEDA – Council on EDA Co-Sponsored by IFIP WG10.5  International Federation for Information Processing Organized by UFSC – Federal University of Santa Catarina

[paper] Datasheet‑Driven Automated Device Modeling

Siddharth Mohan, Mike Engelhardt, Tim McCune, and Jeff Strang

Datasheet-Driven Automated Device Modeling

22nd IEEE SMACD (2026) Dresden, Germany

DOI: 10.1109/SMACD70206.2026.11647759

* Qorvo Inc., CA, USA

Abstract: Accurate device models are a prerequisite fortrustworthy SPICE simulations, yet generating compact models from vendor datasheets has traditionally been time‑consuming anderror‑prone. QSPICE adds a Model Generators that build MOSFET, JFET, and diode models from commonly available datasheet values in minutes, integrating directly with its mixed‑mode simulator. We formalize a datasheet‑drivenworkflow (digitization, automated parameter mapping, simulation), and report qualitative validation across ID–VDS, ID–VGS, Coss, Qg, and IS–VSD characteristics using overlays from an industrial case study. We discuss adoption guidance, limitations, and opportunities for further quantitative benchmarking.

Fig: Automated model-generation workflow diagram.

AOB414 datasheet Available: https://www.designing-electronics.com/the-qspice-model-generator/

[book] The FET Centennial: Celebrating the Field-Effect Transistor

The FET Centennial: Celebrating the Field-Effect Transistor

Cary Y. Yang (Editor), Cor Claeys (Editor), 

Arokia Nathan (Editor), Bin Zhao (Editor)

ISBN: 978-1-394-40648-7 Sept. 2026 Wiley-IEEE Press 976pp
 

Abstract: Presents a landmark volume documenting 100 years of field-effect transistor innovation and applications. 

The invention of the field-effect transistor (FET) in 1925 transformed the trajectory of modern civilization, enabling virtually every electronic device in existence today. From the earliest integrated circuits to the most advanced computers and smartphones, the FET has served as the indispensable foundation of contemporary information technology. The FET Centennial: Celebrating the Field-Effect Transistor commemorates this milestone by gathering a distinguished group of contributors to provide a comprehensive account of the device’s history, global development, diverse applications, and potential future directions. 

History and Evolution of FET Technology Table of Contents

• About the Editors xxi
• About the Contributors xxiv
• A Special Tribute in Memory of Chih-Tang Sah [1932–2025] xxxv
• Foreword xxxvii
• Preface xxxix

• 1 The Miraculous Evolution of the Field-Effect Transistor (FET)
  Hiroshi Iwai
  • 1.1 Introduction
  • 1.2 1925–1960: Early Concepts and Challenges in MOSFET Development
  • 1.3 1960–1970: The MOSFET Instability Problem
  • 1.4 From MOS ICs to MOS LSIs: 1965–1969
  • 1.5 Technologies for MOS Integrated Circuits Developed Between 1965 and 1970
  • 1.6 First-Generation LSIs—Al- or Si-Gate PMOS LSIs
  • 1.7 Second-Generation LSI
  • 1.8 First Generation of VLSI
  • 1.9 Transition from NMOS to CMOS
  • 1.10 Advances in Scaling Technologies
  • 1.11 Challenges in Sub-50 nm Scaling
  • 1.12 Development of RF CMOS Device Technology
  • 1.13 Post-2000: Limits of Miniaturization
  • 1.14 Future Prospects
  • 1.15 Summary and Concluding Remarks
• 2 MOSFET Device Structures and Physical Models
  Yuan Taur
  • 2.1 MOSFET Device Structures
  • 2.2 MOSFET Physical Models
  • 2.3 Conclusion
• 3 Field-Effect Transistor R&D in the United States
  Robert Chau, Suman Datta
  • 3.1 Introduction
  • 3.2 Early US FET R&D
  • 3.3 Birth of the MOSFET at Bell Labs
  • 3.4 Advent of CMOS
  • 3.5 Moore's Law: Classical Scaling
  • 3.6 Moore's Law: Equivalent Scaling
  • 3.7 Inflection Point for FETs
  • 3.8 Zetta-Scale Computing
  • 3.9 Conclusion
• 4 Asia's FET R&D Innovations
  Carlos H. Diaz, Akira Toriumi
  • 4.1 Introduction
  • 4.2 Asia's Rise in the Semiconductor Industry
  • 4.3 Logic Technology
  • 4.4 Memory Technology
  • 4.5 Thin Film Transistors
  • 4.6 III–V FETs
  • 4.7 Power FETs
  • 4.8 Concluding Remarks
• 5 Fully Depleted SOI Technology
  Thomas Skotnicki, Stephane Monfray
  • 5.1 Prologue
  • 5.2 Introduction
  • 5.3 From Equation to Demonstration
  • 5.4 From Lab to Fab
  • 5.5 Technology Expansion and Scaling
  • 5.6 Summary and Perspective
• 6 MOS-Based RAM
  Jeonghoon Oh, Sangyeop Baeck
  • 6.1 DRAM Transistor Technology
  • 6.2 SRAM Transistor Technology
  • 6.3 Conclusion
• 7 Floating Gate FETs as Nonvolatile Memories
  Stefan K. Lai, Koji Sakui, Riichiro Shirota
  • 7.1 Introduction
  • 7.2 EPROM and EEPROM
  • 7.3 NOR Flash
  • 7.4 NAND Flash
  • 7.5 Summary and Acknowledgment
• 8 FET-Based Logic Devices and Systems
  Ghavam G. Shahidi
  • 8.1 Introduction
  • 8.2 From Dash-Dots to FETs
  • 8.3 First Commercial FET Microprocessor
  • 8.4 Personal Computer
  • 8.5 Microprocessors
  • 8.6 DSP and Communications
  • 8.7 The iPhone
  • 8.8 Data Centers
  • 8.9 GPUs and AI
  • 8.10 Energy Per Switch
• 9 SiC FETs
  Tsunenobu Kimoto
  • 9.1 Introduction
  • 9.2 Interface Properties
  • 9.3 SiC Power MOSFETs
  • 9.4 SiC Power JFETs
  • 9.5 SiC CMOS ICs
  • 9.6 SiC JFET ICs
  • 9.7 Applications and Outlook
• 10 III–V and III-N FETs
  Giovanni Ghione, Matteo Meneghini
  • 10.1 III–V FETs and ICs
  • 10.2 III-N FETs
  • 10.3 Conclusions
• 11 CMOS Image Sensors
  Yusuke Oike
  • 11.1 Introduction
  • 11.2 Historical Background
  • 11.3 Technological Advancements
  • 11.4 Stacked Device Technologies
  • 11.5 Pixel Performance Metrics
  • 11.6 Sensing Extensions
  • 11.7 Emerging Technologies
• 12 Thin-Film Transistor
  Yue Kuo, Arokia Nathan
  • 12.1 TFT Development History
  • 12.2 Market Size
  • 12.3 Structures and Processes
  • 12.4 Figures of Merit
  • 12.5 Material–Process–Device Relationship
  • 12.6 Applications
  • 12.7 Emerging Challenges
  • 12.8 Summary
• 13 Process Integration for Hyper-Scaled MOSFETs
  Kelin J. Kuhn
  • 13.1 Introduction
  • 13.2 Self-Alignment
  • 13.3 Replacement Gate
  • 13.4 Fully Depleted Channels
  • 13.5 What Happens Next?
• 14 50 Years of RF CMOS Design
  Behzad Razavi
  • 14.1 RF CMOS Is Born
  • 14.2 SPICE Is Born
  • 14.3 Direct-Conversion RX
  • 14.4 Analog Designers
  • 14.5 RF CMOS Again
  • 14.6 High Integration
  • 14.7 ΔΣ Synthesizer
  • 14.8 Direct Conversion
  • 14.9 Noise Simulator
  • 14.10 Direct Conversion Matures
  • 14.11 Scaling Effects
  • 14.12 UWB, Cognitive, WiGig, 5G
  • 14.13 Multiband Radios
  • 14.14 Phased-Array Transceivers
  • 14.15 Conclusion
• 15 Compact FET-Based Device Modeling
  Mitiko Miura-Mattausch, Hans Jürgen Mattausch
  • 15.1 Introduction
  • 15.2 Transistor Operations
  • 15.3 MOSFET Equations
  • 15.4 Modeling Approaches
  • 15.5 Model Standardization
  • 15.6 Advanced Compact Modeling
  • 15.7 MOSFET-Descendant Models
  • 15.8 Advanced FET Generations
  • 15.9 Future Trends
  • 15.10 Circuit Design Perspectives
  • 15.11 Conclusion
• 16 Evolution of Photolithography
  Anthony Yen, Winfried Kaiser, Akiyoshi Suzuki
  • 16.1 Introduction
  • 16.2 Contact/Proximity Printing
  • 16.3 1× Projection Imaging
  • 16.4 Step-and-Repeat Lithography
  • 16.5 Deep UV Lithography
  • 16.6 193nm and 157nm Lithography
  • 16.7 Immersion Lithography
  • 16.8 EUV Lithography
  • 16.9 Summary and Outlook
• 17 Back-End-of-Line Interconnect Technology
  Takayuki Ohba, Takashi Yoda
  • 17.1 Introduction
  • 17.2 Interconnect Module Evolution
  • 17.3 3D Integration
  • 17.4 Variation and Beyond
  • 17.5 2.5D and 3D Damascene Processes
  • 17.6 Conclusion
• 18 Three-Dimensional FET
  Digh Hisamoto, Samar K. Saha
  • 18.1 Introduction
  • 18.2 Dawn of Devices and Computers
  • 18.3 Transistor Computer
  • 18.4 Golden Age of Planar MOSFETs
  • 18.5 FinFET Era
  • 18.6 Conclusions
• 19 GAAFET Technologies
  Dong-Won Kim
  • 19.1 Introduction
  • 19.2 GAAFET Candidates
  • 19.3 Operation
  • 19.4 Design Considerations
  • 19.5 Reliability Challenges
  • 19.6 DTCO for GAAFET
  • 19.7 3D Scaling
  • 19.8 Conclusion
• 20 2D-FET Contact Engineering
  Chandan Biswas, Deji Akinwande
  • 20.1 Introduction
  • 20.2 Electronic Property Challenges
  • 20.3 Contact Engineering
  • 20.4 Quantum Limit of Contact Resistance
  • 20.5 Summary
• 21 Carrier Transport in MOSFETs
  Mark Lundstrom
  • 21.1 Introduction
  • 21.2 A Focus on the Source
  • 21.3 Drift-Diffusion Transport
  • 21.4 Velocity-Saturated MOSFET
  • 21.5 Non-Local Transport
  • 21.6 Ballistic MOSFET
  • 21.7 Quasi-Ballistic MOSFET
  • 21.8 Quantum Transport
  • 21.9 Discussion
  • 21.10 Conclusions
• 22 What Is Next for FET?
  Tsu-Jae K. Liu, Tahir Ghani, Carolyn Duran
• 22.1 Introduction
• 22.2 Tunnel FET
• 22.3 Negative Capacitance FET
• 22.4 High-Mobility Channel Transistors
• 22.5 NEMS Switch
• 22.6 Sustainability
• 22.7 Summary

<https://books.google.ch/books?id=wnUEEgAAQBAJ>

Fwd: The 4th Annual SemiX Summit - Registrations are open now

We are pleased to announce

4th Annual SemiX Summit

will be held at IIT Bombay

from October 14–17, 2026

Click the button to grab your spot: Register Now

This Summit is especially meaningful for us as it marks the year SemiX transforms from a Research Centre into an Academic Centre

Building on the success of the first three editions, and incorporating valuable feedback from past participants, we have redesigned the Summit program to deliver an even richer experience for students, researchers, entrepreneurs, and industry professionals. 

The key highlights of the 4th summit include: 

1. For the first time, we dedicate one day to students to learn the fundamentals of the semiconductor industry including applications, technologies, entrepreneurship, and career pathways they could potentially explore in the space. 

2. Focus on two key application segments (Power and Artificial Intelligence) to understand their markets, system requirements, and semiconductor technologies from design to manufacturing. 

3. In his keynote address, Raj Nair (SVP, Tata Electronics), will share the execution story of the Tata Fab at Dholera and his insights on the enabling ecosystem and talent for the success of Tata’s plans. 

4. An Entrepreneurship track that will focus on (among other aspects) pre-incubation and how SemiX supports current and future entrepreneurs.

5. A post-summit day for Special Interest Groups to dive deeper into exciting topics in semiconductors. 

The 4th Annual SemiX Summit will continue our tradition of fostering learning, collaboration, and meaningful networking across the semiconductor value chain. We look forward to welcoming you to IIT Bombay! 

Come, let us Realize India's Semiconductor Mission. Together!

 

[paper] NetlistBench: SPICE Netlist Evaluation LLM Reliability

Ma, Jiarui, Jianghan Wang, Yuheng Ma, Ziyi Zhuang, and Xiaoguang Liu

"NetlistBench: Evaluating LLM Reliability in SPICE Netlist Recognition and Manipulation" 

In Proceedings of ACM, New York, NY, 8 pages

arXiv: 2608.12197 (2026)

* Southern University of Science and Technology, School of Microelectronics Shenzhen (CN)

Abstract: Large Language Models (LLMs) are increasingly used in circuit design workflows, yet their reliability on simulator-facing SPICE netlist recognition and manipulation remains poorly understood and is rarely separated from high-level design reasoning. Although netlists are textual, they encode structured circuit objects through topology and parameters. We present NetlistBench, a structure verified benchmark for SPICE netlist recognition and manipulation. NetlistBench contains 2,342 cases across 24 task families, covering parameter and connectivity recognition and edits, hierarchical operations, equivalence judgment, and long-horizon compound editing. Model outputs are evaluated by a deterministic structure aware oracle. Across six non-thinking LLMs, performance varies substantially with operation-level structural complexity. Simple local edits reach 96%–100% accuracy, while device addition drops to 41%–83% and equivalence judgment to 49%–90%. Enabling reasoning substantially improves weaker models but does not eliminate structure-preservation failures, with performance still degrading sharply as the edit horizon increases. NetlistBench identifies netlist reliability as a distinct bottleneck for trustworthy LLM-based circuit design automation.

Fig: SPICE netlists as a common representation layer in LLM-based circuit design workflows.