Who should come? Chip designers, EDA developers, researchers, students, and anyone curious about building silicon without proprietary lock-in. All experience levels welcome.
Faculty of Electrical EngineeringTržaška cesta 25SI-1000 Ljubljana
Faculty of Electrical EngineeringTržaška cesta 25SI-1000 Ljubljana
| Start | End | Topic |
|---|---|---|
| 8:00 | 8:30 | Participant registration, organizational introduction |
| 8:30 | 9:00 | FET100 Inauguration Speech¹: Prof. K. Detka, IEEE EDS Poland |
| 9:00 | 10:30 |
OpenSilicon DIY Integrated Circuits²: Dr. Krzysztof Herman, IHP (D) Introduction to analog design in an open-source environment (Tools overview: Xschem, Ngspice, IHP-Open-PDK, workflow basics) |
| 10:30 | 10:45 | Coffee break |
| 10:45 | 12:30 | Analog schematic design in Xschem best practices, parameterization, DC, AC, and transient simulations (live demo) |
| 12:30 | 13:30 | FET100 Luncheon Talk³: W. Grabinski, IEEE EDS R8 Chair |
| 13:30 | 15:00 | Design of a sample analog circuit operation analysis, Monte Carlo simulations, mismatch analysis, parameter verification (live demo) |
| 15:00 | 15:15 | Coffee break |
| 15:15 | 17:00 | Introduction to layout in KLayout, analog design principles (matching, symmetry, noise minimization), PyCells mask design automation (live demo) |
| 17:00 | 18:00 | Complete design flow: from schematic to verification (LVS/DRC process overview), fillers, chip finishing, sign-off (live demo) |
| 18:00 | 18:30 | Q&A session, workshop summary |
| 18:30 | >> | FET100 Celebration Appero |
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Prof. Kwantae Kim, Analog Integrated Circuits at Aalto University, recorded additional videos that cover walkthroughs of the CAD exercises in his Integrated Analog Systems course. These videos should provide useful guidance for ADC design simulation and verification practice!