[100FET] IEEE EDS Egypt Chapter

IEEE EDS Egypt Chapter - 100 Years FET

Theme: Overview and celebration of 100 years of FET research
Location: Zewail City of Science and Technology Campus; October Gardens; 6 of October City
Date: Sept. 27-28, 2026

Main Objectives:

This event celebrates the 100th anniversary of the Field-Effect Transistor (FET) by highlighting its evolution over the past century and exploring future trends in electron devices. It also promotes the activities and membership of the IEEE EDS Egypt Chapter. The event aims to:

• Technical Advancement: Discuss recent developments in FET fabrication, modeling, simulation, and operation
• Knowledge Exchange: Share insights on the historical evolution and future directions of FET technologies
• Professional Networking: Foster collaboration among students, researchers, academics, and industry professionals
• Skill Development: Provide hands-on TCAD workshops to enhance practical device simulation skills
• Membership Growth: Increase the visibility of the IEEE EDS Egypt Chapter and encourage new memberships

Agenda

Time	Activity	Description
	Day 1	Sunday, 27th of September 2026
08:30 – 09:30	Registration	Welcoming participants and distribution of materials
09:30 – 10:00	Welcome Speech	Welcome speeches by the faculty leaders
10:00 – 11:00	Distinguished Lecturer #1 Dr. Hisham Omran	Focus on FET evolution
11:00 – 12:00	Networking Break	Refreshments & snacks
12:00 – 13:00	Distinguished Professor #2	Focus on FET research trends
13:00 – 14:00	Women in Engineering Talk Dr. Shereen Youssef	Talk by IEEE WIE Egypt Chair
14:00 – 15:00	Q&A Interactive Discussion	Interactive discussion: - Academia vs. Industry in FETs
	Day 2	Monday, 28th of September 2026
08:30 – 09:00	Registration	Welcoming participants and distribution of materials
09:00 – 11:00	Workshop #1: TCAD Modelling of FET Devices Eng. Amr W. Shalaby	TCAD workshop #1: - Introduction to the TCAD tool - Simulation of a MOSFET - Doping electrical characterization
11:00 – 12:00	Networking Break	Refreshments
12:00 – 13:00	Workshop #2 Eng. Yasmine AbdulAal Senior design engineer at Siemens	TCAD workshop #2 - Compact modelling for next-gen electronics
13:00 – 13:30	Panel / Q&A	TCAD in academia and industry
13:30 – 14:30	Closing Ceremony	Certificates and giveaways

[paper] GaN HEMT Biosensor

Ashkhen Yesayan and Jean-Michel Sallese

Modeling and Sensitivity Analysis of GaN HEMT Biosensor

Biosensors: Section Biosensor and Bioelectronic Devices (2026), 16(9), 520

DOI: 10.3390/bios16090520 

* STI-EDLab, EPFL, Lausanne (CH)

Abstract: Gallium nitride (GaN) high-electron-mobility transistor (HEMT) biosensors have recently emerged as promising platforms for highly sensitive and label-free detection of biomolecules. Their exceptional electrical properties, including high carrier mobility, together with the wide bandgap and strong chemical bonds of GaN materials, provide excellent stability under high temperatures, ionizing radiation, and chemically harsh environments. Despite significant experimental progress, comprehensive analytical models capable of linking biomolecular recognition events to the electrical response of GaN biosensors remain limited. This work presents a physics-based, design-oriented analytical modeling framework for AlGaN/GaN HEMT biosensors. The model incorporates biomolecular binding kinetics, the dielectric properties of the hybrid system, and electrostatic coupling to the transistor channel conductivity. Numerical simulations are performed using commercial multiphysics software to validate the analytical model. The developed framework provides physical insight into the mechanisms governing biosensor operation and offers practical guidelines for the optimization and comparative assessment of HEMT/MIS-HEMT biosensor architectures.

FIG: Typical GaN HEMT structure with a simplified representation of the functionalization and diffuse layers (not to scale) and corresponding IV plot at different gating potentials induced by analyte concentration variations, obtained from the analytical model and numerical simulations.

Acknowledgments: This work was funded by the SNSF Foundation project 200021 213116. During the preparation of this manuscript the authors used GPT-5.6 Luna to draw the picture in Figure 1. The authors have reviewed and edited the output and take full responsibility for the content.

[FOSS] AI IC Designs

Harald Pretl, Kevin Cameron, Jun‑ichi Okamura

FOSS AI IC Designs Examples

Intensive work over last three months was carried out by Prof. Harald Pretl together with an AI coding agent, thru which a substantial chip‑design knowledge base was built. At this stage, the AI agent is able to design, simulate, and layout a low‑noise, low‑voltage bandgap reference plus LDO with minimal manual intervention (along with many additional circuits that will be showcased later). The rapid progress in capability development is highly impressive.

The entire implementation was performed in OpenPDK 130nm CMOS using IIC‑OSIC‑TOOLS with almost no human involvement. The resulting layout is densely packed, the floorplan is coherent, and a manually created version would not differ significantly. Dummy structures were inserted for matching, and common‑centroid placement was applied to critical MOSFET devices.

Significant progress has also been achieved by Kevin Cameron, primarily on the simulation side, covering complete digital and AMS/RF domains. The work described in the linked repository has been developed and advanced accordingly, with sv2ghdl, which translates SystemVerilog RTL into VHDL for use with GHDL and NVC simulators. The generated VHDL leverages simulator extensions that go beyond what SystemVerilog offers, including multi‑UDN wires, bidirectional components, and improved unknown‑state handling

<https://github.com/kev-cam/sv2ghdl/blob/main/README.md>

A beta version of an automatic P&R tool for the OpenPDK TR‑1um was developed by Jun‑ichi Okamura using Claude AI and FOSS KLayout API and accompanying verification scripts. The flow is based on the newly updated standard‑cell library, incorporating both LEF and Liberty files, and STA analysis is now supported. Regression testing was carried out on three designs: I²C, SPI, and TD4

<https://lnkd.in/gMy3ThYm>

The synthesis and automatic P&R of TD4, an educational 4‑bit CPU, were completed by Jun‑ichi Okamura using Claude AI and the OpenPDK TR‑1um flow. A custom 8×16 register file was designed, the standard‑cell height was reduced, and a simplified Liberty (.lib) file was created to enable static timing analysis. The final chip implementation is made up of 4225 devices.

[githib] Teaching Analog Electronics in Minecraft

Rodrigo Picos, Stavros G. Stavrinides, George Stavrinides, Ariadna Picos, and Gerard Picos.

CircuitSimCraft: a Fabric mod for teaching analog electronics in Minecraft

https://github.com/rpicos-uib/circuitsimcraft (2026)

CircuitSimCraft: a Fabric mod that turns Minecraft into an analog electronics lab. Place resistors, capacitors, inductors and memristors as blocks, wire them up, drive them with power supplies and function generators, and probe the live voltage/current with a handheld oscilloscope — all backed by a real modified-nodal-analysis (MNA) circuit solver, the same family of algorithm SPICE uses, not a scripted approximation.

This is a teaching tool: the goal is for the in-game behavior to actually match what you'd see on a real bench (RC charge curves, RL transients, a memristor's resistance drifting with accumulated charge), just at Minecraft-tick timescales instead of real-world ones.

[paper] 12nm FinFETs from 292K to 10mK

D. Lee, J. Lee, L. Jin, R. Rangaraj, L. Shao and J. S. Walling

12nm FinFETs from 292K to 10mK:

Characterization and a Temperature-Continuous Compact Model for Qubit Control

Preprint arXiv:2609.11963 (19 Aug 2026)

1 Bradley Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, VA, USA

Abstract: We report cryogenic characterization and compact modeling of GlobalFoundries (GF) 12LP regular-voltagethreshold (RVT) n- and p-FinFETs, measured from 292K to 10mK. Both devices retain sub-Kelvin gate control without carrier freeze-out, with the n-type device exhibiting an intrinsic subthreshold slope (SS) floor of 24.8 mV/dec. To bypass high on-chip series routing resistance that confounds peak-gm extraction, we adopt a fixed-current (3.26 μA/μm) methodology. These low current metrics inform a continuous 1.36K to 292K compact model using dynamic parameter injection, preserving room temperature process development kit (PDK) qualification.

Fig: Measured transfer characteristics at |VDS,ext| = 0.8V, shaded dark to light with increasing temperature. Drain current is normalized to gate width, so the dotted line marks the constant-current threshold criterion at ICC = 1μA/μm.

Acknowledgment: The 12nm finFET IC fabrication was provided by GlobalFoundries as part of their University Partnership Program.