[FOSS] AI IC Designs

Harald Pretl, Kevin Cameron, Jun‑ichi Okamura

FOSS AI IC Designs Examples

Intensive work over last three months was carried out by Prof. Harald Pretl together with an AI coding agent, thru which a substantial chip‑design knowledge base was built. At this stage, the AI agent is able to design, simulate, and layout a low‑noise, low‑voltage bandgap reference plus LDO with minimal manual intervention (along with many additional circuits that will be showcased later). The rapid progress in capability development is highly impressive.

The entire implementation was performed in OpenPDK 130nm CMOS using IIC‑OSIC‑TOOLS with almost no human involvement. The resulting layout is densely packed, the floorplan is coherent, and a manually created version would not differ significantly. Dummy structures were inserted for matching, and common‑centroid placement was applied to critical MOSFET devices.

Significant progress has also been achieved by Kevin Cameron, primarily on the simulation side, covering complete digital and AMS/RF domains. The work described in the linked repository has been developed and advanced accordingly, with sv2ghdl, which translates SystemVerilog RTL into VHDL for use with GHDL and NVC simulators. The generated VHDL leverages simulator extensions that go beyond what SystemVerilog offers, including multi‑UDN wires, bidirectional components, and improved unknown‑state handling

<https://github.com/kev-cam/sv2ghdl/blob/main/README.md>

A beta version of an automatic P&R tool for the OpenPDK TR‑1um was developed by Jun‑ichi Okamura using Claude AI and FOSS KLayout API and accompanying verification scripts. The flow is based on the newly updated standard‑cell library, incorporating both LEF and Liberty files, and STA analysis is now supported. Regression testing was carried out on three designs: I²C, SPI, and TD4

<https://lnkd.in/gMy3ThYm>

The synthesis and automatic P&R of TD4, an educational 4‑bit CPU, were completed by Jun‑ichi Okamura using Claude AI and the OpenPDK TR‑1um flow. A custom 8×16 register file was designed, the standard‑cell height was reduced, and a simplified Liberty (.lib) file was created to enable static timing analysis. The final chip implementation is made up of 4225 devices.

[githib] Teaching Analog Electronics in Minecraft

Rodrigo Picos, Stavros G. Stavrinides, George Stavrinides, Ariadna Picos, and Gerard Picos.

CircuitSimCraft: a Fabric mod for teaching analog electronics in Minecraft

https://github.com/rpicos-uib/circuitsimcraft (2026)

CircuitSimCraft: a Fabric mod that turns Minecraft into an analog electronics lab. Place resistors, capacitors, inductors and memristors as blocks, wire them up, drive them with power supplies and function generators, and probe the live voltage/current with a handheld oscilloscope — all backed by a real modified-nodal-analysis (MNA) circuit solver, the same family of algorithm SPICE uses, not a scripted approximation.

This is a teaching tool: the goal is for the in-game behavior to actually match what you'd see on a real bench (RC charge curves, RL transients, a memristor's resistance drifting with accumulated charge), just at Minecraft-tick timescales instead of real-world ones.

[paper] 12nm FinFETs from 292K to 10mK

D. Lee, J. Lee, L. Jin, R. Rangaraj, L. Shao and J. S. Walling

12nm FinFETs from 292K to 10mK:

Characterization and a Temperature-Continuous Compact Model for Qubit Control

Preprint arXiv:2609.11963 (19 Aug 2026)

1 Bradley Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, VA, USA

Abstract: We report cryogenic characterization and compact modeling of GlobalFoundries (GF) 12LP regular-voltagethreshold (RVT) n- and p-FinFETs, measured from 292K to 10mK. Both devices retain sub-Kelvin gate control without carrier freeze-out, with the n-type device exhibiting an intrinsic subthreshold slope (SS) floor of 24.8 mV/dec. To bypass high on-chip series routing resistance that confounds peak-gm extraction, we adopt a fixed-current (3.26 μA/μm) methodology. These low current metrics inform a continuous 1.36K to 292K compact model using dynamic parameter injection, preserving room temperature process development kit (PDK) qualification.

Fig: Measured transfer characteristics at |VDS,ext| = 0.8V, shaded dark to light with increasing temperature. Drain current is normalized to gate width, so the dotted line marks the constant-current threshold criterion at ICC = 1μA/μm.

Acknowledgment: The 12nm finFET IC fabrication was provided by GlobalFoundries as part of their University Partnership Program.

[conf] International Conference on Microelectronics

ICM 2026 International Conference on Microelectronics

<https://www.ieee-icm.org/>

7-10 December 2026

Borneo Cultures Museum, Sarawak, Malaysia

The IEEE International Conference on Microelectronics has already been held numerous times in different countries across the MiddleEast, North Africa, and Asia for the past 37 years.

The 38th edition of the conference will take place in Borneo Cultures Museum Sarawak, Malaysia. IEEE-ICM 2026 will include oral, poster sessions and tutorials given by experts on state-of-the-art topics. The regular technical program will run for three days. In addition, tutorial sessions will be held on the first day of the conference.

The theme of ICM 2026, “Innovations in Circuits and Systems for a Sustainable Future,” has been selected in recognition of the unprecedented global challenges related to climate change, healthcare, and energy. Continued innovation and the development of new technological solutions are considered essential for building a more sustainable future. The conference is intended to provide a unique platform for the exchange of ideas and the exploration of new avenues for research and collaboration that may contribute to this objective.

Sincere appreciation is expressed to the keynote speakers, session chairs, reviewers, and volunteers, whose dedicated efforts have contributed significantly to the organization and success of the conference. Gratitude is also extended to the sponsors and exhibitors for their generous support, which has made the event possible.

It is hoped that the conference will be both informative and enjoyable, offering numerous opportunities for networking, learning, and collaboration. On behalf of the organizing committee, best wishes are conveyed for a productive and rewarding experience at ICM 2026.

[read more...]

[webinar] SPICE Device Modeling and Circuit Simulation

Mansun Chan

Circuit Simulation and Device Modeling: From SPICE Fundamentals to Industrial BSIM Models

DOI 10.17023/9439-t168

This tutorial introduces the fundamentals of circuit simulation and compact device modelling for integrated circuit design. Starting from SPICE-based circuit simulation #it explains the role of device models #the requirements for DC #transient #and AC analyses #and the trade-offs between physical accuracy and simulation efficiency. The development of industrial compact models is illustrated using BSIM3 as an example #providing insight into how practical device models are constructed and used in modern circuit design [EDS Education Committee]

More EDS Education Resources like this:

SPICE Models: Problems and Opportunities

Compact Modeling of MOSFETs: Overview and Challenges

#simulation #modeling #circuit #SPICE #bsim #mosfet #transistor #compact #tcad #jacobian #conductance #voltage