[paper] Self-Heating Effects in 55-nm SiGe HBTs

Abdelaaziz Boulgheb1, Billel Smaani2, Taha Housseyn Nouibat1

Physics-Based Electro-Thermal Modeling and Analysis 

of Self-Heating Effects in 55-nm SiGe HBTs

physica status solidi (a), 2026; 223:e70563 

https://doi.org/10.1002/pssa.70563

1. USTHB, Bab Ezzouar, Algeria 

2. University of Mila, Mila, Algeria

Abstract: This work investigates spatially resolved electrothermal behavior in scaled SiGe HBTs under self-heating conditions, emphasizing its impact on temperature distribution and RF performance. Unlike conventional lumped thermal resistance approaches assum- ing uniform temperature rise, the present analysis resolves the internal temperature field to capture nonuniform heat propagation effects. A physics-based electrothermal framework combining drift–diffusion transport, temperature-dependent semiconductor properties, and heat conduction equations is used to study hotspot formation and thermal confinement in a 55 nm SiGe HBT structure. Three operating conditions are considered: nominal operation at 300 K, self-heating at 300 K ambient temperature, and elevated ambient temperature of 320 K. The results reveal localized hotspot formation near the base–collector junction due to current crowding and geometrical confinement, leading to RF performance degradation. The cutoff frequency decreases from 320 to 285 GHz, while the maximum oscillation frequency reduces from 486 to 458.5 GHz. The current gain decreases from 2000 to 1500, and the maximum junction temperature reaches 417 K under the highest thermal stress condition. These findings highlight the importance of spatial thermal effects in governing RF limitations of SiGe HBTs and provide insight into the coupling between heat propagation and electrical performance in BiCMOS technologies.

FIG: Device structure of 55 nm SiGe HBT simulated with multiphysics TCAD: (a) log of electron and hole concentration highlighting emitter/base/SIC pedestal (b) TEM cross section of a fabricated BiCMOS 55nm HBT. Impact of self-heating on high-frequency performance of the 55-nm SiGe HBT under three thermal conditions: (c) parasitic delay parasitic (d) forward transit time τF , (e) cutoff frequency fT, and (f) maximum oscillation frequency fmax.

[paper] BSIM4 CryoModel-4K

Mohammed Saleh Alshaikh

CryoModel-4K: physics-based BSIM4 extension for28 nm bulk CMOS compact modeling at 4K

Nature Scientific Reports (Article in Press) DOI: 10.1038/s41598-026-69962-w

* Device Simulation Laboratory, Department of Electrical Engineering, College of Engineering and Architecture, Umm Al-Qura University, Makkah (SA)

Abstract: Accurate compact transistor models for 28nm bulk CMOS at cryogenic temperatures are essential for reli-able quantum computing interface circuit design. Existing room-temperature BSIM4 models fail to capture carrier mobility freeze-out, subthreshold swing saturation, current kink effects, and threshold voltage shifts at 4K. These failures produce post-fabrication performance deviations exceeding 300% in cryo-CMOS circuits designed using room-temperature models. This paper presents CryoModel-4K, a physics-based compact model that extends BSIM4 to accurately capture 28nm bulk CMOS behavior from 300 to 4K through three integrated correction modules. The Phonon Freeze-Out Mobility Enhancement Module (PFMEM) models the 3 to 8× car-rier mobility enhancement at liquid helium temperatures through a Matthiessen’s-rule combination of phonon, impurity, and surface roughness scattering. It is validated against published 4 K Hall effect measurements. The Cryogenic Subthreshold Swing Saturation Model (CSSM) replaces the classical kT/q thermal voltage with aband-tail tunneling-corrected expression. It accurately reproduces the observed 15 to 25 mV/dec subthreshold swing plateau below 30K. The Impurity Band Transport Kink Model (IBTK) captures the characteristic drain current kink arising from impact ionization triggered floating body effects in the partially frozen bulk substrate. Validation against published wafer-level characterization data for TSMC 28 nm bulk CMOS spanning 300 to 4K across 380 devices on three wafer splits demonstrates less than 5% RMS prediction error for all DC char-acteristics and less than 8% for RF S-parameters up to 10 GHz. Ring oscillator frequency is predicted within6.2% of measured values at 4K, compared to 312.5% error for standard BSIM4. The total SPICE simulation overhead relative to standard BSIM4 is approximately 25%.

FIG: a) Fig. 5 Complete small-signal equivalent circuit of CryoModel-4K for RF simulation, showing the intrinsic MOSFET withPFMEM-modified transconductance, CSSM-corrected output conductance, IBTK kink current source, temperature-depen-dent gate and substrate resistances, and parasitic interconnect elements. Small-signal equivalent circuit valid for operation from 100 MHz to 10 GHz at temperatures from 300 to 4 K. All substrate network elements are temperature-dependent 

b) Output characteristics (𝐼𝐷𝑉D) of a 28 nm NMOS device at 4 K for multiple 𝑉𝐺 values: measured data (symbols) ,CryoModel-4K with IBTK (solid lines), and BSIM4 without kink correction (dashed lines). Device: NMOS Lg = 28 nm, W =  um at T = 4K. VGS stepped from Vth to Vth + 0.5V in 0.1V increments. VDS swept from 0 V to 1.0 V in 25 mV steps. The IBTK captures the characteristic current kink at 𝑉𝐷≈0.5–0.7V

Acknowledgements: The author extends his sincere gratitude to the Umm Al-Qura University, for the invaluable resources and sup-portive environment that made this research possible.

Open Access: This article is licensed under a Creative Commons Attribution 4.0 International License

APCI Program: SBMicro Projects

APCI Program

Support for SBMicro Integrated Circuit Projects

TAB: Universities Involved in IC Design and EDA/CAD Tool Development

University	#Profs	#PhDs	#MSCs
CEFET-MG - Centro Federal de Educação Tecnológica de Minas Gerais	8	0	3
CEFET-RJ - Federal Center for Technological Education Celso Suckow da Fonseca	2	1	0
FEI - Centro Universitário da FEI	2	0	3
FURG - Universidade Federal do Rio Grande	3	1	1
IFSP - Instituto Federal de São Paulo	5	0	0
ITA - Instituto Tecnológico de Aeronáutica	10	0	5
PUCRS - Pontifícia Universidade Católica do Rio Grande Do Sul	8	15	9
UCPEL - Universidade Católica de Pelotas	3	0	6
UEA - Universidade do Estado do Amazonas	1	0	0
UERGS - State University of Rio Grande do Sul	5	0	0
UFABC - Federal University of ABC	6	0	2
UFAM - Universidade Federal de Manaus	4	4	0
UFBA - Universidade Federal da Bahia	5	13	8
UFC - Universidade Federal do Ceará	3	5	3
UFERSA - Mossoró	1	0	4
UFERSA - Pau dos Ferros	5	1	3
UFG - Federal University of Goiás	8	1	0
UFMG - Universidade Federal de Minas Gerais	6	3	9
UFPB - Universidade Federal da Paraíba	1	1	2
UFPEL - Universidade Federal de Pelotas	13	13	2
UFPR - Universidade Federal do Paraná	7	2	5
UFRGS - Universidade Federal do Rio Grande do Sul	17	32	45
UFRJ - Federal University of Rio de Janeiro	6	2	4
UFRN - Federal University of Rio Grande do Norte	4	3	2
UFS - Universidade Federal do Sergipe	3	0	1
UFSC - Universidade Federal de Santa Catarina	11	12	11
UFSM - Universidade Federal de Santa Maria	8	0	5
UFV - Universidade Federal de Viçosa	2	3	3
UNB - Universidade de Brasília	9	3	9
UNESP - Universidade Estadual Paulista	4	0	1
UNICAMP - Universidade Estadual de Campinas	8	16	21
UNIFEI - Universidade Federal de Itajubá	7	2	3
UNIFEI - Itabira	3	0	3
UNIPAMPA - Universidade Federal do Pampa	4	0	2
UNISANTOS - Universidade Católica de Santos	1	0	0
UNISINOS - Universidade do Vale do Rio dos Sinos	3	0	3
UNIVALI - Universidade do Vale do Itajaí	3	0	3
USP - Universidade de São Paulo	8	1	12
USP-EESC - Escola de Engenharia de São Carlos	3	1	2
UTFPR - Universidade Tecnológica Federal do Paraná	1	0	0

[REF] Report: Strengthening EU-Brazil bilateral know-how of semiconductor sector technologyand possibilities for cooperation on trade and R&D (July 2023)

[OpenSUSI] First Tyepout

J. I. Okamura

New Semiconductor Design Programs with Japan’s Open Source Ecosystem

[Society News] in IEEE Solid-State Circuits Magazine, vol. 18, no. 3, pp. 87-88, Summer 2026, 

doi: 10.1109/MSSC.2026.3708432

Abstract: Open Source Utilized Silicon Initiatives (OpenSUSI), founded in April 2024 as a nonprofit organization, has been working closely with two Japanese legacy foundries to foster an open source silicon ecosystem in Japan. On 19 September 2025, TOKAI RIKA Co., Ltd., a 6-inch legacy foundry in Japan, announced the release of a non-disclosure-free process design kit (PDK) as an open source platform [1]. This new open source PDK, called TR-1um [2], was released via the OpenSUSI GitHub repository, and, since last October, we have been cleaning up and maintaining it alongside our collaborators.

Fig. First Tapeout application form on the OpenSUSI homepage.

[OpenPDK] GT2N

This the initial release for the GT2N PDK with 72 standard cells: <https://github.com/azadnaeemi/GT2N>.

It is based on 2nm GAAFET with BSPDN. All the device models are based on 3-stack nanosheets

Standard cell layouts can also be imported using the .gds file: GT2N/gds/gt2_6t_std_cells.gdsLVS and DRC rulesets for icvalidator are present in "GT2N/icv_runset".
Libraries are composed of 3 process corners (under development), 2 nanosheet width (W) flavors, and 5 threshold voltage (VT) flavors. (In the order of decreasing VT, HVT > SVT > LVT > ULVT > ELVT)

The collaterals required for synthesis and PnR are (depending on the process corner and W/VT flavor):

LIB: GT2N/lib/tt/gt2_6t_w31_lvt_tt_0p7v25c.lib
LEF: GT2N/lef/tt/gt2_6t_w31_lvt.lef
Techlef: GT2N/techlib/gt2_tech.lef
ICT: GT2N/qrc/GT2.ict
QRCTech: GT2N/qrc/GT2_qrc.tch
ITF: GT2N/nxtgrd/GT2.itf
NXTGRD: GT2N/nxtgrd/GT2.nxtgrd

The thermal-calibrated GAAFET (3-stack nanosheet) model card is (depending on the process corner and W/VT flavor):

GT2N/device/tt/gt2_w31_lvt_tt.sp

[ref] D. Jang, P. Kumar, M. N. H. Shazon, S. J. Ram, A. Svizhenko, V. Moroz, A. Ceyhan, N. A. Radhakrishn, and A. Naeemi, "GT2N: An Open-Source 2nm Nanosheet PDK Enabling Multi-Width/VT Benchmarking" in IEEE International Symposium on Circuits and Systems (ISCAS) 2026