Oct 12, 2026

[paper] BSIM4 CryoModel-4K

Mohammed Saleh Alshaikh
CryoModel-4K: physics-based BSIM4 extension for28 nm bulk CMOS compact modeling at 4K
Nature Scientific Reports (Article in Press) DOI: 10.1038/s41598-026-69962-w

* Device Simulation Laboratory, Department of Electrical Engineering, College of Engineering and Architecture, Umm Al-Qura University, Makkah (SA)

Abstract: Accurate compact transistor models for 28nm bulk CMOS at cryogenic temperatures are essential for reli-able quantum computing interface circuit design. Existing room-temperature BSIM4 models fail to capture carrier mobility freeze-out, subthreshold swing saturation, current kink effects, and threshold voltage shifts at 4K. These failures produce post-fabrication performance deviations exceeding 300% in cryo-CMOS circuits designed using room-temperature models. This paper presents CryoModel-4K, a physics-based compact model that extends BSIM4 to accurately capture 28nm bulk CMOS behavior from 300 to 4K through three integrated correction modules. The Phonon Freeze-Out Mobility Enhancement Module (PFMEM) models the 3 to 8× car-rier mobility enhancement at liquid helium temperatures through a Matthiessen’s-rule combination of phonon, impurity, and surface roughness scattering. It is validated against published 4 K Hall effect measurements. The Cryogenic Subthreshold Swing Saturation Model (CSSM) replaces the classical kT/q thermal voltage with aband-tail tunneling-corrected expression. It accurately reproduces the observed 15 to 25 mV/dec subthreshold swing plateau below 30K. The Impurity Band Transport Kink Model (IBTK) captures the characteristic drain current kink arising from impact ionization triggered floating body effects in the partially frozen bulk substrate. Validation against published wafer-level characterization data for TSMC 28 nm bulk CMOS spanning 300 to 4K across 380 devices on three wafer splits demonstrates less than 5% RMS prediction error for all DC char-acteristics and less than 8% for RF S-parameters up to 10 GHz. Ring oscillator frequency is predicted within6.2% of measured values at 4K, compared to 312.5% error for standard BSIM4. The total SPICE simulation overhead relative to standard BSIM4 is approximately 25%.

FIG: a) Fig. 5 Complete small-signal equivalent circuit of CryoModel-4K for RF simulation, showing the intrinsic MOSFET withPFMEM-modified transconductance, CSSM-corrected output conductance, IBTK kink current source, temperature-depen-dent gate and substrate resistances, and parasitic interconnect elements. Small-signal equivalent circuit valid for operation from 100 MHz to 10 GHz at temperatures from 300 to 4 K. All substrate network elements are temperature-dependent 
b) Output characteristics (𝐼𝐷𝑉D) of a 28 nm NMOS device at 4 K for multiple 𝑉𝐺 values: measured data (symbols) ,CryoModel-4K with IBTK (solid lines), and BSIM4 without kink correction (dashed lines). Device: NMOS Lg = 28 nm, W =  um at T = 4K. VGS stepped from Vth to Vth + 0.5V in 0.1V increments. VDS swept from 0 V to 1.0 V in 25 mV steps. The IBTK captures the characteristic current kink at 𝑉𝐷≈0.5–0.7V

Acknowledgements: The author extends his sincere gratitude to the Umm Al-Qura University, for the invaluable resources and sup-portive environment that made this research possible.

Open Access: This article is licensed under a Creative Commons Attribution 4.0 International License

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TAB: Universities Involved in IC Design and EDA/CAD Tool Development

University # Profs # PhD Students # MSc Students
CEFET-MG - Centro Federal de Educação Tecnológica de Minas Gerais803
CEFET-RJ - Federal Center for Technological Education Celso Suckow da Fonseca210
FEI - Centro Universitário da FEI203
FURG - Universidade Federal do Rio Grande311
IFSP - Instituto Federal de São Paulo500
ITA - Instituto Tecnológico de Aeronáutica1005
PUCRS - Pontifícia Universidade Católica do Rio Grande Do Sul8159
UCPEL - Universidade Católica de Pelotas306
UEA - Universidade do Estado do Amazonas100
UERGS - State University of Rio Grande do Sul500
UFABC - Federal University of ABC602
UFAM - Universidade Federal de Manaus440
UFBA - Universidade Federal da Bahia5138
UFC - Universidade Federal do Ceará353
UFERSA - Mossoró104
UFERSA - Pau dos Ferros513
UFG - Federal University of Goiás810
UFMG - Universidade Federal de Minas Gerais639
UFPB - Universidade Federal da Paraíba112
UFPEL - Universidade Federal de Pelotas13132
UFPR - Universidade Federal do Paraná725
UFRGS - Universidade Federal do Rio Grande do Sul173245
UFRJ - Federal University of Rio de Janeiro624
UFRN - Federal University of Rio Grande do Norte432
UFS - Universidade Federal do Sergipe301
UFSC - Universidade Federal de Santa Catarina111211
UFSM - Universidade Federal de Santa Maria805
UFV - Universidade Federal de Viçosa233
UNB - Universidade de Brasília939
UNESP - Universidade Estadual Paulista401
UNICAMP - Universidade Estadual de Campinas81621
UNIFEI - Universidade Federal de Itajubá723
UNIFEI - Itabira303
UNIPAMPA - Universidade Federal do Pampa402
UNISANTOS - Universidade Católica de Santos100
UNISINOS - Universidade do Vale do Rio dos Sinos303
UNIVALI - Universidade do Vale do Itajaí303
USP - Universidade de São Paulo8112
USP-EESC - Escola de Engenharia de São Carlos312
UTFPR - Universidade Tecnológica Federal do Paraná100

Oct 11, 2026

[OpenSUSI] First Tyepout

J. I. Okamura
New Semiconductor Design Programs with Japan’s Open Source Ecosystem
[Society News] in IEEE Solid-State Circuits Magazine, vol. 18, no. 3, pp. 87-88, Summer 2026, 
doi: 10.1109/MSSC.2026.3708432

Abstract: Open Source Utilized Silicon Initiatives (OpenSUSI), founded in April 2024 as a nonprofit organization, has been working closely with two Japanese legacy foundries to foster an open source silicon ecosystem in Japan. On 19 September 2025, TOKAI RIKA Co., Ltd., a 6-inch legacy foundry in Japan, announced the release of a non-disclosure-free process design kit (PDK) as an open source platform [1]. This new open source PDK, called TR-1um [2], was released via the OpenSUSI GitHub repository, and, since last October, we have been cleaning up and maintaining it alongside our collaborators.


Fig. First Tapeout application form on the OpenSUSI homepage.


Oct 10, 2026

[OpenPDK] GT2N

This the initial release for the GT2N PDK with 72 standard cells: <https://github.com/azadnaeemi/GT2N>.
It is based on 2nm GAAFET with BSPDN. All the device models are based on 3-stack nanosheets


Standard cell layouts can also be imported using the .gds file: GT2N/gds/gt2_6t_std_cells.gdsLVS and DRC rulesets for icvalidator are present in "GT2N/icv_runset".
Libraries are composed of 3 process corners (under development), 2 nanosheet width (W) flavors, and 5 threshold voltage (VT) flavors. (In the order of decreasing VT, HVT > SVT > LVT > ULVT > ELVT)

The collaterals required for synthesis and PnR are (depending on the process corner and W/VT flavor):
LIB: GT2N/lib/tt/gt2_6t_w31_lvt_tt_0p7v25c.lib
LEF: GT2N/lef/tt/gt2_6t_w31_lvt.lef
Techlef: GT2N/techlib/gt2_tech.lef
ICT: GT2N/qrc/GT2.ict
QRCTech: GT2N/qrc/GT2_qrc.tch
ITF: GT2N/nxtgrd/GT2.itf
NXTGRD: GT2N/nxtgrd/GT2.nxtgrd

The thermal-calibrated GAAFET (3-stack nanosheet) model card is (depending on the process corner and W/VT flavor):
GT2N/device/tt/gt2_w31_lvt_tt.sp

[ref] D. Jang, P. Kumar, M. N. H. Shazon, S. J. Ram, A. Svizhenko, V. Moroz, A. Ceyhan, N. A. Radhakrishn, and A. Naeemi, "GT2N: An Open-Source 2nm Nanosheet PDK Enabling Multi-Width/VT Benchmarking" in IEEE International Symposium on Circuits and Systems (ISCAS) 2026  








Oct 9, 2026

[ICTA2026 ] Special OpenPDK Session

IEEE International Conference on Integrated Circuits, Technologies & Applications
ICTA 2026 Special Session “OpenPDK - Global FOSS Scholar Platform"
21st - 24th (Wed - Sat) October 2026
Grand Copthorne Waterfront Hotel, Singapore


The OpenPDK initiative delivers a global FOSS Scholar Platform supporting analog/RF, mixed‑signal, and digital IC design. Central to this effort are accurate SPICE models for low‑power sensing MOSFETs, RF HBTs, and emerging RRAM devices, validated across cryogenic temperatures for space and quantum‑computing applications. The initiative also advances Verilog‑A compact‑model standardization, ensuring result reproducibility and seamless integration into open‑source design flows. Supported by the EU Chips JU, OpenPDK fosters collaboration among academia, startups, and industry, while providing FOSS IC‑design tools covering schematic capture, simulation, layout, and verification up to tape‑out. Similar to the EU Chips JU program, Zhejiang CoreXin in China offers an open‑source PDK together with tape‑out services for its 55nm CMOS process. To accelerate the semiconductor‑industry development across the Asia‑Pacific and Southeast‑Asia regions, semiconductor model development and parameter extraction techniques should be pursued in a more focused manner. This special session brings together experts to present and discuss advances in device characterization, compact modeling, simulation methodologies, and validation techniques for a broad range of solid‑state devices, including Si, III/V semiconductors, power devices, nanoscale structures, and emerging 2.5D/3D advanced packaging technologies [ read more...]

ICTA 2026 Special OpenPDK Session Presenters
  • SPICE/Verilog-A standard models and OpenPDK practice
    Wladek Grabinski, GMC Consulting, Switzerland
  • Open-Source Ecosystem Updates and Semiconductor Design Development Programs in Japan
    Jun-ichi Okamura, AIST Solutions, OpenSUSI, Japan
  • Open-Source EDA Meets Industrial IC Design
    Ehrenfried Seebacher, ams-OSRAM AG, Austria
  • Building an Open-Source Process Platform, Empowering VLSI Innovation and Development
    Da Zhang, Zhejiang University/CTO, Zhejiang Chuangxin Integrated Process Platform, China
  • From Silicon to Design: Intelligent Measurement and Modeling for DTCO
    Yutao Ma, VP of R&D, Primarius Technologies. Ltd. China
  • Beyond Moore, Application-Driven IC Innovation International Cooperation Opportunities at NICE
    Alex Gu, National Innovation Center Par Excellence (NICE), China
  • 2.5D/3D IC: AI+EDA Reshaping the System-Design-Technology Co0ptimization (STCO) Paradigm for Advanced Packaging
    Alex Zhao, Founder/CEO Zhuhai SiChip Technology Co., Ltd., China
  • Modelling of semiconductor devices: the heart of innovation bridging academia and industrial applications
    Fujiang Lin, University of Science and Technology of China (USTC), China
Special OpenPDK Session progeam include the panel discussion: 
How to have a close loop for PDK, EDA, PDA and ICS simulation?