[ICTA2026 ] Special OpenPDK Session

IEEE International Conference on Integrated Circuits, Technologies & Applications

ICTA 2026 Special Session “OpenPDK - Global FOSS Scholar Platform"

21st - 24th (Wed - Sat) October 2026

Grand Copthorne Waterfront Hotel, Singapore

The OpenPDK initiative delivers a global FOSS Scholar Platform supporting analog/RF, mixed‑signal, and digital IC design. Central to this effort are accurate SPICE models for low‑power sensing MOSFETs, RF HBTs, and emerging RRAM devices, validated across cryogenic temperatures for space and quantum‑computing applications. The initiative also advances Verilog‑A compact‑model standardization, ensuring result reproducibility and seamless integration into open‑source design flows. Supported by the EU Chips JU, OpenPDK fosters collaboration among academia, startups, and industry, while providing FOSS IC‑design tools covering schematic capture, simulation, layout, and verification up to tape‑out. Similar to the EU Chips JU program, Zhejiang CoreXin in China offers an open‑source PDK together with tape‑out services for its 55nm CMOS process. To accelerate the semiconductor‑industry development across the Asia‑Pacific and Southeast‑Asia regions, semiconductor model development and parameter extraction techniques should be pursued in a more focused manner. This special session brings together experts to present and discuss advances in device characterization, compact modeling, simulation methodologies, and validation techniques for a broad range of solid‑state devices, including Si, III/V semiconductors, power devices, nanoscale structures, and emerging 2.5D/3D advanced packaging technologies [ read more...]

ICTA 2026 Special OpenPDK Session Presenters

• SPICE/Verilog-A standard models and OpenPDK practice
  Wladek Grabinski, GMC Consulting, Switzerland
• Open-Source Ecosystem Updates and Semiconductor Design Development Programs in Japan
  Jun-ichi Okamura, AIST Solutions, OpenSUSI, Japan
• Open-Source EDA Meets Industrial IC Design
  Ehrenfried Seebacher, ams-OSRAM AG, Austria
• Building an Open-Source Process Platform, Empowering VLSI Innovation and Development
  Da Zhang, Zhejiang University/CTO, Zhejiang Chuangxin Integrated Process Platform, China
• From Silicon to Design: Intelligent Measurement and Modeling for DTCO
  Yutao Ma, VP of R&D, Primarius Technologies. Ltd. China
• Beyond Moore, Application-Driven IC Innovation International Cooperation Opportunities at NICE
  Alex Gu, National Innovation Center Par Excellence (NICE), China
• 2.5D/3D IC: AI+EDA Reshaping the System-Design-Technology Co0ptimization (STCO) Paradigm for Advanced Packaging
  Alex Zhao, Founder/CEO Zhuhai SiChip Technology Co., Ltd., China
• Modelling of semiconductor devices: the heart of innovation bridging academia and industrial applications
  Fujiang Lin, University of Science and Technology of China (USTC), China

Special OpenPDK Session progeam include the panel discussion: 

How to have a close loop for PDK, EDA, PDA and ICS simulation?

[ read more...]

[conference] ELECTRONICS 2026 at KTU Kaunas

International Conference ELECTRONICS 2026

From SMT to Advanced Packaging – Manufacturing Meets Microinterconnects

KTU Kaunas, Lithuania

12–13 November 2026

Conference Vision : A joint platform connecting SMT engineers, advanced packaging researchers, reliability specialists, and industry to build a shared technical language, bridge research and manufacturing, and grow German-Baltic collaboration around heterogeneous integration and microinterconnects. Organized by Kaunas University of Technology, the conference serves as a platform for collaboration and discussion among representatives from academy, industry, and business.

Partners:
TUD IAFT (Dresden University of Technology, Institute of Electronic Packaging Technology)
IHP (IHP GmbH, Leibniz Institute for High Performance Microelectronics)
Industry Partners: FINETECH, TELTONIKA, etc.

Conference Program Online <https://eef.ktu.edu/events/electronics2026/>

Conference Organzation Committee:

General Chair

Prof., Dr. Mindaugas ŽILYS, KTU Kaunas

Executive Chair

Dr. Agata ROMANOVA, KTU Kaunas

Co-Chairs

Prof., Dr. Algimantas VALINEVIČIUS, KTU Kaunas

Prof., Dr. Darius ANDRIUKAITIS, KTU Kaunas

Prof., Dr. Dangirutis NAVIKAS, KTU Kaunas

Schematic to Silicon with Mini MOSbius

Zero To ASIC Course and Tiny Tapeout by Matt Venn

Schematic to Silicon with Mini MOSbius 

https://www.youtube.com/watch?v=NM5cLWYWqG0

Take Matt Venn TT course: 

https://www.zerotoasiccourse.com/

Buy a copy of Mini MOSbius, part of the TT IP library, here: 

https://store.tinytapeout.com/products/TTSKY25b-Development-Kit-p849160072

Check the configurator: 

https://github.com/mattvenn/mini-mosbius-configurator

Mini MOSbius is available on these chips

• [OK] TTSKY25a - delivered July 2026 - available in the store
• [OK] TTSKY25b - delivered August 2026 - available in the store
• TTSKY26b - tapeout May 2026
• TTSKY26c - tapeout September 2026
• GF180 - will be taped out December 2026

and finally check out the original MOSBius: https://mosbius.org/ If you are interested to acquire MOSbius kits, review the express license and email Peter Kinget for kit availability before placing an order.

[poster] Active Cantilever with Dual Actuator

Bartosz Pruchnik1, Fabian Dietrich2, Richard Subianto2, Katerina Ivanova2, Athulya K. Muraleedharan Bindu2, Hans-Georg Pietscher2, Javad Basseri2, Muralikrishnan Brajesh Kaimal2, Władysław Kopczyński1, Wojciech Godlewski1, Dominik Badura1, Piotr Putek1, Krzysztof Kwoka1, Piotr Smagowski1, Andrew Yacoot3, Tomasz Piasecki1, Fangzhou Xia4, Ivo W. Rangelow2 

Active Cantilever with Dual Actuator

52nd International Micro and Nano Engineering Conference

Sep. 21-24, 2026 Interlaken (CH)

MEN2026 Poster S05A-T2-P-5

1. Wrocław University of Science and Technology,

2. nano analytik GmbH, 

3. National Physical Laboratory

4. University of Texas at Austin

Abstract: Atomic Force Microscopy (AFM) is often limited by the speed and bandwidth of three main components: the cantilever, the scanner, and the controller. Recent microelectromechanical systems (MEMS) have improved the performance of the cantilever and scanner by combining high-speed active cantilevers with low-latency scanners. In this work, we present a standardized active cantilever design. The system combines a large cantilever that acts as a Z-axis actuator with a smaller active cantilever sensor that provides a bandwidth greater than 400kHz. The smaller cantilever is integrated into the larger structure, creating a compact and highly responsive device. We introduce a new active cantilever architecture that uses two integrated electrothermal actuators. One actuator is used for cantilever operation, while the second provides vertical (Z-axis) movement for surface tracking. This design allows AFM measurements to be performed without the need for an external piezoelectric z-actuator.

Acknowledgements: This work was supported by the European Union's Horizon Europe research and innovation program under the Marie Sklodowska-Curie grant agreement No 101072775, and by the National Science Centre, Poland (grant No. 2021/41/B/ST7/03144).

[paper] Open Source EZ130 8T standard cell library

Oscar Castaneda, Lavinia Recchioni, Tobias Senti, Flurin Cahenzli, Marco Ferroni, Thorben Heekenjann, Robert Kenter, Stefan Odermatt, Daniel Richner, Gabriel Altendorfer, Davide Cannone, Miguel Correa, Ivan Herger, Lars Kroger, Nicolas Nanzer, Darja Nonaca, Christopher Reinwardt, Lukas Winklhofer, Enrico Zelioli, Yiheng Zhang, Yingxue Zhang, Domenic Keller, Seyed Hadi Mirfarshbafan, Zerun Jiang, Beat Muheim, Arianna Rubino, Jeremy Guichemerre, Frank K. Gurkaynak, and Christoph Studer

An Open-Source Standard-Cell Library for IHP 130 nm Developed by Students

arXiv:2609.29965v1 [cs.AR] 24 Sep 2026

1. Department of Information Technology and Electrical Engineering, ETH Zurich, Switzerland

* The open-source EZ130 8T standard-cell library is available at https://ez.ethz.ch

Abstract: Standard-cell libraries form the critical interface between transistor-level circuit design and automated digital design flows, yet their design and characterization are rarely covered in depth in digital VLSI courses. This paper presents VLSI 5, a graduate-level course at ETH Zurich in which students design, lay out, characterize, and integrate their own standard cells using IHP’s open-source 130 nm SG13G2 process design kit. In the first course offering, 19 students developed EZ130 8T, an open-source eight-track standard-cell library comprising 220 cells. We evaluate successive library versions using eight synthesis benchmarks, across which EZ130 8T achieves significant area reduction compared to the SG13G2 library at competitive timing. For a postlayout 8×8 matrix-vector multiplier, EZ130 8T reduces cell area by 35% and energy by 39% while maintaining virtually the same clock period. The library has already been adopted in other ETH Zurich VLSI courses, enabling the creation of chips entirely designed by students down to the transistor level.

FIG: a.) ETH Zurich course series on digital VLSI design. By teaching students to create a standard-cell library, the new VLSI 5 course closes the gap between transistor-level and HDL-level IC design;
b.) and c.) Layout of two example standard cells from the EZ130 8T library.

Aknowlegements: This work has received funding from the Swiss State Secretariat for Education, Research, and Innovation (SERI) under the SwissChips initiative. The authors thank Cadence for their support by providing licenses to design and characterize the EZ library. The authors also thank H. Pretl, T. Benz, and P. Sauter for their feedback on preliminary versions of the EZ library.