[seminar] OpenPDK - Global Scholar Platform

Radiofrequency, Microwave and Millimetre-Wave Lab (mmiRF)

ETSI Telecomunicación,  Universidad de Málaga, Andalusia

Wednesday, May 27th, at 12:00

The mmiRF Lab is pleased to invite you to our upcoming hybrid seminar, which will be available both in person and online:

• OpenPDK - Global Scholar Platform
• Wednesday, May 27th, at 12:00
• mmiRF Lab, ETSI Telecomunicación, Universidad de Málaga
• Join the meeting online (MS Teams)

The semiconductor industry is evolving. The emergence of OpenPDKs is creating a new platform for global collaboration and education. The seminar will explore:

• The role of FOSS CAD/EDA tools in building a global talent ecosystem.
• OpenPDK initiatives from SkyWater, GF, and IHP (the first in Europe).
• Complete open IC design flows: Xschem, ngspice, Xyce, Magic, kLayout, and more.
• Hands-on examples of analog, RF, and digital IC design

Don't miss this chance to learn from a leading expert in the field and explore the tools shaping the future of microelectronics! 

#mmiRF #OpenPDK #Semiconductors #ICDesign #FOSS #EDA #Microelectronics #Innovation #UMA #STEM #MOS-AK

Speaker Bio: Wladek Grabinski received his Ph.D. from the ITE Warsaw, in 1991. He worked at ETHZ on CMOS/BiCMOS characterization and at EPFL on compact EKV model development, later serving as a technical staff engineer at Motorola/FSL in Geneva. He is now a consultant specializing in OpenPDK, coordinating SPICE modeling, device characterization, and parameter extraction for analog/RF IC design, with particular interests in high-frequency measurement, compact modeling and its Verilog-A standardization. He co-edited the book Transistor Level Modeling for Analog/RF IC Design, contributed to the Compact/SPICE Modeling Chapter of the Springer Handbook of Semiconductor Devices, and authored 70+ papers. Furthermore, he also contributes to IEEE EDS, LAEDC, ESSDERC, and MIXDES and manages the MOS-AK association since 1999.

Seeing Transistor Scaling Up Close

 And What “tiny” Really Means - Comparing Modern Chips to the Machines of Life

BEHIND THE CHIP: Apr 17, 2026

<https://behindthechip.substack.com/p/seeing-transistor-scaling-up-close>

[repost] Modern transistors have gate lengths of around 8 nm. To put that in perspective: a red blood cell is 10,000 nm wide. A DNA strand is just 2 nm, and a transistor is sitting right between those two scales. We are literally engineering at the edge of atomic limits, silicon atoms themselves are only 0.2 nm wide.

That foundational brick of modern electronics keeps shrinking year after year, driven by companies like TSMC, Intel, Samsung, and ASML pushing the boundaries of what is physically possible.

Billions of these switches/transistors, smaller than a virus, packed into a chip you can hold between two fingers. That is what powers every microcontroller, every processor, every smart device you touch today.

Revolution EDA Mistral AI Experiments

Revolution EDA MistralAI Experiments

by Murat Eskiyerli  

There was a recent article by Prof Razavi, where the problems of Large Language Models in identifying various analogue integrated circuit blocks were recounted.

Revolution EDA uses structured JSON data format to store design files. JSON also happens to be very easy for LLMs to parse and understand. In fact, Mistral AI has a JSON mode. Mistral AI is the latest addition to the growing number of LLMs that Revolution EDA is able to use.

We did ask a few questions to Mistral AI to test its understanding of designs in Revolution EDA and its potential to help designers. The results have been very encouraging. The future analogue integrated circuit designers will be able to use large language models like Mistral AI to quickly gain understanding of a circuit and improve on it.

The transcription below is taken exactly from the interaction with Mistral AI except for small formatting changes [read more...]

2nd Semiconductor Device Frontier Summit

Date: May 18, 2026; Time: 10:00AM ~ 05:00PM

Ewha Womans University Student Culture Center (Small Theater B101)

The Semiconductor Device Research Group of the Society of Semiconductor Engineers has been holding this event since 2025 to strengthen human networks among domestic researchers and share the latest research trends.

This year's summit, now in its second year, invited top-notch speakers from various fields to provide a broad view of the latest technologies in industry and academia. It will be a place for meaningful academic exchanges to grasp the latest semiconductor technology trends as well as to share in-depth opinions on international market trends. This event is co-organized by the Society of Semiconductor Engineers and the IEEE EDS Seoul Section Chapter and aims to become an international event representing the semiconductor device field in Korea in the future. We ask for your interest and participation so that the 'Semiconductor Device Frontier Summit', which will be the core pillar of the Korean researcher network, can become the cornerstone of the development of our semiconductor industry.

Pre-registration deadline: Until May 16, 2026 (Saturday)

Time	Program
Opening Session
10:00 – 10:20	Welcome & Registration
10:20 – 10:30	Opening Remarks (Prof. Sung‑Jae Cho, Ewha Womans University)
Session 1 | Chair: Prof. Sung‑Jae Cho
10:30 – 11:15	Semiconductor Devices for the New Computing Era Prof. Woo‑Young Choi, Seoul National University
11:15 – 12:00	Development Strategy for AI‑Oriented NAND Solutions Prof. Ki‑Hwan Song, Yonsei University
12:00 – 13:30	Lunch
Session 2 | Chair: Prof. Myung‑Gon Kang
13:30 – 14:15	Trends and Outlook of eNVM Technology Visiting Prof. Yong‑Gyu Lee, Seoul National University
14:15 – 15:00	Memcapacitor Technology for Charge‑Domain PIM Implementation Prof. Tae‑Hyun Kim, Seoul National University of Science and Technology
15:00 – 15:10	Coffee Break
Session 3 | Chair: Prof. Il‑Hwan Cho
15:10 – 15:55	Atomically Thin 2D Semiconductor Electronics toward Beyond‑CMOS Technology Prof. Chul‑Ho Lee, Seoul National University
15:55 – 16:40	Orders‑of‑Magnitude Faster TCAD Device Simulation of GAA MOSFETs without Additional Computational Training Cost Prof. Sung‑Min Hong, GIST
16:40 – 17:00	Closing Ceremony | Prof. Il‑Hwan Cho, Myongji University

[chapter] Modeling of the MOSFETs

Jean-Marc Dienot, “A Review on Analytical and Electrical Modeling of the MOSFET Transistor”

Chapter 2 in "Field-Effect Transistors – Fundamentals, Technologies, and Future Applications"

Editor: Kenan Cicek

DOI: 10.5772/intechopen.1009040

ABSTRACT: Power semiconductor MOSFET and other MOS-controlled devices benefit from material and technology improvements to respond to high-level power features, high voltage, high current density, short switching times, and thermal constants, which optimize energy efficiency. These enhanced characteristics induce more electromagnetic noises and temperature-management constraints for the deployment of this technology. We describe synthetically modeling theory and technic, from basic-to-advanced, to derive predictive simulations for the power MOSFET challenging issues. Analytical and electrical circuit model of the MOSFET elementary cell at semiconductor level, time-domain simulation. Distributed and propagative model, including device packaging and power-printed circuit board (PPCB) PEEC and 3D model levels, signal integrity simulation, common mode emission simulation, and radiated field simulation. Electro-thermal model with thermal propagative network model coupled with electrical model at circuit level, time multi-domain simulation. Case studies on Power PCB with MOSFET Si et SiC illustrate modeling procedures.

FIG: Overeview of analytical equations of the MOSFETs