Mar 26, 2026

[github] NVC: VHDL compiler and simulator

 

https://cameron-eda.com/

NVC is a VHDL compiler and simulator

NVC supports almost all of VHDL-2008 with the exception of PSL, and it has been successfully used to simulate several real-world designs. Experimental support for Verilog and VHDL-2019 is under development. NVC has a particular emphasis on simulation performance and uses LLVM to compile VHDL to native machine code. NVC is not a synthesizer. That is, it does not output something that could be used to program an FPGA or ASIC. It implements only the simulation behaviour of the language as described by the IEEE 1076 standard. NVC supports popular verification frameworks including OSVVM, UVVM, VUnit and cocotb. See below for installation instructions.

Vendor Libraries
NVC provides scripts to compile popular verification frameworks and the simulation libraries of common FPGA vendors
  • For OSVVM use nvc --install osvvm
  • For UVVM use nvc --install uvvm
  • For Xilinx ISE use nvc --install ise
  • For Xilinx Vivado use nvc --install vivado and additionally nvc --install xpm_vhdl
    if you require simulation models of the XPM macros
  • For Altera Quartus use nvc --install quartus
  • For Lattice iCEcube2 use nvc --install icecube2
  • For Free Model Foundry common packages use nvc --install fmf


Mar 25, 2026

[Open Source Survey] From RTL to Fabrication

Emilio Isaac Baungarten-Leon
From RTL to Fabrication: Survey of Open-Source EDA Tools and PDKs
Electronics 2026, 15(5), 1048;
DOI: 10.3390/electronics15051048

* Departamento de Electromecánica, Universidad Autónoma de Guadalajara, Zapopan 45129, Mexico


Abstract: This article aims to synthesize the current ecosystem of open-source tools for Integrated Circuit (IC) design, covering the entire digital design flow from Register-Transfer Level (RTL) description to fabricable layouts. The survey categorizes and analyzes tools across major stages of design, including code-generation tools, logic synthesis, simulation, and physical design flow. Special emphasis is given to the fabricable open-source Process Design Kit (PDK), which enables the physical realization of open-hardware projects. By examining interoperability, limitations, and maturity across this toolchain, the article provides a comprehensive overview of the Electronic Design Automation (EDA) landscape and identifies the research and educational opportunities that arise from democratizing silicon design through open and reproducible workflows.
Fig: (a) IC design flow illustrating the complete process from RTL specification through logic synthesis, physical design (floorplanning, placement, clock tree synthesis, routing), verification, and final GDSII generation for fabrication. (b) FPGA design flow showing the progression from RTL description to synthesis, technology mapping, placement-and-routing on the target FPGA fabric, bitstream generation, and device configuration.

Acknowledgments: The APC was funded by Universidad Autónoma de Guadalajara (UAG), financial support provided through its Fondo Semilla. The author gratefully acknowledges the Universidad Autónoma de Guadalajara (UAG) for the financial support provided through its Fondo Semilla program, which covered the article processing charges and enabled the publication of this work. During the preparation of this manuscript, the authors utilized GPT-5.2 solely to enhance the clarity, grammar, and overall quality of the English text. The author reviewed and edited all AI-assisted content and takes full responsibility for the accuracy, originality, and integrity of the final manuscript.

Table A1. Main open-source EDA tools and their official repositories
Category Tool Official Link
Code-Generation ToolsPandA Bambu HLShttps://github.com/ferrandi/PandA-bambu (accessed on 20 January 2026)
Kiwi Compilerhttps://www.cl.cam.ac.uk/~djg11/kiwi/ (accessed on 20 January 2026)
LegUp HLShttps://github.com/LegUpComputing/legup-examples?tab=readme-ov-file (accessed on 20 January 2026)
ROCCChttp://roccc.cs.ucr.edu/ (accessed on 20 January 2026)
PyMTL3https://github.com/pymtl/pymtl3 (accessed on 20 January 2026)
Chiselhttps://www.chisel-lang.org/ (accessed on 20 January 2026)
SpinalHDLhttps://github.com/SpinalHDL/SpinalHDL (accessed on 20 January 2026)
Pyveriloghttps://github.com/PyHDI/Pyverilog (accessed on 20 January 2026)
Amaranth HDLhttps://github.com/amaranth-lang (accessed on 20 January 2026)
LLM-Based Code GenerationRTLCoderhttps://github.com/hkust-zhiyao/RTL-Coder (accessed on 20 January 2026)
Spec2RTL-Agenthttps://cirkitly.kernex.sbs/ (accessed on 20 January 2026)
OriGenhttps://github.com/pku-liang/OriGen (accessed on 20 January 2026)
AutoChiphttps://github.com/shailja-thakur/AutoChip (accessed on 20 January 2026)
CodeVhttps://github.com/cluesmith/codev (accessed on 20 January 2026)
VeriCoderhttps://github.com/Anjiang-Wei/VeriCoder (accessed on 20 January 2026)
StarCoderhttps://github.com/bigcode-project/starcoder (accessed on 20 January 2026)
CodeLlamahttps://github.com/meta-llama/codellama (accessed on 20 January 2026)
DeepSeek-Coderhttps://github.com/deepseek-ai/DeepSeek-Coder (accessed on 20 January 2026)
CodeQwenhttps://github.com/QwenLM/qwen-code (accessed on 20 January 2026)
Geminihttps://gemini.google.com/ (accessed on 20 January 2026)
GPThttps://chatgpt.com/ (accessed on 20 January 2026)
ChatEDAhttps://github.com/wuhy68/ChatEDA (accessed on 20 January 2026)
Synthesis ToolsYosyshttps://yosyshq.net/yosys/ (accessed on 20 January 2026)
ABC (Berkeley)https://people.eecs.berkeley.edu/~alanmi/abc/ (accessed on 20 January 2026)
ODIN II (VTR)https://docs.verilogtorouting.org/en/latest/odin/ (accessed on 20 January 2026)
GHDL-Yosys Pluginhttps://github.com/YosysHQ/yosys (accessed on 20 January 2026)
Synlighttps://github.com/chipsalliance/synlig (accessed on 20 January 2026)
Mockturtle (EPFL)https://github.com/lsils/mockturtle (accessed on 20 January 2026)
Simulation & Verification ToolsVerilatorhttps://www.veripool.org/verilator/ (accessed on 20 January 2026)
Icarus Veriloghttps://steveicarus.github.io/iverilog/ (accessed on 20 January 2026)
cocotbhttps://www.cocotb.org/ (accessed on 20 January 2026)
GTKWavehttps://gtkwave.sourceforge.net/ (accessed on 20 January 2026)
Yosys-SMTBMChttps://symbiyosys.readthedocs.io/en/latest/reference.html (accessed on 20 January 2026)
EQYhttps://github.com/YosysHQ/eqy (accessed on 20 January 2026)
CoSAhttps://github.com/cristian-mattarei/CoSA (accessed on 20 January 2026)
OpenSTAhttps://github.com/The-OpenROAD-Project/OpenSTA (accessed on 20 January 2026)
OpenTimerhttps://github.com/OpenTimer/OpenTimer (accessed on 20 January 2026)
Tatum (VTR)https://github.com/verilog-to-routing/tatum (accessed on 20 January 2026)
Physical Design Flow ToolsOpenROADhttps://theopenroadproject.org/ (accessed on 20 January 2026)
OpenLanehttps://github.com/The-OpenROAD-Project/OpenLane (accessed on 20 January 2026)
iEDAhttps://github.com/OSCC-Project/iEDA (accessed on 20 January 2026)
SiliconComphttps://github.com/siliconcompiler/siliconcompiler (accessed on 20 January 2026)
Fabricable PDKsSKY130https://github.com/gdsfactory/skywater130 (accessed on 20 January 2026)
GF180MCUhttps://github.com/google/gf180mcu-pdk (accessed on 20 January 2026)
IHP SG13G2https://github.com/IHP-GmbH/IHP-Open-PDK (accessed on 20 January 2026)
ICsprout55https://github.com/openecos-projects/icsprout55-pdk (accessed on 20 January 2026)

Mar 24, 2026

[DATE2026 Panel] Empowering Education through Open-Source Hardware

 #SavetheDate | On April 22, 2026, at 11:00 Norbert Wehn and Lukas Krupp from the RPTU Kaiserslautern-Landau will host a special session at the DATE Conference 2026 in Verona, Italy: “Empowering Education through Open-Source Hardware”.


The session focuses on how open design ecosystems can make chip development more accessible, from first hands-on experiences to full design flows from system level to GDSII. Topics include:
  • open-source hardware in education
  • hands-on chip design across the full stack
  • broader access to PDKs, IP, and EDA tools
Panelists:
  • Luca Benini (ETH Zürich)
  • Luca Carloni (Columbia University)
  • Oscar Gustafsson (Linköping University)
  • Patrick Haspel, PhD (Synopsys Inc)
  • Prof. Dr.-Ing. Gerhard Kahmen (IHP – Leibniz Institute for High Performance Microelectronics)
  • Matt Venn (Tiny Tapeout)
Save the date and learn more about our upcoming stops and events here: 
https://lnkd.in/dgGbnJgn


Mar 11, 2026

26th Workshop Analog Circuits

26th Workshop Analog Circuits 
12.03.2026 and 13.03.2026
at Leibniz University Hannover

The workshop series offers a platform to present one's own ideas and discuss results with science and industry. The focus is on integrated analog and mixed-signal circuits.

The workshop will take place on 12.03.2026 and 13.03.2026 in the Royal Horse Stable of the University of Hannover.  Registration - Participation in the workshop is free of charge.

The programme will be compiled after the call for papers has been completed and is avalable online 

In the run-up to the 26th Workshop on Analog Circuits, the DE:Sign cooperation event on the topic of "Open Source Tools for Analog Design" will take place on the morning of 12.03.2026. In this event, the funded projects will present their current status on open design tools and methods for analogue design. Participants will receive an overview of the contribution of the respective projects to the development of technology open, accessible, and sustainable design chains in the sense of the DE:Sign guideline.

If you have any questions, please contact the organizers by e-mail at: analog2026@ims.uni-hannover.de

Mar 2, 2026

Aalto Microelectronics Fair

Aalto Microelectronics Fair
March 20, 2026, 9.00-15.30
Aalto Yliopisto, Kandidaattikeskus, H304, Otakaari 1, 02150 Espoo

Time Session
8:30–9:00 Morning coffee
9:00–9:15Opening
Aleksi Korsman
Keynotes
9:15–10:00Keynote 1: “OpenPDK - Global Scholar Platform”,
Wladek Grabinski, Open PDK Initiative


10:05–10:50Keynote 2: “Open Source Design Tools in SME IC Design Companies”,
Ari Paasio, Kovilta




Research overviews
11:00–11:15Research overview: Kari Stadius
11:15–11:30Research overview: Prof. Marko Kosunen
11:30–11:45Research overview: Prof. Kwantae Kim
11:45–12:45Lunch (and posters)
12:45–13:15Student talk: “Five years of RISC‑V processor design at Aalto”,
Aleksi Korsman
13:15–13:45Student talk: “Beyond Neural Networks: Overcoming the Symbolic Bottleneck via Approximate Logarithm Acceleration”,
Lingyun Yao
Posters
13:45–14:00Poster intro
14:00–15:00Posters with coffee and snacks
15:00–15:30Feedback and closing

Should you have any questions, please email Marko Kosunen