[mos-ak] [C4P] Submissions Now Open for IEDM 2026

Submit a Paper Meeting Info Contact Us Submissions Now Open Deadline: July 16, 2026 The IEEE International Electron Devices Meeting Committee is seeking paper submissions for the 2026 IEDM Conference, themed “Devices at the Hearth of the Intelligence Revolution” We invite contributions from various areas of expertise (view all suggested topics).  Format: Papers must be submitted electronically in a PDF format, compatible with IEEE Xplore Guidelines: Before preparing your paper, please review the paper preparation and submission guidelines on our website where you’ll find a paper template, sample paper and additional preparation details. Presentation: Accepted papers MUST be presented in person at the conference AND authors must submit a pre-recording of their presentation for OnDemand registrants. Call for Papers Info Student Papers We highly encourage student submissions. Papers presented by students based on their own work are eligible for the Best Student Paper Award. To be considered, the paper must be identified as a student paper during submission. The award will be judged on the paper's quality and its presentation, which must be delivered by the student. The winner of the award will be announced and honored at IEDM 2027. MEETING HIGHLIGHTS IEDM is the world’s preeminent forum for reporting technological breakthroughs in semiconductor and electronic device technology, design, manufacturing, physics, and modeling. The conference will feature: Three plenary presentations  Special focus sessions  Evening panel discussions  Tutorial sessions Short Courses  Mark your calendar for December 12-16, 2026, and join us in San Francisco, CA. Attendee:  For more information IEDM Online Email: info@ieee-iedm.org Social Networks (Info/Follow) IEDM | Canfield Event Management, LLC | +1 972 521-9902 | ieee-iedm@cemllc.com

IEDM | 445 Hoes Lane | Piscataway, NJ 08854 US

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[paper] SPICE-Q Quantum Chip Production

Ling Qiao Cai1,2, Bin Yang1,2, Fumin Luo1,2, Chang Liu1,2, WeiGui Guo1,2, GuoRong Zhang1,2, XueFei Liu1,2, Qinglang Guo1,2 and Bin Wu

SPICE-Q and Large-Scale Quantum Chip Production

[quant-ph] 16 Jun 2026 

arXiv:2606.17907v1  

1.) Yangtze Delta Industrial Innovation Center of Quantum Science and Technology, Suzhou, (CN)
2.) China Academy of Electronics and Information Technology, No. 11 Shuangyuan Road, Shijingshan District, Beijing, (CN)

Abstract: The historical analogy with SPICE is based on foundational reports, numerical methods, and experience from integrated circuit design. The requirements for quantum computing and scaling refer to established work in the field. The background on superconducting qubits, transmons, circuit quantum electrodynamics, microwave networks, material loss, and three‑dimensional interconnects draw from widely recognized literature. The background on parameter extraction, simulation frameworks, and manufacturability is informed by recent research and practical developments.

Table of Contents (Top‑Level Sections)

1. Abstract ... p. 4
2. The Emergence of SPICE and Large‑Scale Classical Circuits
   and Its Implications for Quantum Chips ... p. 5
3. SPICE‑Q Model Composition ... p. 24
4. SPICE‑Q Device‑Level Models ... p. 40
5. Standardized Manufacturing System ... p. 53
6. Integrating SPICE‑Q with Process Models ... p. 66
7. Design‑Technology Co‑Optimization (DTCO) ... p. 71
8. Large‑Scale Production Examples and Design Scenarios ... p. 75
9. Engineering Transition and Large‑Scale Quantum Chips ... p. 80
10. Summary ... p. 84
11. Acknowledgment ... p. 87
12. Reference ... p. 87
13. Appendix A ... p. 90

Acknowledgment The authors thank Jun Ye for helpful assistance. The authors also acknowledge the use

of AI tools for translation assistance and auxiliary text generation.

[paper] 130-nm CMOS tunnel p-bit cell

Ju-Young Yoon, Nuno Caçoilo, Advait Madhavan, Jabez J. McClelland, Shun Kanai, Hideo Ohno, Shunsuke Fukami, and William A. Borders, 

"130-nm CMOS-integrated superparamagnetic tunnel junction-based p-bit," 

in IEEE Electron Device Letters, 

DOI: 10.1109/LED.2026.3696800

Abstract: Probabilistic computers offer promising solutions for computationally hard problems in domains such as combinatorial optimization and machine learning. A key building block in these systems is the probabilistic bit (p-bit), which relies on superparamagnetic tunnel junctions (sMTJs) as its source of randomness. A challenging threshold to cross for scaling sMTJ-based p-bit systems is integration of sMTJs with CMOS technology. In this work, we present experimental results of a p-bit unit cell using sMTJs integrated with 130 nm CMOS technology and demonstrate that the sMTJ’s resistance fluctuations can generate a corresponding fluctuating digital output voltage which is tunable via the input voltage. These findings establish the feasibility of CMOS-compatible, sMTJ-based probabilistic circuits and mark a key step toward scalable hardware for real-world probabilistic computing applications. 

FIG: (a) Circuit diagram of the spintronic p-bit; b) Schematic cross-sectional structure of the spintronic p-bit. Transistors and lower interconnect layers were fabricated at SkyWater, followed by fabrication of the spintronic devices at Uni. Tohoku. (c,d) Cross-sectional and plan-view electron microscope images of the spintronic device designed to exhibit stochastic fluctuations.

Acknowledgements: This work was made possible by the NIST-led Nanotechnology Xccelerator program that distributes open-source circuit designs for integration of novel technologies on CMOS.

RevEDA v0.9.0 Has Arrived

Revolution EDA v0.9.0 Has Arrived The wait is over. Revolution EDA v0.9.0 is now available, delivering our largest feature update to date and taking another major step toward a complete open-source analog and mixed-signal IC design platform. This release introduces integrated verification workflows, expanded simulation support, AI-assisted design tools, a new plugin ecosystem, and important architectural improvements designed to help engineers move faster from concept to silicon. Why This Release Matters Version 0.9.0 brings together capabilities that traditionally require multiple disconnected tools. By integrating verification, automation, extensibility, and simulation workflows into a unified environment, Revolution EDA continues to make professional IC design more accessible to engineers, researchers, educators, and startups. Highlights of v0.9.0 Integrated LVS Verification Layout-versus-Schematic (LVS) checking is now built directly into Revolution EDA. Users can: Extract hierarchical netlists from layouts and schematics Compare extracted and reference netlists Review detailed mismatch reports Cross-probe errors between schematic and layout views This significantly reduces verification effort and helps catch issues earlier in the design cycle. Expanded Simulation Support Revolution EDA now includes support for Xyce netlist generation, providing greater flexibility for simulation workflows. In addition, support for Spectre and VACASK netlisting is actively under development, bringing us closer to a truly multi-simulator environment. Hierarchical netlisting has also been enhanced with support for buses and instance arrays, enabling more complex and scalable designs. AI-Powered Design Assistance The new AI Terminal allows designers to interact with Revolution EDA using natural language. From automating repetitive tasks to exploring design modifications and workflow assistance, AI capabilities are becoming a native part of the design experience. We're only at the beginning of what's possible, and future releases will continue expanding these capabilities. New Plugin & Library Registry One of the most requested features is finally here. The new Plugin Registry and Library Registry make it simple to discover, install, and manage extensions directly from within Revolution EDA. The underlying architecture has also been redesigned to support clean integration of: Process Design Kits (PDKs) Plugins Custom workflows Third-party extensions without requiring modifications to the core codebase. Foundations for Schematic-Driven Layout Version 0.9.0 introduces the first implementation of Schematic Driven Layout (SDL), creating the foundation for tighter synchronization between circuit intent and physical implementation. Future releases will continue building on this capability to further streamline analog layout development. Coming Soon: Expanded IHP PDK Support We're also excited to share that work on the IHP PDK continues at a rapid pace. New parametric cells (PCells) are currently being added and validated, expanding device coverage and improving layout productivity. These additions are expected to be released shortly, providing designers with a richer and more capable open-source design environment built around the IHP technologies. Stay tuned for a dedicated announcement in the coming weeks. Under the Hood Improvements Alongside the headline features, v0.9.0 includes substantial improvements to performance, stability, and usability: Improved file validation and project security Faster editor responsiveness Better thread management and application stability Enhanced project workflows Numerous bug fixes across netlisting, layout editing, and plugin management MPL-2.0 Licensing Beginning with v0.9.0, Revolution EDA is distributed under the Mozilla Public License 2.0 (MPL-2.0). This change supports broader commercial and academic adoption while preserving the collaborative spirit of open-source development. Download v0.9.0 Today Whether you're designing analog ICs, building custom design flows, developing plugins, or evaluating open-source EDA solutions, Revolution EDA v0.9.0 offers powerful new capabilities ready for exploration. Download the latest release, update your existing installation, and let us know what you build. As always, your feedback, bug reports, feature requests, and contributions help shape the future of Revolution EDA. Contact us! The Revolution EDA Team

ChipFoundry September Shuttle

The commitment deadline for our September shuttle is fast approaching on July 18th.   We want to remind you that this is not the final design submission date. Here is what you need to know to confirm your space:   A 50% payment is required by July 18th to hold your reservation. Your final design files are not due until September 16th. You only need to provide your user project wrapper, and we will handle the integration through our tapeout flow.   Our team is available if you have any questions about the submission process or need help with your invoice. Reserve Now We look forward to confirming your commitment and working with you on your September tapeout!   Best regards,   The ChipFoundry Team