[QEMU 11.0] Brings New RISC-V Extensions, Fixes

QEMU 11.0 Brings New RISC-V Extensions, Fixes The latest release of the QEMU emulator, version 11.0, is out, and brings with it support for the RISC-V Zilsd, Zclsd, Zalasr, and Smpmpmt extensions - plus various compatibility and security fixes. “We’d like to announce the availability of the QEMU 11.0.0 release. This release contains 2500+ commits from 237 authors,” the project maintainers write of the new release. “Thank you to everybody who contributed to this release, whether that was by writing code, reporting bugs, improving documentation, testing, or providing the project with CI resources. We couldn’t do these without you!” The latest QEMU release brings with it support for four new extensions to the free and open RISC-V instruction set architecture: Zilsd and Zclsd, RV32-exclusive extensions to add register pair load and store instructions by reusing existing RV64-only instruction encodings; Zalasr, an atomic load-acquire store-release extension; and Smpmpmt, which provides a memory attribute control mechanism analogous to the RV64-only Rvpmt using PMP registers. The full changelog is available on the QEMU wiki; releases are available on the project website, with full source code available on GitLab under the reciprocal GNU General Public Licence 2 or later. Copyright © 2026 The Free and Open Source Silicon Foundation C.I.C., All rights reserved. You are receiving this e-mail because you opted in at our website. Our mailing address is: The Free and Open Source Silicon Foundation C.I.C. Unit C5 Tenterfields Business Park Halifax, HX2 6EQ United Kingdom

[paper] FDSOI Based Cryogenic Circuit

Tapas Dutta, Fikru Adamu-Lema, Djamel Bensouiah, German Cherstvov, Plamen Asenov,

and Asen Asenov

FDSOI Based Cryogenic Circuit Performance Enhancement 

Using Back Biasing and Threshold Voltage Engineering

IEEE Journal of the Electron Devices Society (2026)

DOI 10.1109/JEDS.2026.3691285

Device  Modelling  Group,  University of Glasgow, UK
Pramana  Modelling  Labs,  Glasgow, UK
School of  Engineering,  University of Glasgow, UK
Semiwise  Ltd.,  Glasgow, UK

Synopsys,  Glasgow, UK

Abstract : In this work, we use predictive cryogenic spice based compact models derived using a process design kit re-centering approach for 22 nm FDSOI technology to analyze the impact of back-gate biasing on circuit performance. We focus on analysis of power-delay trade-offs while varying the supply voltage at room and cryogenic temperature (4K). We show that back-biasing is necessary to mitigate the effects of the higher threshold voltages observed at cryogenic temperature. We further show that simple “threshold voltage engineering” has the potential to provide much better performance, compared to room temperature.

Fig : IDS −VGS characteristics for different VBG going to much higher values 

than the previous sections (without applying anyVth shift).

Acknowledgement : We are grateful to GlobalFoundries for providing the 22FDX PDK and allowing us to customize it for cryogenic temperature operation. The device measurements were performed by Incize SRL, Belgium. This work was supported partially by Innovate UK funded project “Development of Cryo-CMOS to enable the next generation of scalable quantum computers” under the grant number of 10006017 and was also partially supported by Semiwise Ltd, UK.

[VACASK] device-level transient noise analysis

VACASK, a free and open-source analog circuit simulator, now does device-level transient noise analysis. As far as I know, this is a first among FOSS circuit simulators. Ngspice has had source-based transient noise for a while, but the user has to wire noise sources into the circuit by hand. In VACASK, every resistor, diode, and transistor contributes its own white (thermal and shot) and flicker (1/f) noise automatically during the transient run, the way Spectre and other commercial RF simulators do it.

Why it matters: this lets you actually see how noise shapes the behavior of oscillators, PLLs, mixers, and sampling circuits in the time domain, not just as an abstract spectral quantity.

Quick demo on an LC oscillator at fosc=245kHz:

Top: power spectral density of the output

Middle: single-sideband phase noise (SSB PSD)

Bottom: phase jitter accumulating over time

Having this in a FOSS tool opens the door for students, hobbyists, and researchers to run the same analyses that were previously gated behind five and six-figure licenses.

Árpád Bűrmen, the lead VACASK developer, would love to hear from anyone working on analog/RF simulation. 

What would you put it through first?

https://codeberg.org/arpadbuermen/VACASK

#OpenSource #AnalogDesign #CircuitSimulation #RFDesign #EDA

[seminar] OpenPDK - Global Scholar Platform

Radiofrequency, Microwave and Millimetre-Wave Lab (mmiRF)

ETSI Telecomunicación,  Universidad de Málaga, Andalusia

Wednesday, May 27th, at 12:00

The mmiRF Lab is pleased to invite you to our upcoming hybrid seminar, which will be available both in person and online:

• OpenPDK - Global Scholar Platform
• Wednesday, May 27th, at 12:00
• mmiRF Lab, ETSI Telecomunicación, Universidad de Málaga
• Join the meeting online (MS Teams)

The semiconductor industry is evolving. The emergence of OpenPDKs is creating a new platform for global collaboration and education. The seminar will explore:

• The role of FOSS CAD/EDA tools in building a global talent ecosystem.
• OpenPDK initiatives from SkyWater, GF, and IHP (the first in Europe).
• Complete open IC design flows: Xschem, ngspice, Xyce, Magic, kLayout, and more.
• Hands-on examples of analog, RF, and digital IC design

Don't miss this chance to learn from a leading expert in the field and explore the tools shaping the future of microelectronics! 

#mmiRF #OpenPDK #Semiconductors #ICDesign #FOSS #EDA #Microelectronics #Innovation #UMA #STEM #MOS-AK

Speaker Bio: Wladek Grabinski received his Ph.D. from the ITE Warsaw, in 1991. He worked at ETHZ on CMOS/BiCMOS characterization and at EPFL on compact EKV model development, later serving as a technical staff engineer at Motorola/FSL in Geneva. He is now a consultant specializing in OpenPDK, coordinating SPICE modeling, device characterization, and parameter extraction for analog/RF IC design, with particular interests in high-frequency measurement, compact modeling and its Verilog-A standardization. He co-edited the book Transistor Level Modeling for Analog/RF IC Design, contributed to the Compact/SPICE Modeling Chapter of the Springer Handbook of Semiconductor Devices, and authored 70+ papers. Furthermore, he also contributes to IEEE EDS, LAEDC, ESSDERC, and MIXDES and manages the MOS-AK association since 1999.

Seeing Transistor Scaling Up Close

 And What “tiny” Really Means - Comparing Modern Chips to the Machines of Life

BEHIND THE CHIP: Apr 17, 2026

<https://behindthechip.substack.com/p/seeing-transistor-scaling-up-close>

[repost] Modern transistors have gate lengths of around 8 nm. To put that in perspective: a red blood cell is 10,000 nm wide. A DNA strand is just 2 nm, and a transistor is sitting right between those two scales. We are literally engineering at the edge of atomic limits, silicon atoms themselves are only 0.2 nm wide.

That foundational brick of modern electronics keeps shrinking year after year, driven by companies like TSMC, Intel, Samsung, and ASML pushing the boundaries of what is physically possible.

Billions of these switches/transistors, smaller than a virus, packed into a chip you can hold between two fingers. That is what powers every microcontroller, every processor, every smart device you touch today.