[paper] Ultralow-Voltage NMOS-Only Voltage Reference

Francesco Gagliardi, Paolo Bruschi, Massimo Piotto, Soumaya Sakouhi, Michele Dei

Ultralow-Voltage NMOS-Only Voltage Reference with High-Frequency PSR Optimization 

via Decoupling Pseudo-Resistor

IEEE ACCESS • Vol. 14, 2026

DOI: 10.1109/ACCESS.2026.3707314

Dipartimento di Ingegneria dell’Informazione, University of Pisa, 56122 Pisa (I)

Abstract: The design of integrated circuits operating at minimal supply voltage and power levels is a key requirement for energy-harvested smart sensing devices. This paper presents a novel NMOS-only 4-transistor voltage reference (VR) that exploits a self-cascode technique with high-frequency power-supply rejection (PSR) optimization through a decoupling pseudo-resistor. Post-layout simulations of a 0.18‑μm CMOS design show low-supply compliance and robustness to process-voltage-temperature variations. The output voltage is 177 mV with line sensitivity of 54 ppm/V in the 0.4–1.8 V supply range, PSR lower than –40 dB down to 0.28 V supply, simulated current consumption of 223 pA, and a mean temperature coefficient of 24.44 ppm/°C from –20 °C to 80 °C. The compact area footprint is 115.2 μm². The results indicate potential for stable low-voltage and low-power voltage reference implementations.

Fig: Small-signal equivalent circuits of (a) the 2T-VR and (b) the 3T-VR. The high-frequency path highlighted in (b) causes a limitation of the 3T-VR topology discussed at the end of this section.

Acknowledgements: This work was supported in part by the National Recovery and Resilience Plan (NRRP) of Italian Ministry of University and Research (MUR) funded by the European Union (EU) NextGenerationEU with the Project HeMoWear under Grant 0004610/2022, and in part by the European Innovation Council (EIC) through the Project Green valorization of CO2 and Nitrogen compounds for making fertilizers (CONFETI) under Grant 101115182. The associate editor coordinating the review of this manuscript and approving it for publication was Poki Chen.

[paper] Reconfigurable Characteristics in MoS2 Transistors

Matteo Farronato, Fabio Carletti, Niccolò Garegnani, Anupam Jana, Matteo Porzani, Saverio Ricci, Augusta Ungarelli, Christian Monzio Compagnoni, Paolo Fantini, Innocenzo Tortorelli, Agostino Pirovano, Christian Rinaldi and Daniele Ielmini

Voltage-controlled reconfigurable characteristics in MoS2 transistors 

via ion migration for reprogrammable logic.

NPJ 2D Mater Appl (2026)

DOI: 10.1038/s41699-026-00720-2

1 DEIB, Politecnico di Milano and IU.NET, Milano, Italy

2 Dipartimento di Fisica, Politecnico di Milano, Italy

3 Micron Technology Inc., Vimercate (MB), Italy

Abstract: 2D semiconductors such as MoS2 offer a promising pathway for future logic and analog transistors and memories. These materials feature scalable channel size, back-end of the line compatibility, and high mobility for relatively small channel thickness approaching few atomic monolayers. An open issue for the development of mature 2D-based digital technology is the availability of both n- and p-type transistors, as well as the ability to control the transistor type in a reconfigurable way. This work presents a novel MoS2-based transistor exhibiting reconfigurable n- or p-type characteristics, namely switching from n-type to p-type and vice versa, which is attributed to ion-assisted doping from the gate dielectric layer. Extensive characterization of the device shows repeatable switching with relatively low cycle-to-cycle (C2C) and device-to-device (D2D) variability. A reconfigurable p-n junction is demonstrated via a junction-less multi-gate MoS2-based transistor. We also demonstrate various reconfigurable logic gates, including a complementary metal-oxide-semiconductor (CMOS) inverter, a fully n-type inverter and an XNOR logic gate based on MoS2 transistors, showcasing the generality and flexibility of channel reconfiguration for logic circuit applications. These results underscore the strong potential of reconfigurable MoS2 transistors for ultra-scaled, reconfigurable logic circuits.

Fig: Logic gates with reconfigurable MoS2 transistors. (a) SEM image of a logic inverter or CMOSNOT gate with two transistors in the same MoS2 flake. (b) Schematic of the inverter with reconfigurable MoS2 transistors and logic truth table.

Acknowledgments: This article has received funding from the European Research Council (ERC) under the EuropeanUnion’s Horizon Europe Research and Innovation Programme (grant 101054098). Authors want tothank all the Polifab (the micro and nano technology infrastructure of Politecnico di Milano) staff fortheir help in the fabrication of the MoS2-based devices.

[paper] Harmonic Distortion of GaN HEMT Varactors

Loukas Chevas 1,  Matthias Bucher 1,  Nikolaos Makris 1,2, Ioannis Spiridon Fosteris 1,  Nikolaos Fasarakis 1,  Antonios Stavrinidis 2,1, Maria Kayambaki 2,  Athanasios Kostopoulos 2 

and George Konstantinidis 2

Methodology for Harmonic Distortion Characterization and Modelling of GaN HEMT Varactors

Instruments 2026, 10(3), 37; 

DOI: 10.3390/instruments10030037

1 School of Electrical and Computer Engineering, Technical University of Crete, 73500 Chania, Greece
2 Institute of Electronic Structure and Laser, Foundation for Research and Technology-Hellas, 70013 Heraklion, Greece

Abstract: The bias-dependent capacitance of varactors can introduce harmonic distortion into the circuits where they are utilized. A gate capacitance model valid through inversion–depletion has been presented for GaN HEMT varactors in the drive for their utilization in monolithic GaN ASICs. This work focuses on the circuit and the methodology employed to accurately measure on wafer the harmonic distortion caused by one such device. The circuit is presented and its design considerations and operation trade-offs are discussed, followed by a presentation of the measurements resulting from its use. Second- and third-order harmonic distortion is recorded and presented, with Verilog-A model simulations used to fit the measured data. The model consists of a charge-based expression of the HEMT varactor capacitance, with a minimal number of parameters. The good fit of the model is demonstrated, proving both the suitability of the circuit used for the measurements and the validity of the capacitance model for real-world applications.  

Fig: Measurement setup schematic for the harmonic distortion characterization of HEMT varactors and V(f) characterization of the HEMT varactor. Inset is the parallel impedance combination measured by the LCR meter. (a) Cgc(Vg) for fixed frequencies. (b) Cgc(f) for fixed Vg levels. (c) Rp(Vg) for fixed frequencies. (d) Rp(f) for fixed Vg levels.

Aknowlegements: This research was partially funded by the European Union under the project AGAMI_EURIGAMI (ID:101102983).

Data Availability Statement: The measurement data generated and analyzed during the present study are available from the corresponding author upon reasonable request.

[mos-ak] [Final Program] 23rd MOS-AK/ESSERC Workshop in Palma de Mallorca (SP) Sept. 7, 2026

Arbeitskreis Modellierung von Systemen und Parameterextraktion

Modeling of Systems and Parameter Extraction Working Group

MOS-AK FOSS OpenPDK Workshop
ESSERC, Palma de Mallorca, Sept. 7 2026

The 23rd MOS‑AK/ESSERC Compact Modeling Workshop in Palma de Mallorca brings together the international community advancing SPICE/Verilog‑A modeling, OpenPDKs, and open‑source IC design flows. Since 2002 ESSEDRC/ESSCIRC in Porto, MOS‑AK has been the leading forum connecting technology developers, circuit designers, and FOSS CAD/EDA contributors, supporting knowledge exchange and strengthening the open semiconductor ecosystem. This year’s program showcases cutting‑edge developments: GaN MOS‑HEMT compact models for emerging OpenPDKs, AI/ML‑driven modeling workflows replacing manual tuning, cryogenic FD‑SOI model libraries, fully open‑source RFIC design case studies using IIC‑OSIC‑TOOLS, reliability insights for advanced CMOS and RF technologies, and a new OpenPDK MOSFET matching matrix IC enabling fast mismatch characterization. The workshop organizers are inviting engineers, researchers, and students who want a clear, practical view of modern device models and open simulation frameworks. It directly supports global OpenPDK adoption and aligns with European ODE4EC‑AMS activities, promoting accessible, reproducible, and future‑ready IC design methodologies. The MOS-AK workshop program is available online as well as with the direct link:

<https://www.mos-ak.org/palma_2026/>

Venue: ESSERC, Palma de Mallorca (SP)
Online Registration is OPEN (Early: until FRIDAY July 17, 2026)

MOS-AK ESSERC W7 Workshop Agenda

9:30 - 11:00	W7 Workshop Opening
T_1	ODE4EC-AMS OpenPDK: the Status and Roadmap Wladek Grabinski IHP OpenPDK (D)
T_2	Advanced in Verilog-A Model Standardization Arpad Buermen Uni. Ljubljana (SL)
T_3	Compact Modeling of GaN MOS-HEMTs for Open PDKs Ashkhen Yesayan EPFL (CH)
T_4	From Manual Tuning to Agentic AI: Transforming Device Modeling with AI/ML Roberto Tinti Keysight (US)
11:00 - 11:30	Coffee Break
T_5	Development of Cryogenic Model Libraries for FD-SOI Transistors Phanish Chava AdMOS (D)
T_6	Open-Source RFIC Design: Case Studies Using IIC-OSIC-TOOLS Georg Zachl JKU Linz (A)
T_7	Reliability topics for the miniaturization and qualification in OpenSilicon perspective Fernando Guarin IEEE EDS D1 (US)
T_8	OpenPDK MOSFET Matching Matrix IC Juan Brito CEITEC (BR)
13:00-14:00	End of the W7 Workshop and Lunch Break

W.Grabinski for Extended MOS-AK Committee

WG060726

[mos-ak] [C4P] Submissions Now Open for IEDM 2026

Submit a Paper Meeting Info Contact Us Submissions Now Open Deadline: July 16, 2026 The IEEE International Electron Devices Meeting Committee is seeking paper submissions for the 2026 IEDM Conference, themed “Devices at the Hearth of the Intelligence Revolution” We invite contributions from various areas of expertise (view all suggested topics).  Format: Papers must be submitted electronically in a PDF format, compatible with IEEE Xplore Guidelines: Before preparing your paper, please review the paper preparation and submission guidelines on our website where you’ll find a paper template, sample paper and additional preparation details. Presentation: Accepted papers MUST be presented in person at the conference AND authors must submit a pre-recording of their presentation for OnDemand registrants. Call for Papers Info Student Papers We highly encourage student submissions. Papers presented by students based on their own work are eligible for the Best Student Paper Award. To be considered, the paper must be identified as a student paper during submission. The award will be judged on the paper's quality and its presentation, which must be delivered by the student. The winner of the award will be announced and honored at IEDM 2027. MEETING HIGHLIGHTS IEDM is the world’s preeminent forum for reporting technological breakthroughs in semiconductor and electronic device technology, design, manufacturing, physics, and modeling. The conference will feature: Three plenary presentations  Special focus sessions  Evening panel discussions  Tutorial sessions Short Courses  Mark your calendar for December 12-16, 2026, and join us in San Francisco, CA. Attendee:  For more information IEDM Online Email: info@ieee-iedm.org Social Networks (Info/Follow) IEDM | Canfield Event Management, LLC | +1 972 521-9902 | ieee-iedm@cemllc.com

IEDM | 445 Hoes Lane | Piscataway, NJ 08854 US

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