[paper] Ion-Sensitive FET Memory

Henrique Lanfredi Carvalho, Pedro Henrique Duarte, Ricardo Cardoso Rangel 

and Joao Antonio Martino

“Effect of gate capacitance ratio on ion-sensitive FET memory”

Solid-State Electronics (2026) Art. no. 109350.

doi: 10.1016/j.sse.2026.109350

* LSI/PSI/USP, University of Sao Paulo, Sao Paulo, Brazil

Abstract: This paper introduces the ISFET Memory device, which combines nonvolatile memory capabilities with the traditional ISFET functionality for pH sensing applications. The device’s performance is evaluated in both writing and erasing modes, with particular emphasis on how adjusting the gate capacitance ratio (GCR) influences the operating voltages and sensitivity. Results show that optimizing the GCR to 0.43 significantly reduces the voltages required for writing and erasing operations, while also enhancing sensitivity across a broader pH range. The device achieves maximum sensitivities of 1609 mV/pH in the writing state and 940 mV/pH in the erasing state, far exceeding the ideal ISFET sensitivity of 58.2 mV/pH. Furthermore, the device demonstrates adaptability to different pH ranges: the writing mode is better suited for pH values from 2 to 10, whereas the erasing mode is more effective for the remaining pH range.

Fig: Cross section of ISFET Memory (a) and with optimized structure (b)

Acknowledgment: The authors acknowledge CNPq, CAPES (Coordenação de Aperfeiçoamento de Pessoal de Nível Superior – Brazil - Finance Code 001) and São Paulo Research Foundation - FAPESP (under grant #2020/04867-2) for the financial support.

[+] This article is part of a special issue entitled: ‘EuroSOI-ULIS 2025’ published in Solid State Electronics.

[paper] Compact Modeling of Ferroelectric Devices

J. Lee, J. Kim, M. Kim, H. Kim, C. Ra, H. Choi, and J. Jeon,

“Asymmetry-Aware Compact Modeling of Ferroelectric Devices for Circuit-Level Simulation,”

ACS Applied Electronic Materials, Feb. 2026,

doi: 10.1021/acsaelm.5c02300

* Department of Electrical and Computer Engineering, Sungkyunkwan University (SKKU), Suwon 16419 (KR)

Abstract: This paper presents a unified compact model that comprehensively captures nonideal behaviors such as asymmetric hysteresis and minor loops of ferroelectric devices based on hafnium zirconium oxide (HfO2–ZrO2, HZO). The proposed model, based on the Preisach framework, integrates branch-dependent slopes, asymmetric coercive voltages, imprint-induced loop shifts, and low-voltage minor-loop responses into a unified analytical form. Implemented in Verilog-A, the proposed model reproduces measured polarization–voltage (P–V) characteristics of a ferroelectric capacitor (FeCAP) with higher accuracy than conventional symmetric models. Furthermore, using an identical parameter set, it consistently scales from a single device to logic, memory, and neuromorphic circuits, enabling prediction of operating characteristics and read/write margins. Owing to these capabilities, the model serves as a reliable predictive tool for circuit-level design and provides a practical pathway for process–design feedback and co-optimization.

[paper] Cryo FD SOI LNA Design

Giovani Britton, Salvador Mir, Estelle Lauga-Larroze, Benjamin Dormieu, Jose Lugo, Joao Azevedo, Sebastien Sadlo, Quentin Berlingard, Mikael Casse, Philippe Galy

Using DC transistor characterization measurements for LNA design at cryogenic temperatures

(2026) researchsquare.com

DOI: 10.21203/rs.3.rs-7754596/v1

1. STMicroelectronics, Crolles (F)
2. Univ. Grenoble Alpes, CNRS, Grenoble-INP, TIMA, Grenoble (F)
3. Univ. Grenoble Alpes, CEA-Leti, Grenoble (F)
4. Univ. Grenoble Alpes, CNRS, Grenoble-INP, IMEP-LAHC, Grenoble (F)

Abstract: The design of Radio Frequency (RF) cryogenic circuits has attracted much interest in recent years due to applications such as quantum computers. Interface electronics with ultra-low levels of power consumption at temperatures as low as 4 K are required. Silicon technologies are being considered for implementation because of the possibility of large-scale qubit integration with energy-efficient readout and control interfaces. However, the design of RF cryogenic circuits is complicated because of the lack of standard design kits with the corresponding component models for their simulation at these temperatures. Alternative approaches to avoid costly design and fabrication cycles are possible, in particular the use of Look-Up-Table (LUT) based techniques that exploit characterization data of circuit components at cryogenic temperature. In this paper, we make use of this approach for the design of a RF Low Noise Amplifier (LNA) using a 28 nm FD-SOI technology that has been characterized at cryogenic temperatures1using DC measurements. Furthermore, we also experimentally demonstrate that the DC measurements used are valid to extract the transistor noise parameters used in the LUT-based analysis.

Fig: Measurement of: (a) transconductance gm, and (b) threshold voltage Vth 

for the 28nm FD-SOI technology, from 300K down to 4K.

Acknowledgements: This work was supported by the French CIFRE program and the Labex MINOS of French program ANR-10-LABX-55-01.

[paper] From RTL to Prompt Coding Chip Design

Lukas Krupp∗, Matthew Venn† and Norbert Wehn∗

From RTL to Prompt Coding: Empowering the Next Generation of Chip Designers through LLMs

arXiv:2601.13815v1 [cs.AR] 20 Jan 2026

∗RPTU University of Kaiserslautern-Landau, Kaiserslautern, Germany

†Tiny Tapeout

Abstract: This paper presents an LLM-based learning platform for chip design education, aiming to make chip design accessible to beginners without overwhelming them with technical complexity. It represents the first educational platform that assists learners holistically across both frontend and backend design. The proposed approach integrates an LLM-based chat agent into a browser-based workflow built upon the Tiny Tapeout ecosystem. The workflow guides users from an initial design idea through RTL code generation to a tapeout-ready chip. To evaluate the concept, a case study was conducted with 18 high-school students. Within a 90-minute session they developed eight functional VGA chip designs in a 130 nm technology. Despite having no prior experience in chip design, all groups successfully implemented tapeout-ready projects. The results demonstrate the feasibility and educational impact of LLM-assisted chip design, highlighting its potential to attract and inspire early learners and significantly broaden the target audience for the field.

Fig: Overview of the proposed idea-to-GDSII learning workflow integrating the LLM-based chat agent for the RTL implementation, VGA simulation tool, and GitHub-driven backend flow.

Acknowledgments: This paper was funded by the German Federal Ministry of Research, Technology and Space (BMFTR) as part of the “Chipdesign Germany” project under grant number 16ME0890.

ChipFoundry Webinar Recording: New CLI, OpenFrame & Production

ChipFoundry Webinar: New CLI, OpenFrame and Production   Please find the link to the video recording: https://youtu.be/7gIYObtXvPM   You can also find a link to the slides here.   If you have any further questions, please reach out to us at info@chipfoundry.io Cheers, The ChipFoundry Team ­ ­ ChipFoundry