M. Saravanan, Eswaran Parthasarathy, Shiromani Balmukund Rahi and Ramkumar Natarajan
Impact of drain and source engineering on dual metal InAs-GaSb VTFETs
with high-K gate stack design
with high-K gate stack design
Sci Rep 15, 44796 (2025) DOI: 10.1038/s41598-025-28448-x
Department of Electronics and Communication Engineering, SRM Institute of Science and Technology, Kattankulathur, 603203, India
University School of Information and Communication Technology, Gautam Buddha University, Greater Noida, 201312, Uttar Pradesh, India
Department of Electronics and Communication Engineering, SR University, Warangal, 506371, Telangana, India
Abstract: The performance of a Dual-Metal-InAs-GaSb Vertical Tunnel Field Effect Transistor (DM-InAs-GaSb VTFET) with an InAs source pocket was investigated in relation to the gate dielectric materials. This research chose gate dielectric materials such as SiO2, Al2O3, HfO2, and ZrO2. The simulation is performed using the Silvaco Technology Computer-Aided Design (TCAD) software. The drain current (ION) of the DM-InAs-GaSb VTFET, which includes an InAs source pocket and an extended drain, is assessed across several dielectric materials; still, ZrO2 (7.92 × 10− 5 A/µm) and HfO2 (8.15 × 10− 5 A/µm) demonstrate enhanced performance. The transconductance (gm) values were 606 µS/µm for HfO2 and 589 µS/µm for ZrO2. A comparison is performed between the Ge-Si VTFET and the suggested configuration. The proposed DM-InAs-GaSb VTFET demonstrates a 1.5-times increase in ON current (ION) and a three-time boost in transconductance (gm). The frequency response of the proposed device was evaluated by employing its SPICE characteristics to construct the common source amplifier in the SPICE circuit simulator. This amplifier comparison reveals that ZrO2 and HfO2 insulators provide significant gain, with HfO2 displaying a cut-off frequency of 1.808 GHz.
FIG: Cross-sectional schematic (a) DM-InAs-GaSb VTFET with split drain (Device-A),
(b) DM-InAs-GaSb VTFET with reduced channel (Device-B),
(c) DM-InAs-GaSb VTFET with drain extension (Device-C).
(b) DM-InAs-GaSb VTFET with reduced channel (Device-B),
(c) DM-InAs-GaSb VTFET with drain extension (Device-C).
Acknowledgements: The authors acknowledge the SRM Institute of Science and Technology, Kattankulathur, Chennai, India for providing the support and facility to carry out this research work.
