Sadık İlik, Masoud Babaie, Andrei Vladimirescu and Fabio Sebastiano
Characterization and Modeling of MOSFET Gate Capacitance Under Cryogenic Operation
IEEE Journal of the Electron Devices Society (2026)
DOI 10.1109/JEDS.2026.3745897
1 Delft University of Technology, 2628 CJ Delft (NL)
2 Qutech, 2628 CJ Delft (NL)
3 University of California at Berkeley, CA (US)
Abstract—The modeling of incomplete ionization is a key element for a reliable and scalable cryogenic transistor model. Despite the increasing interest in cryo-CMOS modeling, capacitance–voltage (CV) characteristics remain relatively unexplored, even though they are less sensitive to secondary effects, such as mobility variations, than DC measurements. While the experimental data in the literature are few and limited, a clear discrepancy is observed between model predictions and capacitance–voltage (CV) measurements. To address these limitations, this paper presents a new, accurate, and scalable capacitance model including an incomplete ionization model that predicts cryogenic behavior more accurately than existing models, along with a corresponding charge model derived from the proposed formulation. The model accurately reproduces all CV features, including the field-dependent ionization–induced flatband voltage dip, the depletion-region capacitance, the trap related threshold voltage humps, and the inversion region. Extensive CV characterizations over multiple device geometries, frequencies, AC excitation voltages, and temperatures are finally used to validate the model.
Fig: Inversion capacitance at 4.2 K for PMOS (a)–(d) and NMOS (e)–(h) devices with varying geometries. In (a), (b), (d), (e), (f), and (h), identical small-sized devices are connected in parallel to enable characterization with sufficient SNR.
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