Open Silicon microelectronic bootcamp

Call for leaders to organize an Open Silicon microelectronic bootcamp

Bring Chip Design to Your Community!

Join the global Open Silicon movement and gain hands-on experience in chip design and fabrication. Our Q1 2026 bootcamps provide access, mentoring, and real silicon opportunities for students, educators, and innovators.

The IEEE is seeking passionate leaders from around the world to organize microelectronics design bootcamps in their local communities, under the IEEE division 1 OPEN SILICON initiative.

If you organize a bootcamp between February and May 2026, IEEE will sponsor the fabrication of three of your designs. You'll receive your fabricated chips (tape-out) mounted on a development board for testing and hands-on exploration.

Selected bootcamp leaders will be invited to an online training session with Matt Venn (Tiny Tapeout) during the last week of February.

To be considered, please provide the following information at REGISTRATION FORM

Key Dates:

• Bootcamp Leader Registration Deadline: Sunday, February 22nd, 2026
• Leader Training Session: Last week of February (TBD)
• Bootcamp Period: March–May 2026
• Tapeout Submission Deadline: March 23rd, 2026 / May 1st, 2026
• Development Board Shipping: September 2026 / November 2026

ICMC 2026: Paper Deadline Extended!

Submission Deadline Extended Submit Now IMPORTANT DATES February 16, 2026:   Extended Submission Deadline April 6, 2026:   Acceptance Notification May 10, 2026:   Final Version for Publication   This year, the  International Compact Modeling Conference (ICMC)  especially encourages submissions in the following domains: Electrostatic Discharge (ESD) modeling for protection design Reliability and aging-aware compact models and simulation techniques AI or Machine Learning for model development, parameter extraction, circuit simulation efficiency, etc. We are also seeking submissions in the following domains: Application of Device Models Device Model Development Model Enhancements and Implementations Emerging Devices   Submit Now     Conference Sponsors       Media Sponsors     Industry Sponsors

[C4P] MIXDES 2026

CALL FOR PAPERS

33rd International Conference

MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS

MIXDES 2026

25 - 27 June 2026, Poznań, Poland

MIXDES Areas of Interest include:
1. Design of Integrated Circuits and Microsystems

Design methodologies. Digital and analog synthesis. Hardwaresoftware codesign. Reconfigurable hardware. Hardware description languages. Intellectual property-based design. Design reuse.

2. Thermal Issues in Microelectronics

Thermal and electro-thermal modelling, simulation methods and tools. Thermal mapping. Thermal protection circuits.

3. Analysis and Modelling of ICs and Microsystems

Simulation methods and algorithms. Behavioural modelling with VHDL-AMS and other advanced modelling languages. Microsystems modelling. Model reduction. Parameter identification.

4. Microelectronics Technology and Packaging

New microelectronic technologies. Packaging. Sensors and actuators.

5. Testing and Reliability

Design for testability and manufacturability. Measurement instruments and techniques.

6. Power Electronics

Design, manufacturing and simulation of power semiconductor devices. Hybrid and monolithic Smart Power circuits. Power integration.

7. Signal Processing

Digital and analogue filters, telecommunication circuits. Neural networks. Fuzzy logic. Low voltage and low power solutions.

8. Embedded Systems

Design, verification and applications.

9. Medical Applications

Medical and biotechnology applications. Biometrics. Thermography in medicine.10. Artificial Intelligence in Electronic SystemsAI-driven design. AI-driven signal and data processing. Edge AI.

Tutorials and Special Sessions Call for Proposals

Several tutorials/special sessions will be held prior to the conference. Authors willing to propose a tutorial at MIXDES 2026 are invited to send a proposal to the Organizing Committee. The proposal should consist of a three-page summary including tutorial title, name and affiliation of the lecturer(s), tutorial objectives and audience, topical outline and provisional schedule of the tutorial.

Enquiries:
Mariusz Orlikowski (Conference Secretary) e-mail: mixdes2026@dmcs.p.lodz.pl

Lodz University of Technology
Department of Microelectronics and Computer Science (K-22)
ul. Wólczańska 221 (building B18)

93-005 Łódź, Poland

tel.: +48 604397239
fax: +48 426360327

[chapter] Compact/SPICE Modeling

Wladek Grabinski and Daniel Tomaszewski

Compact/SPICE Modeling

In: Rudan, M., Brunetti, R., Reggiani, S. (eds) 

Springer Handbook of Semiconductor Devices

DOI 10.1007/978-3-030-79827-7_34

Abstract: The microelectronics and nano-electronics industry strongly relies on compact models to reduce a new microelectronic product development costs. The goals of this review are to highlight critical issues for the development of compact models for microelectronics and nano-electronics. In this chapter, we’ve covered the main principles of the compact device modeling. Also discussed are the possibilities of integrating compact models into circuit simulation and design tools, with an emphasis on the Verilog-A standardization, which simplify model implementation into EDA tool.

 

[paper] dual metal InAs-GaSb VTFETs

M. Saravanan, Eswaran Parthasarathy, Shiromani Balmukund Rahi and Ramkumar Natarajan

Impact of drain and source engineering on dual metal InAs-GaSb VTFETs
with high-K gate stack design

Sci Rep 15, 44796 (2025) DOI: 10.1038/s41598-025-28448-x

Department of Electronics and Communication Engineering, Sri Eshwar College of Engineering, Coimbatore, 641202, India
Department of Electronics and Communication Engineering, SRM Institute of Science and Technology, Kattankulathur, 603203, India
University School of Information and Communication Technology, Gautam Buddha University, Greater Noida, 201312, Uttar Pradesh, India
Department of Electronics and Communication Engineering, SR University, Warangal, 506371, Telangana, India

Abstract: The performance of a Dual-Metal-InAs-GaSb Vertical Tunnel Field Effect Transistor (DM-InAs-GaSb VTFET) with an InAs source pocket was investigated in relation to the gate dielectric materials. This research chose gate dielectric materials such as SiO2, Al2O3, HfO2, and ZrO2. The simulation is performed using the Silvaco Technology Computer-Aided Design (TCAD) software. The drain current (ION) of the DM-InAs-GaSb VTFET, which includes an InAs source pocket and an extended drain, is assessed across several dielectric materials; still, ZrO2 (7.92 × 10− 5 A/µm) and HfO2 (8.15 × 10− 5 A/µm) demonstrate enhanced performance. The transconductance (gm) values were 606 µS/µm for HfO2 and 589 µS/µm for ZrO2. A comparison is performed between the Ge-Si VTFET and the suggested configuration. The proposed DM-InAs-GaSb VTFET demonstrates a 1.5-times increase in ON current (ION) and a three-time boost in transconductance (gm). The frequency response of the proposed device was evaluated by employing its SPICE characteristics to construct the common source amplifier in the SPICE circuit simulator. This amplifier comparison reveals that ZrO2 and HfO2 insulators provide significant gain, with HfO2 displaying a cut-off frequency of 1.808 GHz.

FIG: Cross-sectional schematic (a) DM-InAs-GaSb VTFET with split drain (Device-A),
(b) DM-InAs-GaSb VTFET with reduced channel (Device-B),
(c) DM-InAs-GaSb VTFET with drain extension (Device-C).

Acknowledgements: The authors acknowledge the SRM Institute of Science and Technology, Kattankulathur, Chennai, India for providing the support and facility to carry out this research work.