Feb 15, 2026

[paper] From RTL to Prompt Coding Chip Design

Lukas Krupp∗, Matthew Venn† and Norbert Wehn∗
From RTL to Prompt Coding: Empowering the Next Generation of Chip Designers through LLMs
arXiv:2601.13815v1 [cs.AR] 20 Jan 2026

∗RPTU University of Kaiserslautern-Landau, Kaiserslautern, Germany
†Tiny Tapeout

Abstract: This paper presents an LLM-based learning platform for chip design education, aiming to make chip design accessible to beginners without overwhelming them with technical complexity. It represents the first educational platform that assists learners holistically across both frontend and backend design. The proposed approach integrates an LLM-based chat agent into a browser-based workflow built upon the Tiny Tapeout ecosystem. The workflow guides users from an initial design idea through RTL code generation to a tapeout-ready chip. To evaluate the concept, a case study was conducted with 18 high-school students. Within a 90-minute session they developed eight functional VGA chip designs in a 130 nm technology. Despite having no prior experience in chip design, all groups successfully implemented tapeout-ready projects. The results demonstrate the feasibility and educational impact of LLM-assisted chip design, highlighting its potential to attract and inspire early learners and significantly broaden the target audience for the field.

Fig: Overview of the proposed idea-to-GDSII learning workflow integrating the LLM-based chat agent for the RTL implementation, VGA simulation tool, and GitHub-driven backend flow.

Acknowledgments: This paper was funded by the German Federal Ministry of Research, Technology and Space (BMFTR) as part of the “Chipdesign Germany” project under grant number 16ME0890.

Feb 12, 2026

ChipFoundry Webinar Recording: New CLI, OpenFrame & Production


Feb 11, 2026

[C4P] ESSERC 2026


ESSERC 2026 PAPERS SUBMISSION DEADLINE 
APRIL 3, 2026

Papers submitted for ESSERC 2026 review must clearly state:
  • The purpose of the work
  • How and to what extent it advances the state-of-the art
  • Specific results and their impact.
Only work that has not been previously published or submitted elsewhere will be considered. Submission of a paper for review and subsequent acceptance is considered as a commitment that the work will not be publicly available prior to the conference. Measurement results or calibration against measured data is required to support the claims of the submitted paper.

ESSERC 2026 Conference Tracks 
  1. Advanced Technology, Process and Materials
  2. Analog, Power and RF Devices
  3. Modelling and Simulation of Electron Devices
  4. Analog Circuits
  5. Data Converters
  6. RF & mm‑Wave Circuits
  7. Frequency Generation Circuits
  8. Digital Circuits & Systems
  9. Power Management
  10. Wireless Systems
  11. Wireline and Optical Circuits and Systems
  12. Emerging Computing Devices and Circuits
  13. Architectures and Circuits for AI and ML
  14. Devices & Circuits for Sensors, Imagers and Displays
After selection of papers, the authors will be informed about the decision of the Technical Program Committee by e-mail by May 27, 2026.

At the same time, the complete program will be published on the conference website. An oral presentation will be given at the Conference for each accepted paper. No-shows will result in the exclusion of the papers from any conference related publication. The submitted final PDF files must be IEEE Xplore compliant.

Best Paper Award: Papers presented at the conference will be considered for the “Best Paper Award” and “Best Young Scientist Paper Award”. The selection will be based on the results of the paper selection process and the judgment of the conference participants. The award delivery will take place during ESSERC 2027.

For each paper independently, at least one (co-)author is required to register for the conference (one registration one paper policy). Registration fees and deadlines will be available on the conference website.

 

Feb 10, 2026

Open Silicon microelectronic bootcamp

Call for leaders to organize an Open Silicon microelectronic bootcamp
Bring Chip Design to Your Community!

Join the global Open Silicon movement and gain hands-on experience in chip design and fabrication. Our Q1 2026 bootcamps provide access, mentoring, and real silicon opportunities for students, educators, and innovators.

The IEEE is seeking passionate leaders from around the world to organize microelectronics design bootcamps in their local communities, under the IEEE division 1 OPEN SILICON initiative.
If you organize a bootcamp between February and May 2026, IEEE will sponsor the fabrication of three of your designs. You'll receive your fabricated chips (tape-out) mounted on a development board for testing and hands-on exploration.

Selected bootcamp leaders will be invited to an online training session with Matt Venn (Tiny Tapeout) during the last week of February.

To be considered, please provide the following information at REGISTRATION FORM

Key Dates:
  • Bootcamp Leader Registration Deadline: Sunday, February 22nd, 2026
  • Leader Training Session: Last week of February (TBD)
  • Bootcamp Period: March–May 2026
  • Tapeout Submission Deadline: March 23rd, 2026 / May 1st, 2026
  • Development Board Shipping: September 2026 / November 2026




Feb 9, 2026

ICMC 2026: Paper Deadline Extended!

Submission Deadline Extended
IMPORTANT DATES
February 16, 2026:   Extended Submission Deadline
April 6, 2026:   Acceptance Notification
May 10, 2026:   Final Version for Publication
 
This year, the  International Compact Modeling Conference (ICMC)  especially encourages submissions in the following domains:
  • Electrostatic Discharge (ESD) modeling for protection design
  • Reliability and aging-aware compact models and simulation techniques
  • AI or Machine Learning for model development, parameter extraction, circuit simulation efficiency, etc.
We are also seeking submissions in the following domains:
  • Application of Device Models
  • Device Model Development
  • Model Enhancements and Implementations
  • Emerging Devices
 
 
 
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