IEEE EDS/SSCS/CAS Mini-Colloquium

Friday 11 September 2026

UIB; Sa Riera Building

C/ de Miquel dels Sants Oliver, 2

07122 Palma

Professors Benjamin Iniguez, URV and Rodrigo Picos, UIB, have organize joint IEEE EDS/SSCS/CAS Mini-Colloquium as an integral part of the recent ESSERC2026 in Palma de Mallorca. All the MQ participants followed the MQ program as follows:

Mini-Colloquium Agenda

9:00 - 09:05 Opening

9:05-9:15 Tribute to Michael S. Shur

9:05-9:15 Tribute to José Epifânio da Franca 

9:15-10:05 Leveraging semiconductor technology for the benefit of society

Fernando Guarin (Director of IEEE Division I)

10:05-10:55 Power efficient WBG devices for the green transition

Mikael Ostling (KTH, SE)

10:55-11:25 Coffee Break

11:25-12:15 Holistic solutions to future computing - not only scaling

Francesca Iacopi (Purdue University, US)

12:15-13:05 Status of the Compact modeling and its Verilog-A standardization

Wladek Grabinski (MOS-AK, CH and IHP OpenPDK, DE)

13:05-14:25 Lunch

14:25-15:15 Graphene thin film technology for neural interfaces

José Antonio Garrido (ICN2, Barcelona, Spain)

15:15-16:05 Energy-Efficient Analog IC Design:

Exploring Solutions at Device, Circuit and System Levels

Antonio López (Public University of Navarra, Spain)

[paper] TCAD Modeling of SB Diode

Pedro Paulo Pessoa Oliveira1,2, Andreas Mai1,3, Norbert Herfurth1, 

and Davies William de Lima Monteiro2

TCAD Modeling of Schottky-Diode in an open-source SiGe BiCMOS technology

In 2026 40th Symposium on Microelectronics Technology and Devices 

SBMicro, pp. 1-4. IEEE, 2026

DOI: 10.1109/SBMicro70495.2026.11684441

1. IHP, Frankfurt (Oder), Germany
2. Department of Electrical Engineering, UFMG - Belo Horizonte-MG, Brazil
3. University of Applied Sciences Wildau, Germany

Abstract: Accurate simulation of Schottky barrier diodes (SBDs) is challenging because standard idealized models fail to capture non-ideal interface physics, such as Fermi-level pinning and image-force lowering. This paper presents an enhanced Technology Computer-Aided Design (TCAD) methodology to model an SBD from the IHP SG13G2 130-nm open-source SiGe BiCMOS technology. To overcome limitations of conventional simulations that often rely on oversimplified assumptions and empirical fitting, this work explicitly incorporates interface en- ergy states into the simulation, specifically modeling the fun- damental pinning mechanisms driven by Metal-Induced Gap States (MIGS). By calibrating the TiSi2/Si interface using the theoretical slope parameter, a value of 0.503 V was determined for the zero-bias barrier height. The resulting physics-based model captures the true rectifying nature of the contact and accurately reproduces the electrical characteristics targeted by the empirical model, achieving a nominal forward voltage drop of 0.39 V and a realistic reverse leakage current of 29.3 nA at -2.5 V. Ultimately, this paper shows the innovation and education gain of open- source foundry data by showcasing an open innovation path for a targeted near-industry device development flow.

FIG: a.) Energy band diagram of the Schottky diode at V=0V. Thecoordinate x = 0 corresponds to the TiSi2/n-Si Schottky interface. The inset displays the 2D device schematic, with the solid black line indicating the multi-segment cut-path used to extract the energy levels across the anode, n-buried layer and n-well RT to cathode contact. b.) Comparison of the simulated DC current-voltage (IV) characteristics between the proposed TCAD model and the standard SPICE macromodel.

Acknowledgment: The authors thank IHP for the open-source PDK and the collaborative research. They also thank Universidade Federal de Minas Gerais (UFMG) and the Brazilian Microelectronics Society (SBMicro) for supporting this work. Finally, gratitude is extended to S. Srivastava and B. Sake for their valuable guidance.

[NanoIC] Workshop

NanoIC Pilot Line Workshop

Next logic, memory, and chiplet technologies to enable future system innovation

October 1, 2026; Sede Turismo Andaluz; 40 Compañía Str. Málaga, Spain

Workshop Agenda

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10:00 - 10:10 Welcome
10:10 - 10:30 Marie Garcia Bardon 

Short Introduction to EU Chips Act NanoIC Pilot Line

10:30 - 11:30 Nicolas Pantano 

Enabling Chiplet Architectures Through Advanced Packaging And High-Density Interconnects

11:30 - 12:00 Coffee break
12:00 - 13:00 Fernando García Redondo 

Opportunities in memory scaling: design-technology co-optimization for SRAM and emerging memories

13:00 - 14:00 Marie Garcia Bardon 

Advanced Logic Scaling: Technologies for the sub-2nm

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Free Registration Online Workshop  

               https://u.uma.es/icc/workshop

[ChipFoundry] December Shuttle: Commitment deadline moved to November 4th

ChipFoundry Team has an important update regarding our upcoming December shuttle. The commitment deadline has been moved to November 4th. We want to remind you that this is not the final design submission date. Here is what you need to know to confirm your space: A 50% payment of your total is required by November 4th to hold your reservation. Your final design files are still due on December 7th. The tapeout submission date has not changed. You only need to provide your user project wrapper, and we will handle the integration through our tapeout flow. Our team is available if you have any questions about the submission process or need help with your invoice. Reserve Now We look forward to confirming your commitment and working with you on your December tapeout!   Best regards,   The ChipFoundry Team ­ ­

[paper] EKV compact modeling for oxide CTFTs

Mingyu Zhuang, Zhiyuan Wang, Baochuan Liu, Jiawei Zhang, Qian Xin, Aimin Song

Neural-network-assisted EKV compact modeling for complementary oxide thin-film transistors

Appl. Phys. Lett. 129, 123504 (2026)

DOI: 10.1063/5.0349365

1. Shandong Technology Center of Nanodevices and Integration, Uni. Shandong (CN)
2. Department of Electrical and Electronic Engineering, Uni. Manchester (UK)
3. Southern University of Science and Technology, Shenzhen (CN)

ABSTRACT: This work reports a neural-network-assisted Enz–Krummenacher–Vittoz (EKV) compact-modeling framework for complementary oxidethin-film transistors (TFTs). The neural network is used as a bias-dependent effective-parameter generator for the equivalent mobility and onset voltage, while the drain current is calculated by the analytical EKV current core. This strategy represents defect-, contact-, and bias-dependent nonidealities of oxide TFTs through effective quantities without replacing the current equation with a black-box neural-networkpredictor. The model is validated using both n-type indium–gallium–zinc oxide TFTs and p-type tin monoxide (SnO) TFTs, achieving mean absolute percentage errors of 0.56% and 0.36%, respectively. The learned effective parameters further provide an EKV-constrained compact representation of bias-dependent transport capability and channel-onset behavior obtained from global fitting of the measuredoutput-characteristic dataset, rather than serving as directly extracted material parameters. The trained model is translated into aPSpice-compatible library and applied to complementary inverter simulation, showing good agreement with measured voltage-transfer characteristics and reproducing the main transient response characteristics. These results demonstrate an accurate, analytically structured, and Simulation Program with Integrated Circuit Emphasis-compatible compact-modeling strategy that links bias-dependent oxide-TFTtransport to circuit-level simulation. 

FIG. (a) Equivalent parasitic‑capacitance and measurement‑loading network used in the transient simulation of the complementary SnO/IGZO inverter. (b) Simulated output waveforms for different values of the additional external capacitance.

Selected References:

[24] C. C. Enz, F. Krummenacher, and E. A. Vittoz, “An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications,” Analog Integr. Circuits Signal Process. 8, 83–114 (1995)

DOI: 10.1007/BF01239381

[25] J.-M. Sallese et al, “Inversion charge linearization in MOSFET modeling and rigorous derivation of the EKV compact model,” Solid-State Electron. 47, 677–683 (2003) 

DOI: 10.1016/S0038-1101(02)00336-2

[26] W. Grabinski et al, “FOSS EKV 2.6 parameter extractor,” in Proceedings of the 22nd International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES) (IEEE, 2015), pp. 181–186

DOI: 10.1109/MIXDES.2015.7208507