[C4P] EDTM 2027 Fukuoka, Japan

11th IEEE Electron Devices Technology and Manufacturing (EDTM) Conference

Theme: “Empowering the AI Era: 

The Role of Innovation in Semiconductor Devices and Manufacturing”

March 8–11, 2027 Fukuoka, Japan

https://attend.ieee.org/edtm-2027/

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General Information Important Dates Paper submission deadline: October 15, 2026 Notification of acceptance: Late December 2026 Conference Overview The 11th EDTM conference is a four-day meeting fully sponsored by the IEEE Electron Devices Society (EDS). It serves as a forum for the electron devices community to collaborate on devices, materials, tools, and innovative technologies across the semiconductor ecosystem. Technical Areas Materials Processes, Tools, Yield, and Manufacturing Advanced Logic Devices Memory Technologies Photonics, Imaging and Display Power, RF, and Energy Devices Modeling and Simulation Reliability and Testing Packaging and Heterogeneous Integration Sensors, MEMS, BioElectronics Flexible and Wearable Electronics Nanotechnologies Disruptive Technologies Oral and Poster Sessions EDTM 2027 will feature parallel oral and poster technical sessions. Best Paper, Best Student Paper, and Best Poster Awards will be selected. Publications Accepted and presented papers will be published in the EDTM 2027 Proceedings (IEEE Xplore). Selected high-impact papers may be invited to submit extended versions to J-EDS. Short Courses & Tutorials Held on March 8, 2027. Tutorials cover fundamentals to state of‑the‑art; short courses focus on advanced topics aligned with the conference theme. Exhibition Vendors will showcase new products and technologies, enabling attendees to learn about tools and techniques supporting their work. Secretariat PCO, Inc. <edtm2027@pcojapan.jp>

EDTM 2027 Committees General Chair Masumi Saitoh (Kioxia) TPC Chair Kensuke Ota (Sony Semiconductor Solutions) Steering Committee Shuji Ikeda (Chair, tei Solutions) Masumi Saitoh (Kioxia) Arokia Nathan (Uni. Cambridge) Bin Zhao (Iotelligent) Ravi M. Tody (Synopsys) John Dallesasse (UIUC) Murty Polararapu (Space Electronics Solutions) Meikei Ieong (Simbury Limited) Subramaniam Iyer (UCLA) P. Susthitha Menon (UKM) Chen Yang (Analog Devices) Merlyne de Souza (Univ. of Sheffield) Bernard Lim (Appscard) Yang Chai (Poly Univ.) Yogesh Chauhan (IIT Kanpur) Changrock Song (SK Hynix) Kazunari Ishimaru (Rapidus) Hitoshi Wakabayashi (Science Tokyo) Executive Committee Shuji Ikeda (tei Solutions) Hitoshi Wakabayashi (Science Tokyo) Kazunari Ishimaru (Rapidus) Masumi Saitoh (Kioxia) Chen Jiang (Tsinghua University) Kensuke Ota (Sony Semiconductor Solutions) Yuichiro Ando (Osaka Metropolitan Univ.) Kimihiko Kato (AIST) Kazuaki Iwasawa (TEL) Shoichi Kabuyanagi (Kioxia) Tadashi Yamaguchi (Renesas) Takuya Maeda (Univ. Tokyo) Bich-Yen Nguyen (Soitec) Phuc Le Hoang (VSAP Lab)

[program] ICMC2026

INTERNATIONAL COMPACT MODELING CONFERENCE PROGRAM

2026.si2-icmc.org

The 2026 conference continues under the theme “Enhancing Collaboration in Modeling with the Semiconductor Industry.” This year, ICMC especially encourages contributions in several timely and important areas, including electrostatic discharge (ESD) modeling for protection design, reliability and aging-aware compact models and simulation techniques, and the use of AI or machine learning for model development, parameter extraction, and circuit simulation efficiency. The conference also covers a broad range of topics in compact modeling, including the application of device models, device model development, model enhancements and implementations, and emerging devices.

This year’s technical program includes 3 keynote speakers, 7 invited speakers, 28 technical talks, 12 posters and a panel session. The program reflects both the depth and diversity of current modeling research and practice, ranging from model calibration and validation methodologies to reliability, RF, high-voltage, cryogenic, and emerging device applications.

Program at a Glance

Speaker	Title
	Keynote Presentations
Chenming Hu	BSIM, FinFET, and Open Innovation
Yuan Taur	Physical Insights Beyond the Textbook Modeling of MOSFETs and pn-junctions
Elyse Rosenbaum	Measurement Challenges Impeding the Verification of ESD Compact Model Accuracy and Generalizability
	Invited Presentations
James Victory	Modeling and Simulation Challenges in Modern Power Discrete Semiconductor Technologies
Gilson Wirth	Modeling of Low-Frequency Noise and BTI in Electron Devices
Chien-Ting Tung	Application of AI and ML in the Compact Modeling Domain
Michael Stockinger	On-Chip ESD Protection Design Optimization Using ESD Device Compact Models
Darsen Lu	Ferroelectric Memory Devices Compact Modeling and Applications
Meng-Lin Lu	Applications of Machine Learning Techniques in the Compact Modeling Platform
Lorenzo Peri	Compact Quantum Dot Models for Hybrid Microwave Circuits and Quantum Information Processing

Program Grid – Friday, July 30

Time	Session
8:30 - 8:45	Day 1 Welcome (Queens Salon)
8:45 - 9:25	[Keynote] BSIM, FinFET, and Open Innovation by Prof. Chenming Hu
9:25 - 10:25	Advances in Compact Modeling (Queens Salon)
10:25 - 10:45	Coffee Break (Royal Salon & Kings View Room)
10:45 - 12:10	Ferroelectric and other Nonvolatile Memories (Queens Salon)
12:10 - 13:20	Lunch Served (Royal Salon & Kings View Room)
13:20 - 14:00	[Keynote] Physical Insights Beyond the Textbook Modeling of MOSFETs and p-n Junctions by Prof. Yuan Taur
14:00 - 15:05	Emerging Devices and Technologies (Queens Salon)
15:05 - 15:25	Coffee Break (Royal Salon & Kings View Room)
15:25 - 16:30	Wide Bandgap Material Device Models (Queens Salon)
16:30 - 17:00	Poster Introductions (Queens Salon)
17:00	Poster Session & Reception (Verandah Grill/Deck)

Program Grid – Friday, July 31

Time	Session
8:30 - 8:40	Day 2 Welcome (Queens Salon)
8:40 - 9:20	[Keynote] Measurement Challenges Impeding the Verification of ESD Compact Model Accuracy and Generalizability by Prof. Elyse Rosenbaum
9:20 - 10:05	ESD Protections Modeling (Queens Salon)
10:05 - 10:25	Coffee Break (Royal Salon & Kings View Room)
10:25 - 11:55	Machine Learning and Artificial Intelligence in Compact Modeling (Queens Salon)
11:55 - 12:55	Lunch Served (Royal Salon & Kings View Room)
12:55 - 13:55	Panel Session: Machine Learning for Compact Modeling – Promises, Pitfalls, and Paths to Industry Adoption
13:55 - 14:40	Modeling of Noise and Traps (Queens Salon)
14:40 - 15:00	Coffee Break (Royal Salon & Kings View Room)
15:00 - 16:20	Devices at Cryogenic Temperatures (Queens Salon)
16:20 - 17:00	Closing Ceremony & Awards (Queens Salon)

Open Circuit Design: Chipalooza Challenge

Chipalooza Challenge

Tim Edwards: Open Source Silicon Advocate 

Calling on all analog designers!

What is Chipalooza Challenge?

The goal of Chipalooza Challenge is to provide open source libraries of high-quality analog components useful to designers of SoCs for all three major open source PDKS (Sky130, GF180MCU, and IHP SG13CMOS5L), enabling cross-platform porting of SoCs as well as providing a wealth of information for analog designers.

Chipalooza Challenge started under Efabless in 2024, resulting in dozens of analog circuits for Sky130 that were placed on two test chips and now exist in GitHub repositories. The new challenge aims to do the same for GF180MCU and IHP SG13CMOS5L, as well as create a place where designers can go to find the open source IP that they need.

There will be five separate challenges across two years (2026 to 2028), so that there are two challenges for each of the three open KS counting the original Efabless challenge as the first for Sky130). They will be spaced apart by about 3 months each, with overlapping schedules.

How do I get involved?
Keep up with posts on https://fossi-chat.org/#chipalooza. Follow the schedule, join challenge meetings, and send in your analog IP proposal to Open Circuit Design by the posted due date.

When does it start?
Due to limited time before the next HP run, the first challeng has already started! 

Proposals are due July 27. 

However, for the first challenge there will be a 2-week grace period. But the shuttle schedule is fixed, so any delay cuts the design time, so try to get proposals in as early as you can!

What does it cost?
The Chipalooza Challenge is paid for and will pay the designers for good designs. The funding source will be announced when the first funds arrive. The schedule of awards will be posted soon.

ICMC is Almost Here! Don't Forget to Register!

Register for ICMC 2026 Join the global compact modeling community this July at the International Compact Modeling Conference (ICMC 2026), taking place July 30–31, 2026, aboard the historic Queen Mary in Long Beach, California. ICMC brings together leaders in compact modeling, process technology, circuit design, and device development for two days of technical exchange, collaboration, and discussion around the future of semiconductor modeling and simulation. By attending ICMC 2026, participants will have the opportunity to: • Engage in discussions shaping the evolution of compact models • Learn from leading academic researchers and industry experts • Explore technical sessions focused on real-world applications and emerging technologies • Connect with peers across academia, foundries, EDA, and device engineering • Participate in poster sessions, networking opportunities, and collaborative discussions Hosted aboard the iconic Queen Mary in Long Beach, attendees will experience a venue unlike any other conference setting. Once a renowned transatlantic ocean liner and historic World War II troopship, the Queen Mary now serves as a floating hotel and event destination rich in history, architecture, and atmosphere. With one month remaining, now is the time to finalize your plans and join the conversations advancing compact modeling technologies and applications. We look forward to welcoming you to Long Beach! Register Now 2026 Panel Session Friday, July 31, 2026 | 12:55-13:55 How can machine learning help advance compact modeling, and what challenges still stand in the way of broader industry adoption? Join the panel session "Machine Learning for Compact Modeling: Promises, Pitfalls, and Paths to Industry Adoption" at the International Compact Modeling Conference (ICMC) 2026. 👥 Panelists: Chien-Ting Tung, Synopsys Inc. Kiran Gullapalli, NXP Semiconductors Hyunbo Cho, Alsemy Inc. Gajanan Dessai, Analog Devices 🎤 Moderator: Girish Pahwa, NYCU Taiwan 📅 July 31, 2026 | 12:55–13:55 📍 Queens Salon Be part of the discussion as experts explore opportunities, limitations, and practical considerations for integrating machine learning into compact modeling workflows. Learn More Conference Sponsors Media Sponsors Industry Sponsors LinkedIn Website Copyright © 2026 Conference Catalysts, LLC, All rights reserved.

[mos-ak] [early registration] 23rd MOS-AK/ESSERC Workshop in Palma de Mallorca (SP) Sept. 7, 2026

Arbeitskreis Modellierung von Systemen und Parameterextraktion

Modeling of Systems and Parameter Extraction Working Group

MOS-AK FOSS OpenPDK Workshop
ESSERC, Palma de Mallorca, (SP) Sept. 7 2026

Please note that that the Early ESSERC registration is open until FRIDAY July 17, 2026 (23:59 CEST)
then Late runs from SATURDAY July 18, 2026 (00:00 CEST) to FRIDAY August 28, 2026 (23:59 CEST)

MOS‑AK workshop connects compact‑modeling experts and strengthens the OpenPDK‑based IC design platform, creating a shared space for SPICE/Verilog‑A standardization and technical feedback. These activities directly support and advance the new European ODE4EC‑AMS project by improving understanding of modern device models used in FOSS CAD/EDA simulation and OpenPDK analog/RF IC design workflows. The MOS-AK workshop program is available online as well as with the direct link:

<https://www.mos-ak.org/palma_2026/>

Our MOS-AK workshop will be followed by complementary FAMES Pilot Line W2 Workshop presenting in-depth technical results of the 10nm and 7nm FD-SOI nodes developments, combined with NVM memories, RF, smart PMIC and 3D integration options, as a pathway to deliver high-performance, low-power consumption solutions for future chips.

W.Grabinski for Extended MOS-AK Committee

WG130726

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