Papers for curious people... (may 25th 2011)

CMOS Silicon Physical Unclonable Functions Based on Intrinsic Process Variability

Stanzione, S.  Puntin, D.  Iannaccone, G. 
Page(s): 1456 - 1463
Digital Object Identifier : 10.1109/JSSC.2011.2120650

AbstractPlus | Full Text: PDF (1209KB)

This paper presents an extreme-low-power mixed-signal CMOS integrated circuit for product identification and anti-counterfeiting, which implements a physical unclonable function operating with a challenge-response scheme. We devise a series of circuits and algorithmic solutions based on the use of a process monitor and on the prediction of the erratic response bits which allow to suppress the effects of temperature, voltage supply and process variations in order to obtain a robust and reliable b... Read More »


 

A Supply-Rail-Coupled eTextiles Transceiver for Body-Area Networks

Mercier, P. P.  Chandrakasan, A. P. 
Page(s): 1284 - 1295
Digital Object Identifier : 10.1109/JSSC.2011.2120690

AbstractPlus | Full Text: PDF (1915KB)

This paper presents a transceiver that communicates over electronic textiles as an alternative, energy-efficient communication medium for body-area network (BAN) applications. The proposed eTextiles network architecture consists of a two-wire conductive yarn medium, body-worn nodes, and a basestation used for data collection and medium-access control. Fabricated in 0.18 $mu$m CMOS technology, the eTextiles transceiver employs supp... Read More »

Statistical Modeling and Simulation of Threshold Variation Under Random Dopant Fluctuations and Line-Edge Roughness

Ye, Y.  Liu, F.  Chen, M.  Nassif, S.  Cao, Y. 
Page(s): 987 - 996
Digital Object Identifier : 10.1109/TVLSI.2010.2043694

Abstract | Full Text: PDF (1332KB)

The threshold voltage $({V}_{rm th})$ of a nanoscale transistor is severely affected by random dopant fluctuations and line-edge roughness. The analysis of these effects usually requires atomistic simulations which are too expensive in computation for statistical design. In this work, we develop an efficient SPICE simulation method and statistical variation model that accurately predict threshold variation as a function of dopant ... Read More »

On Functional Broadside Tests With Functional Propagation Conditions

Pomeranz, I.  Reddy, S. M. 
Page(s): 1094 - 1098
Digital Object Identifier : 10.1109/TVLSI.2010.2043695

AbstractPlus | Full Text: PDF (197KB)

Functional broadside tests were defined as broadside tests where the scan-in state is a reachable state. This ensures that during the functional capture cycles of the test, the circuit visits states that it can also visit during functional operation. As a result, it avoids overtesting that may occur with unreachable states. However, the scan-out operation at the end of a functional broadside test allows the observation of any fault effects that reached the state variables at the end of the secon... Read More »

 

Broadside and Functional Broadside Tests for Partial-Scan Circuits

Pomeranz, I.  Reddy, S. M. 
Page(s): 1104 - 1108
Digital Object Identifier : 10.1109/TVLSI.2010.2044049

AbstractPlus | Full Text: PDF (176KB)

Functional broadside tests were defined to address overtesting that may occur due to the detection of delay faults under nonfunctional operation conditions. Such conditions are made possible by scanning in unreachable states. Functional broadside tests were defined and studied in the context of full-scan circuits. In this work, we study the definition of broadside and functional broadside tests in partial-scan circuits. A unique property we show is that if the unscanned state variables are obser... Read More »

Papers in IEEE TED, vol 58, issue 6 (june 2011)

An Efficient Robust Algorithm for the Surface-Potential Calculation of Independent DG MOSFET

Jandhyala, S.  Mahapatra, S. 
Page(s): 1663 - 1671
Digital Object Identifier : 10.1109/TED.2011.2131654

Although the recently proposed single-implicit-equation-based input voltage equations (IVEs) for the independent double-gate (IDG) MOSFET promise faster computation time than the earlier proposed coupled-equations-based IVEs, it is not clear how those equations could be solved inside a circuit simulator as the conventional Newton–Raphson (NR)-based root finding method will not always converge due to the presence of discontinuity at the G-zero point (GZP) and nonremovable singularities in ... Read More »

Statistical Model of Line-Edge and Line-Width Roughness for Device Variability Analysis

Hiraiwa, A.  Nishida, A.  Mogami, T. 
Page(s): 1672 - 1680
Digital Object Identifier : 10.1109/TED.2011.2131144

The authors propose a model of line-edge and line-width roughness (LER and LWR) of actual device patterns, which received some smoothing steps, for accurate estimation of device variability. The model assumes that LER/LWR has originally an exponential autocorrelation function (ACF) and is smoothed using another exponential function. The power spectrum of this ACF almost completely fits the experimental one of polycrystalline silicon lines, which were formed using plasma etching. The authors inve... Read More »

A Physics-Based Analytical Compact Model for the Drift Region of the HV-MOSFET

Bazigos, A.  Krummenacher, F.  Sallese, J.-M.  Bucher, M.  Seebacher, E.  Posch, W.  Moln??r, K.  Tang, M. 
Page(s): 1710 - 1721
Digital Object Identifier : 10.1109/TED.2011.2119487

This paper presents a novel physics-based analytical compact model for the drift region of a high-voltage metal–oxide–semiconductor field-effect transistor (HV-MOSFET). According to this model, the drift region is considered as a simple 1-D problem, just as that of a low-voltage inner MOS transistor. It exploits the charge-sheet approximation and performs linearization between the charge in the drift region and the surface potential. The drift region model combined with the standar... Read More »

Papers in IEEE EDL, vol 32, issue 6 (may 2011)

Modeling of Current-Return-Path Effect on Single-Ended Inductor in Millimeter-Wave Regime

Wang, H.  Zhang, L.  Yang, D.  Zeng, D.  Wang, Y.  Yu, Z. 
Page(s): 737 - 739
Digital Object Identifier : 10.1109/LED.2011.2136312

The effect of current return path (CRP) on the accurate modeling of single-ended inductors in the millimeter-wave regime has been investigated. A series of spiral inductors with different sizes, shapes, and CRP positions was fabricated in a 0.18-$muhbox{m}$ RF-CMOS process and measured up to 50 GHz. An analytical appended model for CRP is developed to characterize the effect, and its equivalent circuit is validated by measurement ... Read More »

Simple Analytical Bulk Current Model for Long-Channel Double-Gate Junctionless Transistors

Duarte, J. P.  Choi, S.-J.  Moon, D.-I.  Choi, Y.-K. 
Page(s): 704 - 706
Digital Object Identifier : 10.1109/LED.2011.2127441

A bulk current model is formulated for long-channel double-gate junctionless (DGJL) transistors. Using a depletion approximation, an analytical expression is derived from the Poisson equation to find channel potential, which expresses the dependence of depletion width under an applied gate voltage. The depletion width equation is further simplified by the unique characteristic of junctionless transistors, i.e., a high channel doping concentration. From the depletion width formula, the bulk curre... Read More »

Modeling and Separate Extraction of Gate-Bias- and Channel-Length-Dependent Intrinsic and Extrinsic Source–Drain Resistances in MOSFETs

Bae, H.  Jang, J.  Shin, J. S.  Yun, D.  Lee, J.  Kim, T. W.  Kim, D. H.  Kim, D. M. 
Page(s): 722 - 724
Digital Object Identifier : 10.1109/LED.2011.2131116

A new technique for a separate extraction of the current-path-dependent resistance $(R_{{rm SD}0})$ from the contact-dependent source and drain resistances $(R_{rm Se} hbox{and} R_{rm De})$ is reported for a single MOSFET. We also report a technique for a separation of $V_{rm GS}$ -dependent source an... Read More »

Extraction of Separated Source and Drain Resistances in Amorphous Indium–Gallium–Zinc Oxide TFTs Through – Characterization

Bae, H.  Kim, S.  Bae, M.  Shin, J. S.  Kong, D.  Jung, H.  Jang, J.  Lee, J.  Kim, D. H.  Kim, D. M. 
Page(s): 761 - 763
Digital Object Identifier : 10.1109/LED.2011.2127438

Considering asymmetry caused by layout, process, and device degradation, separate extraction of the source and drain resistances, i.e., $R_{S}$ and $R_{D}$, respectively, from the total resistance $R_{rm TOT}$ is very important in the design, modeling, and characterization of amorphous indium–g... Read More »

Mechanism Analysis of Off-Leakage Current in an LDD Poly-Si TFT Using Activation Energy

Nakashima, A.  Kimura, M. 
Page(s): 764 - 766
Digital Object Identifier : 10.1109/LED.2011.2132112

We have analyzed the mechanism of off-leakage current in an lightly doped drain (LDD) poly-Si thin-film transistor by investigating the activation energy $E_{a}$. It is found that $E_{a}$ decreases as the gate and drain voltages increase. We have also discussed the mechanism using a device simulator. It is found that a hole channel is lightly formed in the LDD regio... Read More »

Evidence of a Novel Source of Random Telegraph Signal in CMOS Image Sensors

Goiffon, V.  Magnan, P.  Martin-Gonthier, P.  Virmontois, C.  Gaillardin, M. 
Page(s): 773 - 775
Digital Object Identifier : 10.1109/LED.2011.2125940

This letter reports a new source of dark current random telegraph signal in CMOS image sensors due to meta-stable Shockley–Read–Hall generation mechanism at oxide interfaces. The role of oxide defects is discriminated thanks to the use of ionizing radiations. A dedicated RTS detection technique and several test conditions (radiation dose, temperature, integration time, photodiode bias) reveal the particularities of this novel source of RTS. Read More »


 

Temperature Dependence of the Threshold Voltage Shift Induced by Carrier Injection in Integrated STI-Based LDMOS Transistors

Poli, S.  Reggiani, S.  Denison, M.  Gnani, E.  Gnudi, A.  Baccarani, G.  Pendharkar, S.  Wise, R. 
Page(s): 791 - 793
Digital Object Identifier : 10.1109/LED.2011.2135835

Large threshold voltage shifts $(Delta V_{t})$ are experimentally observed in n-channel lateral DMOS transistors under high current–voltage regime. The effect is enhanced by the gate voltage as well as by the ambient temperature $(T_{A})$ . By approximating the curves with the usually adopted power-law dependence ... Read More »

RF Model and Verification of Through-Silicon Vias in Fully Integrated SiGe Power Amplifier

Liao, H.-Y.  Chiou, H.-K. 
Page(s): 809 - 811
Digital Object Identifier : 10.1109/LED.2011.2136313

This letter proposes an RF model of through-silicon via (TSV) considering both skin-depth and lossy substrate effects up to 20 GHz. The TSV is fabricated in 0.18-$muhbox{m}$ SiGe BiCMOS process with the dimensions of 50 $muhbox{m}$ in diameter and 100 $muhbox{m}$ in depth. The equivalent circuit model... Read More »

Channel-Length-Dependent Transport Behaviors of Graphene Field-Effect Transistors

Han, S.-J.  Chen, Z.  Bol, A. A.  Sun, Y. 
Page(s): 812 - 814
Digital Object Identifier : 10.1109/LED.2011.2131113

This letter presents a detailed study of transport in graphene field-effect transistors (GFETs) with various channel lengths, from 5 $muhbox{m}$ down to 90 nm, using transferred graphene grown by chemical vapor deposition. An electron–hole asymmetry observed in short-channel devices suggests a strong impact from graphene/metal contacts. In addition, for the first time, we observe a shift of the gate voltage at the Dirac poi... Read More »

Marie Curie PhD position in Catania, Italy

Dear Colleague,

it is a pleasure to inform you that a Marie Curie Early Stage Researcher
position is available at the Institute for Microelectronics and
Microsystem of the National Research Council of Italy (IMM-CNR) in
Catania.
The position is on the topic "Physical issues at interfaces and
nanoscale in advanced SiC devices", and it is open in the framework of
the FP7 Marie Curie ITN - NetFISiC (Training NETwork on Functional
Interfaces for SiC).

You can find more information on the position in the following link:

http://ec.europa.eu/euraxess/index.cfm/jobs/jobDetails/33681023

Would you please inform all the potential applicants for this position
(graduated students in Physics, Engineering or Material Science ) about
this good opportunity.

Should you need more information, contact:

Fabrizio Roccaforte
CNR-IMM
Strada VIII n.5, Zona Industriale
I-95121 Catania
Italy
tel. +39-0955968226
fax. +39-0955968312
e-mail: fabrizio.roccaforte@imm.cnr.it

International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, MAY 2011

A physically based, accurate compact model of direct tunneling gate current considering quantum mechanical effects in nanoscale metal-oxide-semiconductor field-effect transistors

1. M. A. Karim^1,2,*,
2. Q. D. M. Khosru¹

Article first published online: 12 MAY 2011

DOI: 10.1002/jnm.817

Copyright © 2011 John Wiley & Sons, Ltd.

Issue

International Journal of Numerical Modelling: Electronic Networks, Devices and Fields

Early View (Online Version of Record published before inclusion in an issue)

Open Ph D scholarship in semiconductor device modeling

We offer one scholarship for a Ph D student position in the Department of Electronic Engineering in the Universitat Rovira i Virgili (URV), in Tarragona, Spain.

The duration of the grant will be for four years. The monthly salary will be about 1000 Euro/month. The position will start in September 2011.

The candidate should have a Bachelor or Master degree in Electrical Engineering, Electronic Engineering, Telecommunication Engineering or Physics. A good background in Semiconductor Physics, Semiconductor Devices, or Integrated Circuit Design will be highly appreciated.

The work to be done by the candidate will be focused on the development of new techniques of characterization and modeling of novel advanced semiconductor devices, in particular nanoscale MOSFETs. It will be related to several European projects in which the hosting group participates, in particular the COmpact MOdelling Netwok (COMON), that is led by the hosting group (the so-called NEPHOS group) and the SQWIRE (Silicon Quantum WIREs) project, about junctionless nanowires.

The NEPHOS group at URV is one of the most powerful teams in Europe in the area of compact modeling of semiconductor devices.

Required documents for applicants


Applicants are required to send to the address specified below the following documents (in English or Spanish):

1) a full Curriculum Vitae (as complete as possible) with passport number

2) Copy of their diploma

3) copy of their passport

4) Academic certificate including their marks (it is important that the number of hours or credits of each subject appears). It is also very important that the document specifies what is the minimum mark for passing a given subject and what is the maximum mark that can be awarded.

Candidates are requested to send their documents by e-mail to:

Prof. Benjamin Iñiguez
Department of Electronic, Electrical and Automatic Control Engineering

Universitat Rovira i Virgili (URV)

Avinguda Països Catalans, 26
43007 Tarragona (Spain)
Email: benjamin.iniguez@gmail.com
Tel: +34977558521 Fax:+34977559610

Deadline: May 31 2011

You can contact Prof. Benjamin Iñiguez (Benjamin.Iniguez@gmail.com) for more information

Tarragona is a medium city (100000 inhabitants) with a Mediterranean climate and many recreation opportunities (nice beaches, theme parks, nature preserves, mountain hiking, touristic resorts and facilities). It is located 100 km Southwest of Barcelona, and it is very well connected by train, bus, highways and even low cost flights from its own airport. Additional information about the University and the department can be found at: www.urv.cat and sauron.etse.urv.es

Spice simulation, Tina-TI, LTSpice, PSpice, and more

Spice simulation, Tina-TI, LTSpice, PSpice, and more: "I got a nice note from the irrepressible Mary Dunnie that Texas Instruments h..."

job offer at Mentor

As today (May 10, 2011), there is an open position as pre-sales engineer at Mentor. More details here.

π Raspberry Pi Foundation

The Raspberry Pi Foundation is a UK registered charity (Registration Number 1129409) which exists to promote the study of computer science and related topics, especially at school level, and to put the fun back into learning computing [read more...]

Reflections from ISSCC 2011

Sotiris Bantas, VP Technology, Helic Inc., has posted his reflections from ISSCC 2011. Surly you will enjoy reading this: http://goo.gl/HB0ka

TSMC not following Intel to Finfets at 22nm - waiting till 20nm

Nearly a decade ago, TSMC demo-ed a 25nm Finfet - what Intel calls a Tri-Gate - transistor [more at Mannerisms]

Celebrating engineering: EDN names 2010 Innovation Award winners

Celebrating engineering: EDN names 2010 Innovation Award winners: "San Jose, CA—In aceremony here Monday evening, EDN bestowed its 2..."

Category: EDA Tools and ASIC TechnologiesThe finalists in this category—Apache Design Solutions, GateRocket Inc, GlobalFoundries, and Mentor Graphic—are recognized for innovations in design automation tools that reduce cycle time, increase manufacturability, and improve the reliability of integrated circuits. "Tonight's winner has achieved two of the most difficult feats in the EDA industry," Technical Editor Mike Demler said. "First, it has a history of developing innovative, differentiated products. This latest innovation addresses the problem of simulating electro-static discharge that has challenged designers for many years. The second distinction is to leverage that success into a proposed IPO."

Winner: Apache Design Solutions

Intel And Seagate: Silicon Transistor And Magnetic Storage Density Maintain An Impressively Steady Improvement Rate - Brian's Brain | Blog on EDN

Intel And Seagate: Silicon Transistor And Magnetic Storage Density Maintain An Impressively Steady Improvement Rate - Brian's Brain Blog on EDN


Two fundamental technology breakthroughs in two days; these are the times that tech editors dream of! I’ve in the past drawn a correlation between Moore’s Law (named for Intel’s Gordon), a forecast of the pace of single-chip transistor integration increase over time first made in 1965, and the rate of capacity growth over time (said another way, cost-per-capacity) for both magnetic and semiconductor storage. Solid-state drives, of course, are direct beneficiaries of Moore’s prescience, but areal density increases in magnetic storage are at least as impressive if not more so.