Jun 30, 2021

[mos-ak] [2nd Announcement and C4P] 18th MOS-AK ESSDERC/ESSCIRC Workshop (virtual/online) Sept.6, 2021

Arbeitskreis Modellierung von Systemen und Parameterextraktion

Modeling of Systems and Parameter Extraction Working Group

18th MOS-AK ESSDERC/ESSCIRC Workshop

Grenoble, Sept. 6, 2021

2nd Announcement and C4P

Together with local host CEA-Let and STM, lead sponsor ASCENT+, as well as all the Extended MOS-AK TPC Committee, would like to invite you to the 18th MOS-AK ESSDERC/ESSCIRC Workshop Compact/SPICE Modeling Workshop which will be organized as the virtual/online event on Sept. 6, 2021, preceding the ESSDERC/ESSCIRC Conference.

Planned virtual 18th MOS-AK ESSDERC/ESSCIRC Workshop aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring academic and industrial experts in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors.

Topics to be covered include the following among other related to the compact/SPICE modeling and its Verilog-A standardization:

Compact Modeling (CM) of the electron devices
Advances in semiconductor technologies and processing
Verilog-A language for CM standardization
New CM techniques and extraction software
Open Source (FOSS) TCAD/EDA modeling and simulation
CM of passive, active, sensors and actuators
Emerging Devices, Organic TFT, CMOS and SOI-based memory
Microwave, RF device modeling, high voltage device modeling
Nanoscale CMOS, BiCMOS, SiGe, GaN, InP devices and circuits
Technology R&D, DFY, DFT and reliability/aging IC designs
Foundry/Fabless Interface Strategies

Speakers' tentative list includes the following names (in alphabetic order):

Hussam Amrouch; KTI (DE)
Sheikh Aamir Ahsanl; NIT Srinagar (IN)
Mohamed Aouad, CEA-Leti (FR)
Natalia Seoane Iglesias; USC University (ES)
Muhammad Hussain; UCB (US)
Sergey Kokin; MEPHI (RU)
Luisa Petti; Free University of Bozen-Bolzano (IT)
Paul Roseingrave; Tyndall (IE)
Olivier Rozeau; CEA-Leti (FR)
Valentin O. Turin; Orel State University (RU)

Online Abstract Submission to be open in July 2021

(any related enquiries can be sent to abstract@mos-ak.org)

Online Workshop Registration to be in August 2021
(any related enquiries can be sent to register@mos-ak.org)

Important Dates:

Call for Papers - April 2021
2nd Announcement - June 2021
Final Workshop Program - Aug 2021
MOS-AK Workshop - Sept.6, 2021
as Virtual Educational Event at ESSDERC/ESSCIRC

W.Grabinski for Extended MOS-AK Committee

WG300621

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Jun 29, 2021

#Garage #Semi #Fab Gets Reactive-Ion Etching Upgrade https://t.co/Idbflx3oZN https://t.co/mw0q6ZdCmw

#Garage #Semi #Fab Gets Reactive-Ion Etching Upgrade https://t.co/Idbflx3oZN https://t.co/mw0q6ZdCmw
— Wladek Grabinski (@wladek60) Jun 29, 2021

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June 29, 2021 at 02:53PM
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[paper] Nano Device Simulator

Zlatan Stanojevic , Member, IEEE, Chen-Ming Tsai, Georg Strof, Ferdinand Mitterbauer, Oskar Baumgartner, Member, IEEE, Christian Kernstock, and Markus Karner, Member, IEEE

Nano Device Simulator - A Practical Subband-BTE Solver for Path-Finding and DTCO

in IEEE TED, Open Access, June 2021

DOI: 10.1109/TED.2021.3079884.

Global TCAD Solutions GmbH, 1010 Vienna

Abstract: We present an in-depth discussion on the subband Boltzmann transport (SBTE) methodology, its evolution, and its application to the simulation of nanoscale MOSFETs. The evolution of the method is presented from the point of view of developing a commercial general purpose SBTE solver, the GTS nano device simulator (NDS). We show a wide range of applications SBTE is suited for, including state-of-the-art nonplanar and well-established planar technologies. It is demonstrated how SBTE can be employed both as a path-finding tool and a fundamental component in a DTCO-flow.

Fig: NDS simulation of a device generated using level-set topography simulation; left: level-set generated FinFET with complex warped surfaces, typical of topography simulation; the analytical doping is shown; middle: the SBTE domain is cut out of the device and meshed using an extruded grid, and mixed with the mesh of the rest of the device; cuts are then extracted from the SBTE domain and remeshed; right: electron drift velocity in the FinFET, DD versus SBTE; the SBTE result clearly shows the velocity overshoot effect not seen in the DD solution.

Acknowledgment: The authors would like to thank Dr. Edward Chen for many fruitful discussions and the continued valuable feedback.

Jun 28, 2021

South #Korea targets 2028 for first #6G network [Report https://t.co/bKmu4qQ6Ln] #semi https://t.co/MNuL4ssbw5

South #Korea targets 2028 for first #6G network [Report https://t.co/bKmu4qQ6Ln] #semi https://t.co/MNuL4ssbw5
— Wladek Grabinski (@wladek60) Jun 28, 2021

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June 28, 2021 at 02:49PM
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[paper] RTN and BTI statistical compact modeling

G.Pedreira^a, J.Martin-Martinez^a, P.Saraza-Canflanca^b, R.Castro Lopez^b, R.Rodriguez^a, E.Roca^b, F.V.Fernandez^b, M.Nafria^a

Unified RTN and BTI statistical compact modeling from a defect-centric perspective

Solid-State Electronics

Available online 25 June 2021, 108112

In Press, Journal Pre-proof

DOI: 10.1016/j.sse.2021.108112

a Universitat Autònoma de Barcelona (UAB), Electronic Engineering Department, REDEC group. Barcelona, Spain
b Instituto de Microelectrónica de Sevilla, IMSE-CNM, CSIC and Universidad de Sevilla, Spain

Abstract: In nowadays, deeply scaled CMOS technologies, time-dependent variability effects have become important concerns for analog and digital circuit design. Transistor parameter shifts caused by Bias Temperature Instability and Random Telegraph Noise phenomena can lead to deviations of the circuit performance or even to its fatal failure. In this scenario extensive and accurate device characterization under several test conditions has become an unavoidable step towards trustworthy implementing the stochastic reliability models. In this paper, the statistical distributions of threshold voltage shifts in nanometric CMOS transistors will be studied at near threshold, nominal and accelerated aging conditions. Statistical modelling of RTN and BTI combined effects covering the full voltage range is presented.

The results of this work suppose a complete modelling approach of BTI and RTN that can be applied in a wide range of voltages for reliability predictions.

Program 2021: Symposium on Schottky Barrier MOS Devices

The symposium goal is to combine the activities of an enthusiastic group of Schottky barrier researchers worldwide. The topics cover all important aspects of potential applications, simulation and modeling, processing and implementation for CMOS/SOI technologies, Quantum technologies and approaches for neuromorphic applications. The content will be beneficial for anyone who needs to learn the opportunities and challenges of this technology since the first introduction by Walter Schottky in the 1938s. New aspects and future proposals to make the Schottky barrier into the main stream are welcome.

Program 2021

Wed 30.06.2021 (Virtual)

13:00-13:05	Opening IEEE DL
13:05-14:00	IEEE Distinguished Lecture: Tunneling Graphene FET Gana Nath Dash, Sambalpur University (IN) Abstract: During the last few decades, aggressive scaling in Si MOSFET (Metal Oxide Semiconductor Field Effect Transistor) architecture has given rise to several short channel effects, which in turn has set a performance limit on the device owing to constraint in Si technology. The emergence of graphene at this juncture with a host of exotic and favorable electronic properties, generated new hopes for the FET industry. While the graphene based analogue FET witnessed some advantages, the digital counterpart showed a dismal performance, primarily due to the zero bandgap of graphene (poor ON/OFF ratio). For a way out, an alternative architecture based on the quantum tunneling process is augmented with the graphene FET resulting in the new device named TGFET.

14:00-14:05	Opening SSBMOS
14:05-14:35	Germanium nanosheet and nanowire transistor technologies for beyond CMOS applications Walter M. Weber, Raphael Böckle, Lukas Wind, Kilian Eysin, Daniele Nazzari, Tatli Ezgi, Oliver Solfronk, Alois Lugstein and Masiar Sistani, Institute of Solid State Electronics, TU Vienna (A) Abstract: The ultimate downscaling limits of conventional field effect transistors calls for alternative computational methods that provide perspectives towards the enhancement of computational complexity, circuit performance and energy efficiency. In this sense germanium nano-transistors offer both an approachable access to quantum confinement effects and promising electronic transport properties that distinctly are compatible with modern CMOS fabrication flows. We will discuss the applicability of different germanium active regions and gating architectures towards the realization of computational electronics with added functionality. On top of exploring different realizations of reconfigurable transistors with programmable polarity we will discuss further functionality enhancement by enabling operability within the negative differential resistance regime at room temperature. Prospective implications at the circuit level will be discussed.
14:40-15:10	Evolving contact-controlled thin-film transistors Radu Sporea, University of Surrey (UK) Abstract: TFT designs that comprise multiple gates and rectifying source contacts can be designed to produce linear transconductance and act as robust amplifiers and signal converters. This talk outlines device design and opportunities in emerging edge processing applications.
15:10-15:50	COFFEE BREAK
15:50-16:20	Compact Modelling of Dually-Gated Reconfigurable Field-Effect Transistors Christian Römer, Ghader Darbandy, Mike Schwarz, Jens Trommer, André Heinzig, Thomas Mikolajick, Walter M. Weber, Benjamín Iñíguez** and Alexander Kloes* NanoP, THM (DE), namLAB, TU Dresden (DE), TU Vienna (A), DEEEA, URV (ES) Abstract:** This work presents a closed-form and physics-based DC compact model, which is applicable on dually-gated reconfigurable field-effect transistors (RFETs). The presented compact model is focused on the charge-carrier injection at the device’s source and drain side Schottky barriers, which can be separated into field emission and thermionic emission current contributions. This work explains the basic equations which are used to calculate the current contributions and shows calculated device characteristics compared to measurements.
16:25-16:55	The Schottky barrier transistor in all its forms Laurie Calvet, John P. Snyder, Mike Schwarz** C2N, University Paris (FR),* JCap, LLC (USA), *NanoP, THM (DE) Abstract:** The Schottky barrier (SB) transistor, where the source and drain of a conventional planar MOSFET are replaced with metallic contacts, was first explored in the 1960s. Since then, many variations on this structure have been explored in the literature including: different semiconductors materials such as other non-organic semiconductors and nano-structures such as carbon nanotubes and nanowires. In this talk we review some of the changes in the electronic transport that are observed as the geometry and materials of the SB transistors are changed.

Jun 26, 2021

Ten Lessons Learned from Andy Grove [Semiwiki https://t.co/ePZ5MMBbeO] #semi https://t.co/wc8oJZVA5R

Ten Lessons Learned from Andy Grove [Semiwiki https://t.co/ePZ5MMBbeO] #semi https://t.co/wc8oJZVA5R
— Wladek Grabinski (@wladek60) Jun 26, 2021

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June 26, 2021 at 12:39PM
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Jun 25, 2021

[paper] Accelerated numerical modeling of RF circuits

Hongliang Li¹, Jian-Ming Jin¹, Amir Hajiaboli², Douglas R. Jachowski²

Accelerated numerical modeling of RF circuits using network characteristic mode analysis

Int J Numer Model. 2021;e2898 pp.1-16

DOI: 10.1002/jnm.2898

1 Center for Computational Electromagnetics, Department of Electrical and Computer Engineering, University of Illinois, USA
2 Resonant Inc., Goleta, California, USA

Abstract: A fast numerical modeling approach based on network characteristic mode analysis (CMA) is presented and investigated for analyzing electrical layouts in miniature RF filters, such as surface acoustic wave filters. In this approach, a generalized eigenvalue decomposition is performed on the Z-parameters of an electrical layout at one or two sampling frequencies that can be computed and extracted with any numerical full-wave method. The obtained eigenvalues are used to extract modal resistance, inductance, and capacitance matrices for each eigenmode. The frequency dependence of the modal resistance matrix can be assumed a priori or determined automatically, and the modal inductance and capacitance matrices are assumed frequency independent. These modal matrices are then used to approximate the Z-parameters at any other frequencies to provide the response of the electrical layout, which can then be combined with the frequency responses of other components, such as resonators, to yield the electrical response of an entire RF filter. Compared with the previously developed analytic extension of eigenvalues, this fast CMA-based method is less affected by the frequency variation of eigenmodes since the frequency dependencies of the eigenmodes are implicitly canceled out in its formulation. The accuracy of this approach is evaluated by comparing with results from full-wave analyses. For RF circuits whose electrical sizes are small and whose frequency range of interest is relatively small, the proposed CMA- based fast frequency sweep approach is found to be sufficiently accurate and highly practical for engineering applications.

Fig: Configuration of a four-port microstrip circuit with two lumped devices

(A) Dimensions of the layout; (B) Equivalent circuit for a bandpass filter;

Acknowledgements: The third and fourth authors would like to thank Andy Guyette and Jackson Massey from Resonant, Inc. for useful discussions and help in some of the simulations presented in this article.

[paper] Nanosheet field effect transistors

J. Ajayan^a, D. Nirmal^b, Shubham Tayal^a, Sandip Bhattacharya^a, L. Arivazhagan^c, A.S. Augustine Fletcher^b, P. Murugapandiyan^d, D. Ajitha^e

Nanosheet field effect transistors - A next generation device to keep Moore’s law alive:
An intensive study

Microelectronics Journal 114 (2021) 105141

DOI: 10.1016/j.mejo.2021.105141

a SR University, Warangal, Telangana, India
b Karunya Institute of Technology and Sciences, Coimbatore, Tamilnadu, India
c Sri Ramakrishna Engineering College, Coimbatore, Tamilnadu, India
d Anil Neerukonda Institute of Technology & Sciences, Visakhapatnam, Andhra Pradesh, India
e Sreenidhi Institute of Science and Technology, Hyderabad, Telangana, India

Abstract: Incessant downscaling of feature size of multi-gate devices such as FinFETs and gate-all-around (GAA) nanowire (NW)-FETs leads to unadorned effects like short channel effects (SCEs) and self-heating effects (SHEs) which limits their performance and causes reliability issues. FinFET technology has resulted in a remarkable performance up to a feature size of 7nm. The research community is expecting that GAA NW-FETs will take over FinFET technology from 7nm to 5nm. However, further shrinking of feature size to 3nm will impose severe challenges to the performance of these aforesaid multi-gate devices. Subsequently, the electron device designer community needs to look for alternative device designs like nanosheet FETs (NS-FETs) to overcome the limitations of the FinFET and GAA NW-FETs technologies. The driving force behind the emergence of these NS-FETs is their ability to scale down even below a feature size of 5nm with negligible short channel effects. Therefore, in this review article we have intensively investigated the NS-FETs in terms of impact of geometrical scaling, substrate material effects, parasitic channel effects, thermal effects, compatibility with different metal gates, and source/drain (S/D) metal depth effect. Consequently, it can be concluded that vertically stacked NS-FET is the most promising solution for future digital/analog integrated circuit applications due to their outstanding capability to keep Moore’s Law alive.

Fig: 3-D views of (a) FinFET (b) stacked NW-FET (c) vertically stacked NSFET.

#Shenzhen Technology #University sets up school of #IC with Chinese #SMIC

#Shenzhen Technology #University sets up school of integrated circuit #IC with Chinese leading #chip maker #SMIC [Global Times https://t.co/qIQLPe4M1V] #semi https://t.co/49Bd3pV4dw
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June 25, 2021 at 02:09PM
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Jun 23, 2021

EAI ICCASA 2021 Accepting Papers

Web version

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October 28 - 29, 2021
Original Location: Ho Chi Minh City, Vietnam
Submission Deadline: July 6, 2021 (extended)

EAI ICCASA 2021 will be held as a fully-fledged online conference (with an on-site possibility). Participate online and join the conference from wherever you are located!

Get the same full publication and indexing, enjoy EAI's fair evaluation and recognition, present your paper to a global audience, and experience virtual meetings live as well as on-demand from the safety and comfort of your home.

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If the local situation allows it, the event will take place in its original location with an option for all authors to present remotely. In any case, all matters related to publication and indexing will remain unchanged.

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- EAI ICCASA celebrates its 10th anniversary -

ICCASA 2021 is a place for highly original ideas about how Context-Aware Systems (CAS) are going to shape networked computing systems of the future. Hence, it focuses on rigorous approaches and cutting-edge solutions which break new ground in dealing with the properties of context-awareness. Its purpose is to make a formal basis more accessible to researchers, scientists, professionals and students as well as developers and practitioners in ICT by providing them with state-of-the-art research results, applications, opportunities and future trends.

We are pleased to invite you to submit your paper to EAI ICCASA 2021. Submissions should be in English, following the Springer formatting guidelines (see Submission).

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