[paper] Effect of doping on Al2O3/GaN MOS capacitance

B.Rrustemi^ab, C.Piotrowicz^a, M-A.Jaud^a, F.Triozon^a, W.Vandendaele^a, B.Mohamad^a, R.Gwoziecki^a, G.Ghibaudo^b

Effect of doping on Al2O3/GaN MOS capacitance

Solid-State Electronics

Vol. 194, Aug. 2022, 108356

DOI: 10.1016/j.sse.2022.108356

   
a CEA, LETI, Grenoble (Fermi)
b IMEP-LAHC Minatec, Grenoble(FR)

Abstract: This paper investigates the turning-on-voltage (VFB/VTH) of Al2O3/GaN MOS stacks with n-doped GaN, p-doped GaN and not intentionally doped (NID) GaN by exploiting capacitance measurements on large gate area test structures with systematic variation of Al2O3 thickness (tox). Measurements are compared with 1D Schrödinger-Poisson simulations including incomplete ionization model. The necessity of using a quantum description of electron density is demonstrated especially for thinner gate oxides. We found that, contrary to what is expected, p-doping below the channel barely increases the VTH and the VTH is independent of tox, even if the density of activated acceptors is demonstrated to be sufficiently high. Our results highly suggest that the negative charge induced by p-doping is compensated at the oxide level.

Fig: Al2O3/GaN MOS stacks with n-doped GaN, p-doped GaN and its CV plots

[mos-ak] [Final Program] Spring MOS-AK Workshop April 29, 2022 (online)

Together with local host INAOE (MX), as well as all the Extended MOS-AK TPC Committee, would like to invite you to the Spring MOS-AK Workshop Compact/SPICE Modeling Workshop which will be organized as the virtual/online event on April 29, 2022

Upcoming online Spring MOS-AK Workshop aims to strengthen a network and discussion forum among experts in the field, create an open forum for sharing information related to compact/SPICE modeling and Verilog-A standardization, bring academic and industrial experts in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. The content will be helpful for anyone who needs to understand what is really behind the IC simulation in modern device models, in particular using Free 130nm Skywater PDK.

Final Spring MOS-AK Workshop Program is available online:

https://www.mos-ak.org/spring_2022/

Online Registration Form 

https://forms.gle/2csBFMQXxMW7Ky5g8

Registered participants will receive an online meeting invitation 24h before the event. 

(any related enquiries can be sent to register@mos-ak.org)

Important Dates: 

• Call for Papers: Feb. 2022
• 3nd Announcement: April 5, 2022
• Spring MOS-AK Workshop: April 29, 2022
• Online Event 4:00pm - 6:00pm CET / GMT-1

Postworkshop Publications: Selected, the best MOS-AK technical presentation will be recommended for further publication in a special Solid State Electronics (SSE) issue on compact modeling.

-- W.Grabinski for Extended MOS-AK Committee

WG270422

[paper] 50 Two-Transistor MOSFET Circuits

Harald Pretl* and Matthias Eberlein**

Fifty Nifty Variations of Two-Transistor Circuits: A tribute to the versatility of MOSFETs

IEEE Solid-State Circuits Magazine 13(3):38-46, August 2021

DOI: 10.1109/MSSC.2021.3088968  

  

* Institute for Integrated Circuits, JKU, Linz, Austria
** Semiconductor electronics, TU, Darmstadt, Germany

Abstract: We present a compendium of two-MOS-transistor circuits, spanning the range from simple standard configurations to ingenious arrangements. Using these building blocks, circuit designers can assemble a vast array of complex analog functions. This (incomplete) collection shall serve as a reference and inspiration to junior circuit designers and hopefully contains at least one unexpected example for the professional engineer.

Part 1/2 #thisismagic #circuit #mosfet

Part 2/2 #thisismagic #circuit #mosfet

Acknowledgments: We thank the reviewers for their many mindful suggestions. We want to thank our colleagues at the Institute for Integrated Circuits, Johannes Kepler University Linz, for their support in preparing this manuscript and for their many enlightening discussions.

[paper] Universal Charge Model for Multigate MOS Structures

Kwang-Woon Lee and Sung-Min Hong

Derivation of a Universal Charge Model for Multigate MOS Structures

with Arbitrary Cross Sections

IEEE TED (2022, Early Access)

DOI:  10.1109/TED.2022.316486

   

* Gwangju Institute of Science and Technology (KR)

Abstract: A universal equation for the charge-voltage characteristics in the multigate metal oxide semiconductor (MOS) structure with an arbitrary cross section is presented. A generalized coordinate is proposed and the Poisson equation is integrated with a weighting factor related with the generalized coordinate and the electric field. A compact charge model is derived and analytic and numerical examples for various MOS structures are shown.

Fig: Thin slab in the semiconductor channel region of the multigate MOS structure. The A∗ surfaces are perpendicular to the z-direction, which is the transport direction and its generalized coordinate, ψ, for rectangular nanosheet MOS structures at 0.0 V (top) and 0.7 V (bottom).

Aknowlegements: This workwas supported by the National Research Foundation of Korea (NRF) Grant funded by the Korean Government under Grant NRF- 2019R1A2C1086656 and Grant NRF-2020M3H4A3081800.

[paper] DL Physics-Driven MOSFET Modeling

Ming-Yen Kao, H. Kam, and Chenming Hu, Life Fellow, IEEE

Deep-Learning-Assisted Physics-Driven MOSFET Current-Voltage Modeling

in IEEE Electron Device Letters

DOI: 10.1109/LED.2022.3168243

Abstract: In this work, we propose using deep learning to improve the accuracy of the partially-physics-based conventional MOSFET current-voltage model. The benefits of having some physics-driven features in the model are discussed. Using a portion of the Berkeley Short-channel IGFET Common-Multi-Gate (BSIM-CMG), the industry-standard FinFET and GAAFET compact model, as the physics model and a 3-layer neural network with 6 neurons per layer, the resultant model can well predict IV, output conductance, and transconductance of a TCAD-simulated gate-all-around transistor (GAAFET) with outstanding 3-sigma errors of 1.3%, 4.1%, and 2.9%, respectively. Implications for circuit simulation are also discussed.

Fig: (a) Model implementation for circuit simulations, without the relative gm and gds errors terms in the cost function, Model shows larger prediction error in (b) gm and (c) gds.

Acknowledgements: This work was supported by the Berkeley Device Modeling Center, 

UCB, CA (USA)

[paper] DC, LF noise and TID mechanisms in 16nm FinFETs

Stefano Bonaldo^ab, Teng Ma^ab, Serena Mattiazzo^bc, Andrea Baschirotto^de, Christian Enz^f, Daniel M.Fleetwood^g, Alessandro Paccagnella^ab, Simone Gerardin^ab

DC response, low-frequency noise, and TID-induced mechanisms in 16-nm FinFETs for high-energy physics experiments

J. NIMA Section A; available online 18 April 2022, 166727

DOI: j.nima.2022.166727

     
a University of Padova (I)
b INFN Padova (I)
c University of Padova (I)
d INFN Milano (I)
e University of Milano Bicocca (I)
f ICLab, EPFL, Lausanne (CH)
g Vanderbilt University, Nashville (USA)

Abstract: Total-ionizing-dose (TID) mechanisms are evaluated in 16nm Si bulk FinFETs at doses up to 1 Grad (SiO₂) for applications in high-energy physics experiments. The TID effects are evaluated through DC and low-frequency noise measurements by varying irradiation bias conditions, transistor channel lengths, and fin/finger layouts. The TID response of nFinFETs irradiated under positive gate bias at ultrahigh doses shows a rebound of threshold voltage with significant increase in the 1/f noise amplitude. The degradation is related to the generation of border and interface traps at the upper corners of STI oxides and at the gate oxide/channel interfaces. In contrast, pFinFETs have the worst degradation due to positive charge trapping in STI oxides, which severely degrades the device transconductance and total drain current, while negligible effects are visible in the threshold voltage and 1/f noise. The TID sensitivity depends strongly on the transistor layout. Short-channel devices have the best TID tolerance thanks to the influence of halo implantation, while pFinFETs designed with low number of fins have the worst degradation because of high densities of positive charge in the surrounding thick STI oxides. As a guideline for IC design, short-channel transistors with more than 4-fins may be preferred in order to facilitate circuit qualification.

Fig: Low-frequency noise measured at |Vds|=50mV and |Vgs|=0.85V at room temperature for pFinFET with Nfin=2 and L=16 nm, irradiated up to 1Grad (SiO2) in the ON condition

Acknowledgment: This work has been carried out within the FinFET16v2 experiment funded by the National Institute for Nuclear Physics - INFN, Italy.

[paper] Roadmapping of Nanoelectronics for the New Electronics Industry

Paolo Gargini¹,Francis Balestra², and Yoshihiro Hayashi³

Roadmapping of Nanoelectronics for the New Electronics Industry

Appl. Sci. 2022, 12(1), 308

DOI: 10.3390/app12010308

Received: 4 November 2021 / Revised: 17 December 2021 

Accepted: 20 December 2021 / Published: 29 December 2021

Academic Editor: Gerard Ghibaudo; This article belongs to the Special Issue Advances in Microelectronic Materials, Processes and Devices

   
1IEEE IRDS, (US)
2 CNRS, Grenoble INP (F)
3 Keio University, Tokyo (J)

Abstract: This paper is dedicated to a review of the international effort to map the future of nanoelectronics from materials to systems for the new electronics industry. The following sections are highlighted: the Roadmap structure with the international teams, the methodology and historical evolution, the various eras of scaling, the new ecosystems and computer industry, the evolving supply chain, the development of SoC and SiP, the advent of the Internet of Everything and the 5G communications, the dramatic increase of data centers, the power challenge, the technology fusion, heterogeneous and system integration, the emerging technologies, devices and computing architectures, and the main challenges for future applications.

FIG: 40 Years of Microprocessor Trend Data

[webinar] Prof. Benjamin Iniguez' IEEE EDS DL on “2D Semiconductor FET Modeling”

[webinar] Prof. Benjamin Iniguez' IEEE EDS DL on “2D Semiconductor FET Modeling” https://t.co/cIYL8W3M0D #semi https://t.co/s3DX1301MN

— Wladek Grabinski (@wladek60) Apr 12, 2022

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[paper] Noise Degradation and Recovery in Gamma-irradiated SOI nMOSFET

S.Amora^b, V.Kilchytska^a, F.Tounsi^a, N.André^a, M.Machhout^b, L.A.Francis^a, D.Flandre^a

Characteristics of noise degradation and recovery in gamma-irradiated SOI nMOSFET

with in-situ thermal annealing

Solid-State Electronics; 108300; online 7 April 2022, 

DOI: 10.1016/j.sse.2022.108300

   
a SMALL, ICTEAM Institute, Université catholique de Louvain (B)
b Faculté des Sciences de Université de Monastir (TN)

Abstract: This paper demonstrates a procedure for complete in-situ recovery of on-membrane CMOS devices from total ionizing dose (TID) defects induced by gamma radiation. Several annealing steps were applied using an integrated micro-heater with a maximum temperature of 365°C. The electrical characteristics of the on-membrane nMOSFET are recorded prior and during irradiation (up to 348 krad (Si)), as well as after each step of the in-situ thermal annealing. High-resolution current sampling measurements reveal the presence of oxide defects after irradiation, with a clear dominant single-trap signature in the random telegraph noise (RTN) traces. Drain current over time measurements are used for the trap identification and further for the defects' parameters extraction. The power spectral density (PSD) curves confirm a clear dominance of the RTN behavior in the low-frequency noise. A radiation-induced oxide trap is detected at 5.4 nm from the Si-SiO2 interface, with an energy of 0.086 eV from the Fermi level in the bandgap. After annealing, the RTN behavior vanishes with a further important reduction of flicker noise. Low-frequency noise measurements of the transistor confirmed the neutralization of oxide defects after annealing. The electro-thermal annealing of the nMOSFET allows a total recovery of its original characteristics after being severely degraded by radiation-induced defects.

Fig: Device under test : (a) cross-section schematic, (b) microscopic front view

showing the membrane and other embedded elements

#Soitec s’allie à #STM, #GF et au #CEA-Leti pour faire avancer les puces #FD-SOI

#Soitec s’allie à #STM, #GF et au #CEA-Leti pour faire avancer les puces #FD-SOI https://t.co/tAfGLSVszo #semi https://t.co/d5leucXrui

— Wladek Grabinski (@wladek60) Apr 8, 2022

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April 08, 2022 at 08:11PM
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The #CHIPS for America #Act is a Blueprint for Semiconductor Leadership, but for whom?

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— Wladek Grabinski (@wladek60) Apr 8, 2022

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[webinar] Power WBG Semiconductor Technology Opportunities

"Power WBG Semiconductor Technology Opportunities"

webinar hosted by 

Dr. Victor Veliadis, 

Executive Director and CTO of PowerAmerica, 

a WBG semiconductor power electronics consortium

Event by Łukasiewicz - Institute of Microelectronics and Photonics

Register now: https://lukasiewiczimif.clickmeeting.com/poweramerica/register

Silicon power devices have dominated power electronics due to their excellent starting material quality, ease of fabrication, low-cost volume production, and proven reliability. However, they’re approaching their operational limits primarily due to their relatively low bandgap and critical electric field that results in high conduction and switching losses, and poor high-temperature performance. So what can we do? Well, let’s talk about the favorable WBG material properties, their volume application opportunities, and last but not least let's highlight the respective competitive advantages of SiC and GaN.

You will additionally learn about:

• the lateral and vertical power device configurations that will be analyzed in the context of bidirectional switching
• specific applications and needs for bidirectional switches
• key topologies, enabled by bidirectional switches
• PowerAmerica’s work to accelerate WBG power electronics commercialization

About Dr. Veliadis: Dr. Victor Veliadis is Executive Director and CTO of PowerAmerica, a WBG semiconductor power electronics consortium. At PowerAmerica, he has managed a budget of $146 million that he strategically allocated to 200 industrial and University projects to accelerate WBG semiconductor clean energy manufacturing, workforce development, and job creation. His PowerAmerica educational activities have trained 410 University FTE students in applied WBG projects, and engaged 4100 attendees in tutorials, short courses, and webinars. Dr. Veliadis is an ECE Professor at NCSU and an IEEE Fellow and EDS Distinguished Lecturer. He has 27 issued U.S. patents, 6 book chapters, and over 125 peer-reviewed publications. Prior to entering academia and taking an executive position at Power America in 2016, Dr. Veliadis spent 21 years in the semiconductor industry where his work included design, fabrication, and testing of SiC devices, GaN devices for military radar amplifiers, and financial and operations management of a commercial semiconductor fab. He has a Ph.D. degree in Electrical Engineering from John Hopkins University (1995).

[Naveed Sherwani] well Sam Zeloof is now looking for a $1M donation

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— Wladek Grabinski (@wladek60) Apr 7, 2022

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[paper] Compact Model of JLNGAA MOSFET in Verilog-A

Billel Smaani^1,2, Shiromani Balmukund Rahi³ and Samir Labiod⁴

Analytical Compact Model of Nanowire Junctionless Gate-All-Around MOSFET

Implemented in Verilog-A for Circuit Simulation. 

Silicon (2022)

DOI: 10.1007/s12633-022-01847-9

   

1 Centre Universitaire Abdelhafid Boussouf, Mila, Algeria

2 Electronique Department, Constantine I University, Algeria

3 Department of Electrical Engineering, IIT Kanpur, India

4 Department of Physics, Skikda University, Algeria

Abstract: In the present research article, we have proposed an analytical compact model for Nanowire Junctionless Gate-All-Around (JLNGAA) MOSFET validated in all transistor’s operation regimes. The developed model having an analytical compact form of the current expressions, based on surface potential (ΦS), obtained from approximated solutions of Poisson’s equation. The proposed model has implemented in standard Verilog-A language using SMASH circuit simulator in order to be used in various commercial circuit simulators. The proposed model has also validated using ATLAS-TCAD simulation for various physical parameters such as the channel doping concentration (Nd) and the channel radius (R) of JLNGAA MOSFET. Finally, based on the developed Verilog-A JLNGAA MOSFET model, we have tested it in four types of low voltage circuits, CMOS inverter, CMOS NOR-Gate, an amplifier and a Colpitts oscillator.

Fig: Transient simulation of the implemented Colpitts oscillator using SMASH, where Vout is the output voltage. R = 4 nm, tox = 2 nm, L = 1 μm and Nd = 1E19/cm^3

Acknowledgments: Dr. S. B. Rahi (Indian Institute of Technology, Kanpur, India) for their useful suggestions

[Mannerism] #Top10 (+7) Semiconductor Companies In 2021

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— Wladek Grabinski (@wladek60) Apr 6, 2022

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[TechCrunch] A month after stopping shipments to customers in Russia and Belarus, #Intel has now suspended all business operations in Russia. #StandWithUkraine https://t.co/j6U0wnn0zP #semi https://t.co/FklsbFVrLS

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— Wladek Grabinski (@wladek60) Apr 6, 2022

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April 06, 2022 at 09:23AM
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[Webinar] M.Tech in VLSI for Industry Professionals at IIT Roorkee:

ECE department at IIT Roorkee is organizing a webinar on M.Tech in VLSI for Industry Professionals on April 09, 2022 @19:30. The duration is expected to be 45 min to 1 hour. The Department will present the program and its major highlights, which will be followed by interaction/discussion/Q&A.

Please fill up the google form:

https://forms.gle/LhQm4p1UmcDsDXH89

and we will send you the link to join shortly.

[read more: http://ece.iitr.ac.in/mtech-vlsi-industrg-professionols]

[mos-ak] [3rd Announcement and C4P] Spring MOS-AK Workshop on April 1, 2022 (online)

3rd Announcement and C4P

Together with local online host, as well as all the Extended MOS-AK TPC Committee, would like to invite you to the Spring MOS-AK Workshop which will be organized as the virtual/online event on (rescheduled for) April 29, 2022, between 4:00pm - 7:00pm (CET) providing an opportunity to meet with modeling engineers and researchers from Europe and Latin America. 

Upcoming online Spring MOS-AK Workshop aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring academic and industrial experts in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors, in particular using Free 130nm Skywater PDK.

Topics to be covered include the following among other related to the compact/SPICE modeling and its Verilog-A standardization:

• Compact Modeling (CM) of the electron devices
• Advances in semiconductor technologies and processing
• Verilog-A language for CM standardization
• New CM techniques and extraction software
• Open Source (FOSS) TCAD/EDA modeling and simulation
• CM of passive, active, sensors and actuators
• Emerging Devices, Organic TFT, CMOS and SOI-based memory
• Microwave, RF device modeling, high voltage device modeling
• Nanoscale CMOS, BiCMOS, SiGe, GaN, InP devices and circuits
• Technology R&D, DFY, DFT and reliability/aging IC designs
• Foundry/Fabless Interface Strategies (eg: Skywater 130nm CMOS)

List of MOS-AK invited speakers (tentative in alphabetical order) :

• Tim 'mithro' Ansell, Google (US)
• Christian C. Enz, EPFL (CH)
• Brian D. Hoskins, NIST (US)
• Hesham Omran, ASU, (EG)
• Mehdi Saligane, UMICH (US)

Online Abstract Submission is open 

(any related enquiries can be sent to absttracts@mos-ak.org)

Online Event Registration is open 

(any related enquiries can be sent to registration@mos-ak.org)

Important Dates: 

• Call for Papers: Feb. 2022
• 3nd Announcement: April 5, 2022
• Final Workshop Program: April 19, 2022 
• Spring MOS-AK Workshop: April 29, 2022

W.Grabinski for Extended MOS-AK Committee

WG050422

The era of quantum CMOS has started https://t.co/FAvw1rWrS7 #semi https://t.co/kPTmuI1Cci

The era of quantum CMOS has started https://t.co/FAvw1rWrS7 #semi https://t.co/kPTmuI1Cci

— Wladek Grabinski (@wladek60) Apr 5, 2022

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Spain is to spend €11 billion on #semiconductors, says prime minister Pedro Sanchez (pictured) https://t.co/xAvdhExODq #semi https://t.co/GWNXAsUPBR

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— Wladek Grabinski (@wladek60) Apr 5, 2022

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April 05, 2022 at 11:55AM
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[paper] M. Parker, “A sub-terahertz transceiver in 22 nm FinFET,” Nature Electronics, vol. 5, no. 3, pp. 126–126, Mar. 2022, doi: 10.1038/s41928-022-00741-x. https://t.co/Qt8CKHWCoD #semi https://t.co/CliNw0fx4M

[paper] M. Parker, “A sub-terahertz transceiver in 22 nm FinFET,” Nature Electronics, vol. 5, no. 3, pp. 126–126, Mar. 2022, doi: 10.1038/s41928-022-00741-x. https://t.co/Qt8CKHWCoD #semi https://t.co/CliNw0fx4M

— Wladek Grabinski (@wladek60) Apr 4, 2022

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A microprocessor that flexes; Nature Electronics, Published online: 29 March 2022; doi:10.1038/s41928-022-00743-9 https://t.co/XmRtZ1kn7V #semi https://t.co/ZWB7GG4uMc

A microprocessor that flexes; Nature Electronics, Published online: 29 March 2022; doi:10.1038/s41928-022-00743-9 https://t.co/XmRtZ1kn7V #semi https://t.co/ZWB7GG4uMc

— Wladek Grabinski (@wladek60) Apr 3, 2022

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April 03, 2022 at 05:31PM
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Sam Zeloof on Twitter: "looking for a $1M donation to my #semiconductor #research company. I promise I’ll make something cool and change the world etc" https://t.co/KkufqOenvn #semi https://t.co/hpQoy0XpBx

Sam Zeloof on Twitter: "looking for a $1M donation to my #semiconductor #research company. I promise I’ll make something cool and change the world etc" https://t.co/KkufqOenvn #semi https://t.co/hpQoy0XpBx

— Wladek Grabinski (@wladek60) Apr 2, 2022

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April 02, 2022 at 09:36AM
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#MangoPi new hardware is smaller than an SD Card https://t.co/wL6ZddAPUh #semi https://t.co/X1pNq7MnlC

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— Wladek Grabinski (@wladek60) Apr 1, 2022

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