[paper] Open-source Cell Libraries

Chenlin Shi1, Shinobu Miwa1, Tongxin Yang1, Ryota Shioya2, Hayato Yamaki1
and Hiroki Honda1
"CNFET-OCL: Open-source Cell Libraries for Advanced CNFET Technologies"

IEEE Access (2024)

DOI: 10.1109/ACCESS.2024.0429000

1 Department of Computer and Network Engineering, The University of Electro-Communications, Chofu, Tokyo (J)

2 Department of Creative Informatics, Graduate School of Information Science and Technology, Uni Tokyo, Bunkyo (J)

Abstract: In this paper, we propose CNFET-OCL, the first open-source cell libraries for 5-nm and 7nm carbon nanotube field-effect transistor (CNFET) technologies. Our CNFET-OCL is designed to emulate the predictive 5-nm and 7-nm CNFET technologies presented in a published paper. We achieved this by performing a number of SPICE simulations based on an open-source CNFET SPICE model and making certain assumptions used in previous work. Each of our cell libraries includes two types of delay model (i.e., the composite current source and nonlinear delay model), each having 56 typical standard cells, which is sufficient to design various VLSI circuits. CNFET-OCL fully supports both logic synthesis and timing-driven place and route design in the Cadence design flow. Our experimental results demonstrate that CNFET-OCL can achieve performance levels comparable to those reported in previous studies on CNFETs. Consequently, CNFET-OCL can serve as an effective evaluation tool for the CNFET research community.

FIG: I–V characteristics of transistors used in CNFET5, CNFET7 and ASAP7
with cross-section of a CNFET device.

Acknowledgments: This work is partially supported by JSPS KAKENHI under grant number 18K19778 and 23K18461, and VLSI Design and Education Center (VDEC), The University of Tokyo with the collaboration with CADENCE Corporation and Synopsys Corporation. We thank Logic Research Co., Ltd. for helping generate the LIBERTY files and Edanz (https://jp.edanz.com/ac) for editing a draft of this manuscript. We also thank Mr. Dooseok Yoon for his invaluable help with the SPICE netlist simulation of PROBE3.0.

[webinar] Open Source EDA Development of Chips in Europe

Professor Marie-Minerve Louerat, Sorbonne Université-CNRS, GoIT Project, has announced the upcoming webinar on Open Source EDA fostering development of Chips in Europe

"Introduction to the open-source EDA ecosystem"

online webinar to foster engagement for Open-Source EDA and Open-Silicon development in Europe

📅 Tuesday May 14, 2024 🕙 10:00-12:00 (CEST) with Free Online Registration

Workshop Agenda:

• European Semiconductor Design Ecosystem (10 min)
• Matthew Xuereb, European Commission
• Open-Source Semiconductor Ecosystem (15 min)
• Luca Alloatti, Free Silicon Foundation (I) ETS
• Open-Source EDA Software and Semiconductor Design (15 min)
• Jean-Paul Chaput, Sorbonne Université, Coriolis Foundation
• European Roadmap on the Advancement of Open-Source EDA Tools, next steps (15 min)
• Rihards Novickis, Latvian Institute of Electronics and Computer Science
• Q&A session / Feedback (up to 1 hour)

NB: 2nd event - to be announced

Location: Paris, Sorbonne Université

📅 Date: June 18, 2024, before FSiC2024 conference

[IEEE SSCS] “PICO” Open-Source Chipathon

IEEE SSCS “PICO” Open-Source Chipathon

Automating Analog Layout

https://sscs.ieee.org/about/tc-ose/sscs-pico-design-contest

– Sign-Up Deadline: May 10, 2024 –

The IEEE Solid-State Circuits Society is pleased to announce its fourth open-source integrated circuit (IC) design contest under the umbrella of its PICO Program (Platform for IC Design Outreach). While this contest is open to anyone (no restrictions), we encourage the participation of pre-college students, undergraduates, and geographical regions that are underrepresented within the IC design community. 

The goal of this year’s event is to advance the automatic generation and open sharing of analog circuit layout cells to increase our community’s design productivity and to catch up with other fields where sharing and automation is a key enabler of progress (e.g., in machine learning).

Die photo in background courtesy of IBM

Contest Outline

1. Interested individuals sign up using this form by May 10, 2024.
2. Phase 1 (~June): Through a series of weekly meet-ups and training sessions, the participants learn to create basic one- or two-transistor layout generators using Python and open-source CMOS PDKs. Using Jupyter Notebooks hosted on Google Colab allows anyone with an internet connection to participate - no downloads or installations required! Relevant circuit examples can be found in [1], [2]. We will leverage code modules available with the OpenFASoC [3] environment.
3. Phase 2 (~July): Interested participants define larger layout building blocks that they wish to automate (examples: comparator, bandgap, phase interpolator, OTA). Teaming among participants is encouraged to maximize collaboration and learning).
4. Phase 3 (~August-September): Participants implement their generators and submit sample layouts and test structures for potential tape-out to an open-source MPW (tentatively SKY130).
5. Phase 4 (~October-November): A jury evaluates the created generators/layouts and selects the test structures that will be taped out. The teams work together to assemble a shared database with all the designs and to complete the tapeout. Ideally, this phase will involve automated verification through CACE [4] or a similar tool.
6. Phase 5 (TBD): The designs will be tested using lab measurements by a subset of participants and SSCS volunteers with access to lab facilities. Some of the test setups may be available for remote characterization. The obtained measurement data will be added to the repositories containing the layout generators.

 References

[1] H. Pretl, “Fifty Nifty Variations of Two-Transistor Circuits,” MOS-AK Workshop Spring 2022, URL: https://www.mos-ak.org/spring_2022/presentations/Pretl_Spring_MOS-AK_2022.pdf.
[2] H. Pretl and M. Eberlein, "Fifty Nifty Variations of Two-Transistor Circuits: A tribute to the versatility of MOSFETs," in IEEE Solid-State Circuits Magazine, vol. 13, no. 3, pp. 38-46, Summer 2021, URL: https://ieeexplore.ieee.org/document/9523464.
[3] OpenFASoC: Fully Open-Source Autonomous SoC Synthesis using Customizable Cell-Based Synthesizable Analog Circuits, https://github.com/idea-fasoc/OpenFASOC/.
[4] Circuit Automatic Characterization Engine, URL: https://github.com/efabless/cace.

[C4P] OSDA 2024

4th Workshop on Open-Source Design Automation

 OSDA 2024

March 25, 2024, 14:00-18:00

and will be co-hosted with DATE Conference

in VCC in Valencia, Spain

There is no doubt that proprietary EDA tools are successful, mature, and fundamental for hardware development. However, the “walled garden” approach created by closed-source tool flows can hamper novel FPGA/ASIC-based applications and EDA innovation alike by requiring that researchers either operate within the limits of what has already been imagined, or require that they attempt to simulate their effects on incomplete models, potentially leading to incorrect conclusions.

Another recent development has been growing activity in the open-source community to produce open equivalents of EDA tools, as well as efforts to document FPGA architectures. For instance, Yosys has been widely used for behavioral synthesis since 2012 and Project Icestorm, the first fully open-source FPGA design flow has been available since 2015; together they enabled Trenz Electronic’s icoBOARD, a Raspberry Pi accessory that could be programmed entirely using its ARM CPU, a platform not otherwise supported by the vendor. The availability of low-cost FPGA development boards such as the icoBOARD, TinyFPGA, IceZUM Alhambra, the iceBreaker board, amongst others have also played a part in fostering this “Open FPGA” movement. With OpenLANE and the Skywater process development kit, an open-source tool flow emerged that synthesizes RTL models to GDSII, gracefully enabling open-source ASIC design. The advantages of open design automation -- as Linux has provided for operating systems -- are many: unrestricted research and development, improved quality due to competition, teaching benefits, as well as lowering the barrier and risk to entry, and time to market, of start-ups for building novel applications, tools, and silicon. With such an open-source ecosystem in place, ASICs and reprogrammable logic could achieve the same success and inspire the next generation of hardware engineers as the Raspberry Pi has done for software engineers.

OSDA intends to provide an avenue for industry, academics, and hobbyists to collaborate, network, and share their latest visions and open-source contributions, with a view to promoting reproducibility and re-usability in the design automation space. DATE provides the ideal venue to reach this audience since it is the flagship European conference in this field -- particularly poignant due to the recent efforts across the European Union (and beyond) that mandate “open access” for publicly funded research to both published manuscripts as well as software code necessary for reproducing its conclusions. A secondary objective of this workshop is to provide a peer-reviewed forum for researchers to publish “enabling” technology such as infrastructure or tooling as open-source contributions -- standalone technology that would not normally be regarded as novel by traditional conferences -- such that others inside and outside of academia may build upon it.

Topics - we request contributions of the following topics, including but not limited to:

• Open-source EDA tools -- the latest developments, breakthroughs, challenges and surveys on the toolflows required to target real silicon parts: synthesis, verification, place and route, etc.
• Open-source IP -- contributions that enrich the IP ecosystem and reduce the need to “re-invent the wheel”, e.g. PCIe and DDR controllers, debug infrastructure, etc.
• Design methodologies provided as open-source -- such as hardware description languages (e.g. MyHDL, Chisel), domain specific (DSL), high level synthesis (HLS), or asynchronous methods.
• Directions on where the open-source EDA movement should go, current weaknesses in the toolchain, and/or perspectives from industry on how open-source can affect aspects of safety, security, verification, IP protection, time-to-market, datacenter/cloud infrastructure, etc.
• Discussions and case studies on how to license, acquire funding, and commercialize technologies surrounding open-source hardware, which may be different to open software.

Important Dates

Event	Date
Early-Bird submission	Jan. 20, 2024
Early-Bird notification	Jan 23, 2024
Regular submission deadline	Feb. 15, 2024
Regular notification	Feb. 22, 2024
Camera-ready final version	March 16, 2024
Workshop	March 25, 2024, 14:00-18:00

Organizing committee

• Christian Krieg (OSDA and TU Wien, Austria)
• Matthew Guthaus (UC Santa Cruz, USA)
• Claire Xenia Wolf (YosysHQ, Austria)

Program committee

• Andrea Borga
• Jean-Paul Chaput
• Tim Edwards
• Xin Fang
• Francesco Gonnella
• Daniel Grosse
• Matthew Guthaus
• Hipolito Guzman-Miranda
• Steve Hoover
• Tsung-Wei Huang
• Andrew Kahng
• Lucas Klemmer
• Dirk Koch
• Christian Krieg
• Jim Lewis
• Mieszko Lis
• Steffen Reith
• Stefan Riesenberger
• Davide Rossi
• Frans Skarman
• Antonino  Tumeo
• Vamsi Vytla

[paper] How to support open-source software and stay sane

How to support open-source software and stay sane

Anna Nowogrodzki

Nature 571, 133-134 (2019)

DOI: https://doi.org/10.1038/d41586-019-02046-0

Releasing lab-built open-source software often involves a mountain of unforeseen work for the developers.

It’s a familiar problem: open-source software is widely acknowledged as crucially important in science, yet it is funded non-sustainably. Support work is often handled ad hoc by overworked graduate students and postdocs, and can lead to burnout [read more...]