MOS-AK publications

I post an e-mail from Wladek Grabinski:

The MOS-AK San Francisco Meeting presentation are available on-line:
http://mos-ak.org/sanfrancisco/
The authors of selected presentation recommended for further IJNM publication will be informed individually.

Let me once again thank our sponsors, Accelicon and Suss MicroTec for their generous support. In particular, I would like to acknowledge Tim Smith for all local organization and logistic coordination as well as Plamen Minev for opening his NOMA gallery for post MOS-AK reception.

I hope, we will have a chance to meet us soon again at one of coming modeling events:

* Frankfurt/O: March/April 2009; http://www.mos-ak.org/frankfurt_o
* Lodz: June 2009; http://www.mixdes.org
* Athens: September 2009; http://www.mos-ak.org/athens

-- with New 2009 Years greetings - W.Grabinski (for MOS-AK Group)

!!! Szczesliwego Nowego 2009 Roku !!!
!!! Ein Frohes Neus Jahr 2009 !!!
!!! Gelukkig Nieuwjaar 2009 !!!
¡¡¡ Feliz Año Nuevo 2009 !!!
!!! Happy New 2009 Year !!!
!!! Bonne Annee 2009 !!!

RE: Happy new year!

Hello!

let me also send my warm seasons greetings.

I hope, we would have a chance to meet us next year at one of my modeling events:

* Frankfurt/O: March/April 2009; http://www.mos-ak.org/frankfurt_o
* Lodz: June 2009; http://www.mixdes.org
* Athens: September 2009; http://www.mos-ak.org/athens

-- with regards - wladek;

==========================================================
Subscribe: http://groups.google.com/group/mos-ak/subscribe
==========================================================
MOS-AK: www.mos-ak.org
ESSDERC/ESSCIRC Workshops: www.essderc.org
Modeling Book: www.grabinski.ch/mos-ak/book
MIXDES: www.mixdes.org
==========================================================

Happy new year!

We wish all of you a happy holiday season and all the best in 2009!

Memristor

Thanks to the IEEE, who has drawn my attention to this youtube video, where there is a 6-minutes long explanation about what in the **** a memristor is:



By the way,you can find more information in the December 2008 issue of the IEEE Spectrum.

MIXDES 2009

Let me draw your attention to the 16th International Conference Mixed
Design of Integrated Circuits and Systems MIXDES'2009 (www.mixdes.org )
which will be held in ?ódz', June 25-27, 2009. During this conference,
as usually, we will meet at a special session on compact modeling. A
general topic of the session will be "Device level support for emerging
CMOS technologies".

New papers (November 26, 2008)

A brief selection of papers:

Accurate Intrinsic Gate Capacitance Model for Carbon Nanotube-Array Based FETs Considering Screening Effect, (abstract) in Electron Device Letters, IEEE

Analytical Model of Subthreshold Current and Slope for Asymmetric 4-T and 3-T Double-Gate MOSFETs, (abstract) in Electron Devices, IEEE Transactions on

Three-Dimensional Closed-Form Model for Potential Barrier in Undoped FinFETs Resulting in Analytical Equations for VT and Subthreshold Slope, (abstract) in Electron Devices, IEEE Transactions on

A Non-Charge-Sheet Analytic Model for Symmetric Double-Gate MOSFETs With Smooth Transition Between Partially and Fully Depleted Operation Modes, (abstract) in Electron Devices, IEEE Transactions on

Carrier Mobility in Undoped Triple-Gate FinFET Structures and Limitations of Its Description in Terms of Top and Sidewall Channel Mobilities, (abstract) in Electron Devices, IEEE Transactions on

Enjoy your reading!

IEEE IEMDC 2009 FINAL CALL FOR PAPERS

Conference Date: May 3-9, 2009, Miami, Florida USA
Official Submission Site: http://www.iemdc2009.org

Submission of Abstracts and Digests December 5, 2008
Notification of Acceptance February 2, 2009
Submission of Final Papers March 9, 2009


The IEEE International Electric Machines and Drives Conference provides an international forum for sharing experience, new ideas, and developments in design, operation, analysis, and practical application and optimization of electric energy and drive systems and their components. IEMDC is a venue for users, designers and manufacturers, and analysts of electric machines and drives and their related power electronics and controls. The conference is jointly sponsored by the IEEE Power and Energy, Industrial Electronics, Industry Applications, and Power Electronics Societies. Several tutorials in the form of full day and half day short courses will be offered during the day on May 3, 2009.

In addition to the subjects identified above, the conference will have papers and plenary presentations by recognized experts to highlight various aspects of electric machines and drives, such as automotive applications, renewable and alternate energy applications. Of interest are topics related to PM and IPM motor drive systems, fault tolerant operation and
survivability, diagnostics and prognostics of machine drive systems, bearings current, sensorless methods, and turbogenerator operation and maintenance. Also of interest are papers in areas including novel designs and applications of machines and drives, hybrid electric vehicles, naval and aircraft power systems.  Papers addressing these and related topics are encouraged.

Information for Authors

Authors wishing to submit papers are invited to submit an abstract of 200 words single spaced and a digest of five pages, including text, tables, and figures, at the conference website: http://www.iemdc2009.org. The style for the abstract and digest are posted on the website. The style and model paper for the final version will be posted on the website shortly. The Abstract and Digest should be in a single-column pdf format in 12 point serif text, such at Times New Roman and double spaced on either A4 or US letter-size pages. These format requirements are necessary for the peer review stage. Contact information for the corresponding author should be
indicated on the abstract. No author information should appear on the 5 page digest. Submissions should indicate a preference for oral or poster presentation in case of acceptance however; the final decision on the presentation format will be decided by the technical program committee. All
submissions will be made through a web-based system. Acceptance notification will contain instructions for final paper preparation.

Registration and payment of fees by at least one author is required for inclusion in the conference proceedings.

Conference Record: The papers presented during the conference will be posted on IEEE Xplore and be cited in EI (Engineering Index).

This Conference Theme is “Renewable Energy Systems for Today & Tomorrow”

Contact Information: The conference website is located at:
http://www.iemdc2009.org. The preferred mode of contact is e-mail. For general conference information, please address comments and questions to:

IEEE IEMDC-2009 Conference Secretariat
Department of Electrical & Computer Engineering
10555 W. Flagler Street, Room EC-3960
Florida International University
Miami, Florida 33174 USA
Secretariat@iemdc2009.org


Short Courses: If you are interested in offering a short course during IEMDC 2009, the short course proposal deadline: December 5, 2008. Please use the appropriate area on the website at http://www.iemdc2009.org

Important Dates
Submission of Abstracts and Digests December 5, 2008
Notification of Acceptance February 2, 2009
Submission of Final Papers March 9, 2009
Short Course Proposal Deadline: December 5, 2008

More job offers!!

Crisis? Who said crisis?. It seems that a guy called Manoj Gupta is looking again for people to work as device modeling engineers. Have a look at the linkedIn network here. And the only details I have are those posted here:

"Candidate will lead projects in Bipolar/BiCMOS/HVMOS/DMOS process analysis
and device characterization, as well as development of the SPICE model and
simulation library. Candidate should have an MSEE or PhD in EE with an
emphasis on device physics. Candidate will need at least 5 plus years
experience in characterization and modeling of Bipolar and MOS devices, with
good knowledge of modeling tools, IC technology, basic circuit design, and
programming."

If you know something more, share your knowledge!

1st International MOS-AK Workshop in San Francisco // 2nd announcement

--- 1st International MOS-AK Workshop
--- Saturday, 13 December 2008; the Westin St Francis Hotel in San Francisco
--- 2nd announcement

1st International MOS-AK Workshop on compact modeling, will be organized
in San Francisco (co-located with the CMC Meeting and IEDM Conference) with
aims to strengthen a network and discussion forum among experts in the
field, create an open platform for information exchange related to
compact/Spice modeling, bring people in the compact modeling field together,
as well as obtain feedback from technology developers, circuit designers,
and CAD tool vendors. The topics cover all important aspects of compact
model development, implementation, deployment and standardization within the
main theme - compact models for mainstream CMOS/SOI circuit simulation. The
specific workshop goal will be to classify the most important directions for
the future development of the compact models and to clearly identify areas
that need further research. This workshop is designed for device process
engineers (CMOS, SOI, BiCMOS, SiGe) who are interested in device modeling;
ICs designers (RF/IF/Analog/Mixed-Signal/SoC) and those starting in that
area as well as device characterization, modeling and parameter extraction
engineers. The content will be beneficial for anyone who needs to learn what
is really behind IC simulation in modern device models. The technical
program of MOS-AK Workshop consists of one day of tutorials given by noted
academic and industry experts, also a panel session is foreseen. The meeting
program will be availabe soon at:
http://www.mos-ak.org/sanfrancisco/

Tentative list of the speakers already includes following names
(in alphabetic order):
* Henok Abebe, MOSIS;
* Marc Vanden Bossche, NMDG;
* Gennady Gildenblat, ASU;
* Hans J. Mattausch, U.Hiroshima;
* Colin Mcandrew, Freescale;
* Marek Mierzwinski, Tiburon;
* Paul Jespers, UC Louvain;
* Sadayuki Yoshitomi, Toshiba;
* Xisheng Zhang, Accelicon;

--- Important dates:
--------------------
* Final workshop program - Dec.1
* 1st International MOS-AK Workshop - Dec.13
at the Westin St Francis Hotel in San Francisco

Organizing Committee:
---------------------
* Hisayo S. Momose; Toshiba; Session Chair
* Herve Jaouen, STM; Session Chair
* Ehrenfried Seebacher, austriamicrosystems; Panel Session Chair
* Tim K. Smith; Accelicon; Local Arrangement Chair
* Wladek Grabinski, GMC Suisse; Workshop Manager
==========================================================
Subscribe: http://groups.google.com/group/mos-ak/subscribe
==========================================================
MOS-AK: www.mos-ak.org
ESSDERC/ESSCIRC Workshops: www.essderc.org
Modeling Book: www.grabinski.ch/mos-ak/book
MIXDES: www.mixdes.org
======================================================xac=

2009 Workshop on Compact Modeling (WCM'09)

The 2009 Workshop on Compact Modeling (WCM 2009) will be held in the George R. Brown Convention Center in Houston (Texas, USA) on May 3-7 2009, as part of the Nanotech 2009 Conference.

The Workshop on Compact Modeling (WCM) is the largest event devoted to the Compact Modeling field. WCM has become a very important open forum for discussion among experts in this field as well as feedback from technology developers, circuit designers, and EDA tool vendors.

The suggested topics include all important aspects of compact model development and application: intrinsic models, extrinsic/interconnec models, atom/quantum models, statistical models, and model extraction and interface.

A limited number of papers will be selected for oral presentations and the remaining accepted papers will be planned for poster presentations with oral briefing. The deadline for abstract submission is November 12 2008.

The Chairman of WCM is Professor Xing Zhou (from Nanyang Technological University, Singapore). He was the person who created WCM and has made this workshop very successful.

I think that it is a must for Compact Modeling researchers to attend WCM. Many of the last advances in this field are presented there.

An interesting discussion

That is, if someone cares to post... I've get this thread from LinkedIn:

There seem to be a boom in requirement for Device modeling Engineers worldwide from Big Semiconductor Companies as well as small players. Is there a possibility of offshore work in this area too?

You can follow (and post) the discussion here.

Papers on the IEEE Electron Device Letters vol 29 (11), nov 2008

Two interesting papers, I think:

A Variational Approach to the Two-Dimensional Nonlinear Poisson's Equation for the Modeling of Tunneling Transistors

and

Effect of Gate Leakage in the Subthreshold Characteristics of AlGaN/GaN HEMTs

More job offers from linkedIn

I copy the text from LinkedIn:

Looking for R&D Scientist for transistor level (MOSFET, FinFET, etc) research.

- PhD or MSc Microelectronics / Semiconductor Physics or equivalent
- Device Modeling/Simulation (TCAD)
- R&D experience with Universities or Fab/Foundry

Multiple vacancies in East Asia. Email alex at maxima.com.sg for details.

Posted 5 days ago... so hurry up!

As before, we have no relation with this offers, other than passing on the information. For more details, email alex at maxima.com.sg, not us!

Update on the MOS-AK

	1st International MOS-AK Workshop on compact modeling, will be organized in San Francisco (co-located with the CMC Meeting and IEDM Conference) with aims to strengthen a network and discussion forum among experts in the field, create an open platform for information exchange related to compact/Spice modeling, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD tool vendors. The topics cover all important aspects of compact model development, implementation, deployment and standardization within the main theme - compact models for mainstream CMOS/SOI circuit simulation. The specific workshop goal will be to classify the most important directions for the future development of the compact models and to clearly identify areas that need further research. This workshop is designed for device process engineers (CMOS, SOI, BiCMOS, SiGe) who are interested in device modeling; ICs designers (RF/IF/Analog/Mixed-Signal/SoC) and those starting in that area as well as device characterization, modeling and parameter extraction engineers. The content will be beneficial for anyone who needs to learn what is really behind IC simulation in modern device models. The technical program of MOS-AK Workshop consists of one day of tutorials given by noted academic and industry experts, also a panel session is foreseen. The program will be availabe soon at: http://www.mos-ak.org/sanfrancisco/
Speakers:	Tentative list of the speakers already includes following names (in alphabetic order): Henok Abebe, MOSIS; Gennady Gildenblat, ASU; Hans J. Mattausch, U.Hiroshima; Colin Mcandrew, Freescale; Marek Mierzwinski, Tiburon; Paul Jespers, UC Louvain; Sadayuki Yoshitomi, Toshiba; Xisheng Zhang, Accelicon;
Dates:	2nd announcement - Nov.10 Final workshop program - Dec.1 1st International MOS-AK Workshop - Dec.13 at the Westin St Francis Hotel in San Francisco
Place:	The Westin St. Francis 335 Powell Street, San Francisco California 94102
Registration:	On-Line registration is available
Committee:	Hisayo S. Momose; Toshiba; Session Chair Herve Jaouen, STM; Session Chair Ehrenfried Seebacher, austriamicrosystems; Panel Session Chair Tim K. Smith; Accelicon; Local Arrangement Chair Wladek Grabinski, GMC Suisse; Workshop Manager

Open Ph D Student position in semiconductor device modeling

We offer one scholarship for a Ph D student position in the Department of Electronic Engineering in the Universitat Rovira i Virgili (URV), in Tarragona, Spain.

The duration of the grant will be at least three years, possibly four. The monthly salary will be 1000 Euro/month.

The candidate should have a Bachelor or Master degree in Electrical Engineering, Electronic Engineering, Telecommunication Engineering or Physics. A good background in Semiconductor Physics, Semiconductor Devices, or Integrated Circuit Design will be highly appreciated.

The work to be done by the candidate will be focused on the development of new techniques of characterization and modeling of novel advanced semiconductor devices. It will be related to two European projects in which the hosting group participates.

To get more information about our areas of research in the DEEEA, you can visit the website:

http://sauron.etse.urv.es/DEEEA/angles/recerca/nephos/

Required documents for applicants


Applicants are required to send to the address specified below the following documents (in English or Spanish):

1) a full Curriculum Vitae (as complete as possible)

2) Copy of their diploma

3) copy of their passport

4) Academic certificate including their marks (it is important that the number of hours or credits of each subject appears). It is also very important that the document specifies what is the minimum mark for passing a given subject and what is the maximum mark that can be awarded.

Candidates can send their documents by e-mail, but in fact we will need original and copy documents (or authenticated copy) of them; therefore we also suggest to send the documents by postal mail.

Applications should be sent to:

Prof. Benjamin Iñiguez
Department of Electronic, Electrical and Automatic Control Engineering

Universitat Rovira i Virgili (URV)

Avinguda Països Catalans, 26
43007 Tarragona (Spain)
Email: benjamin.iniguez@urv.cat
Tel: +34977558521 Fax:+34977559610

Deadline: November 8 2008

You can contact Prof. Benjamin Iñiguez (Benjamin.Iniguez@urv.cat) for more information

Tarragona is a medium city (100000 inhabitants) with a Mediterranean climate and many recreation opportunities (nice beaches, theme parks, nature preserves, mountain hiking, touristic resorts and facilities). It is located 100 km Southwest of Barcelona, and it is very well connected by train, bus, highways and even low cost flights from its own airport. Additional information about the University and the department can be found at: www.urv.cat and sauron.etse.urv.es

MOS-AK in San Francisco (USA)

--- 1st International MOS-AK Workshop
--- Saturday, 13 December 2008; the Westin St Francis Hotel in San Francisco
--- 1st announcement

 1st International MOS-AK Workshop on compact modeling, will be organized in San Francisco (co-located with the CMC Meeting and IEDM Conference) with aims to strengthen a network and discussion forum among experts in the field, create an open platform for information exchange related to compact/Spice modeling, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD tool vendors. The topics cover all important aspects of compact model development, implementation, deployment and standardization within the main theme -compact models for mainstream CMOS/SOI circuit simulation. The specific workshop goal will be to classify the most important directions for the future development of the compact models and to clearly identify areas that need further research. This workshop is designed for device process engineers (CMOS, SOI, BiCMOS, SiGe) who
are interested in device modeling; ICs designers (RF/IF/Analog/Mixed-Signal/SoC) and those starting in that area as well as device characterization, modeling and parameter extraction engineers. The content will be beneficial for anyone who needs to learn what is really behind IC simulation in modern device models. The technical program of MOS-AK Workshop consists of one day of tutorials given by noted academic and industry experts, also a panel session is foreseen.

The meeting program will be availabe soon at:
http://www.mos-ak.org/sanfrancisco/

Tentative list of the speakers already includes following names (in alphabetic order):
   * Henok Abebe, MOSIS;
   * Gennady Gildenblat, ASU;
   * Hans J. Mattausch, U.Hiroshima;
   * Colin Mcandrew, Freescale;
   * Marek Mierzwinski, Tiburon;
   * Paul Jespers, UC Louvain;
   * Sadayuki Yoshitomi, Toshiba;
   * Xisheng Zhang, Accelicon;

--- Important dates:--------------------
   * 2nd announcement - Nov.10
   * Final workshop program - Dec.1
   * 1st International MOS-AK Workshop - Dec.13 at the Westin St Francis Hotel in San Francisco

Further information including recommended hotels and driving directions will be posted at the web site, soon; please visit regularly: http://www.mos-ak.org

Organizing Committee:
   * Hisayo S. Momose; Toshiba; Session Chair
   * Herve Jaouen, STM; Session Chair
   * Ehrenfried Seebacher, austriamicrosystems; Panel Session Chair
   * Tim K. Smith; Accelicon; Local Arrangement Chair
   * Wladek Grabinski, GMC Suisse; Workshop Manager

Another job offer in compact modelling

Well, it seems we're in a boom... I post another one taken from LindekIn:

Requirement:
This work involves theoretical understanding of quantum effects in 22 nm scale devices; these include carrier transport, geometry and material dependent and structure calculations, role of metal and high-k material
interfaces, role of high-k on bandstructure and related phenomena to enable
development of 22 nm scale devices.

Candidates to be considered for this area are required to have a strong understanding of semiconductor physics and quantum effects in nanodevices.
The candidates are also expected to have a strong background in devices
physics, electronic structure methods, numerical programming, hands on
experience with ab-initio modeling tools, and computer programming in mixed language environment.

Should have Ph.D/MS in Physics, Electrical Engineering, Applied Physics, Computer Science, or Theoretical Materials Science.

For more details, visit the page where the offer is posted.... and polish your CV!

Job on Compact Modeling

Here you have an offer I've got from a groupmail in LinkedIn (please note that we're only posting it because it seems interesting to all those working on Compact Modeling, and looking for a change of position. We're in no way related to the people making the offer):

Looking for R&D Engineers for transistor level (MOSFET, FinFET, etc) research.(View discussion in LinkedIn.)

- PhD or MSc Microelectronics / Semiconductor Physics or equivalent
- Device Modeling/Simulation (TCAD)
- R&D experience with Universities or Fab/Foundry

Multiple vacancies in multiple Asian locations available. Email alex@maxima.com.sg for details.

[mos-ak] Edinburgh on-line publications

I post an e-mail from Wladek Grabinski (MOS-AK), in the MOS-AK googlegroups:

The MOS-AK Edinburgh Workshop's presentations are available on-line
please visit:
http://www.mos-ak.org/edinburgh/

I would like to take this opportunity and thank all speakers and presenters for their valuable contribution to the MOS-AK/ESSDERC/ESSCIRC workshop.

Let me also acknowledge the workshop sponsors (Accelicon, Tanner, X-FAB and SUSS) for their generous financial support as well as the conference organizers for their support, smooth organization and perfect logistic of our modeling event, which is an unique platform for continuous promotion of local, European compact modeling activities.

You are more than welcome to attend and contribute to coming events:

# 1st International MOS-AK Workshop in San Francisco
http://www.mos-ak.org/sanfrancisco/

# MOS-AK Spring'09 Meeting
http://www.mos-ak.org/frankfurt_o/

On the way to Plastic computation

I've found (out of sheer luck, I must say) a very nice paper in the IEEE Circuits and Systems Magazine. The topic: Plastic electronics, one of my fixations, even if I think that it will be used mainly for large-area applications. The paper I'm talking about (On the way to plastic computation) is a quite complete paper, from fabrication to circuit design using a commercial soft (Cadence).

The only point I find improvable (a lot) is that they are not doing a good job in the references, and they miss a lot of the field. However, as I've said, the paper is very interesting (not for the technical aspects, but this is a magazine...), since it's the first time I see a paper presenting the full design cycle...

2009 Symposium on VLSI Technology

The 2009 IEEE Symposium on VLSI Technology will be held from June 15 to June 17 at Rihga Royal Hotel in Kyoto, Japan.

The IEEE Symposium on VLSI Technology is one of the most prestigeous conferences on VLSI devices and processes. It is also a very competitive and tough conference. Papers should always be innovative enough regarding VLSI devices. Some of the topics explicitly mentioned in the Call for Papers are "processes and device modeling of VLSI devices" and "theories and fundamentals" related to VLSI devices. Therefore, researchers in device modeling (including compact modeling) can submit papers to the IEEE Symposium on VLSI Technology, but it should be remarked that these models or theories should be real breakthroughs.

The deadline is January 14.

There will be a Best Student Paper Award. The Symposium will cover the travel mexpenses and registration fee for the award recipient to attend the 2009 Symposium.

The IEEE Symposium on VLSI Technology will be held in conjunction with the IEEE Symposium on VLSI Circuits, which is one of the top conferences in the field of integrated circuits. This Symposium is also very demanding and competitive. Papers should be really breakthroughs to be accepted.

Besides, a satellite workshop, the 2009 Silicon Nanoelectronics Workshop, will be held at the same location as the VLSI Symposia on June 13-14 2009.

Well, despite the symposium is so demanding, it is worthy to work hard to make a suitable paper for this Symposium. And it is also a good opportunity to enjoy some days in Kyoto, one of the most beautiful cities in Japan!

IEEE TED Special issue on Compact Interconnect Models for Giga Scale Integration

This Special Issue in IEEE Transactions on Electron Devices will be devoted to the research and development activities on emerging compact interconnection models for circuit simulation for the 65 nm technological dode and below.

Topics include compact models for RLCK interconnects, Cu/low-K technologies, Carbon nanotube interconnects and Graphene Nano-Ribbon interconnects, RF and Microwave, 2D/3D compact interconnect models, interconnect modeling for SoC design, interconnect variability and statistical modeling,...

The deadline for paper submission is January 16 2009.

Postdoc position on compact device modeling in Spain

A postdoc position is open in the Department of The Electronic, Electrical and Automatic Control Engineering in the Universitat Rovira i Virgili (Tarragona, Spain). This position is funded by a European project of the type called Marie-Curie Industry Academia Partnership and Pathwatys.

The candidate should have a Ph D in Electrical Engineering, Electronic Engineering, Telecommunication Engineering, Physics, or related disciplines.

The candidate should have enough research experience in the field of semiconductor devices, and must have a very good knowledge of the physics of electron devices. The research project to be carried out can be adapted to the candidate's profile. In any case, it will be related to the European project which will fund this position. Our contribution in these projects is the physics and modeling (in particular compact modeling) of the novel devices addressed by this European project: multi-gate MOSFETs (FinFETs, DG MOSFETs,...), High Voltage MOSFETs and advanced HEMTs.

The postdoc position, which will be a contract, will have a duration of at least 18 months (maybe up to 24 months). The net salary will be around 2000 Euro/month.

Interested applicants should send me their CV by e-mail.
DEADLINE TO RECEIVE APPLICATIONS: October 31 2008

MY E-MAIL ADDRESS IS: benjamin.iniguez@urv.cat

Address:
Benjamin Iñiguez
Nanoelectronics and Photonics Systrems Group (NEPHOS)
Department of Electronic Engineering
Universitat Rovira i Virgili (URV)
Avinguda dels Paisos Catalans 26
43007 Tarragona
SPAIN.

ISCAS'09

The 2009 IEEE International Symposium of Circuits and Systems (ISCAS 2009) will be held in Taipei (Taiwan), on 24-27 May 2009. It will be hosted by the hosted by the National Cheng Kung University.

ISCAS is the largest conference in the area of Circuits and Systems. It is sponsored by the IEEE Circuits and Systems Society. Prestigeous speakers in this field are always invited.

ISCAS 2009 will focus on circuits and systems for Human Centric Smart Living Technologies, including mobile communications, multimedia systems, sensor interface, and biosystems.

The deadline for regular paper submission is October 10 2008 As indicated in the Call for Papers, the scope of ISCAS 2009 includes all topics related to integrated circuits and systems. Papers on compact modeling for circuit design are considered to address some of the topic of the call. In fact, every year a number of interesting papers on compact modeling are presented at ISCAS.

It is important to mention that in ISCAS posters are very well considered, as important as oral presentations. Many authors choose poster as their presentation format.

On the other hand, a "a very entertaining social program is planned. Special tours to tourist attractions will be available to the Symposium attendees and their guests." It Sounds promising, anyway.

ITC'09

The 5th International TFT Conference (ITC'09) will take place in the École Polytechnique (near Paris, France) on March 5-6 2009.

ITC is an annual conference which addresses all topics related to Thin Film Transistors (TFTs), from process to circuits, also including simulation and compact modeling.

Abstracts should be submitted not later than November 30 for evaluation.

A number of talks will be given by prestigeous invited speakers.

Key Dates / Schedule
First Call-for-Papers.......................................................................Sep.15, 2008
Submission of Short Abstract........................................................Nov.30, 2008
Acceptance Notification...................................................................Jan.1, 2009
Submission of camera ready manuscript..........................................Feb.1, 2009
Advance Registration.......................................................................Feb.1, 2009

Separate Cover letter
Title of Paper Oral/Poster Preference
Full name, complete mailing address, email address, telephone and fax number of the principal author
Name, Affiliation, city, state, country of additional authors

Abstract
Objective and Background: Briefly describe the goals and intent of your project and give background
factors that led to the new results
Results: Describe, in detail, the specific results that will be presented at the ITC’09.
Impact: Discuss the significance of your work and compare your findings with previously published
work.
All interested authors are requested to submit abstracts for evaluation via the ITC ’09 web site.

No doubt ITC 2009 will be a very interesting conference. Besides, ITC '09 will be held jointly with the SID Mid-Europe Chapter Spring Meeting, an annual meeting attracting many European display professionals.

IRPS 2009

The 2009 IEEE International Reliability Physics Symposium (IRPS) will be held in Montreal, Quebec, Canada, on April 26-30 2009. The venue will be The Fairmont Queen Elizabeth hotel.

For over 40 years, IRPS has been the premier conference for engineers and scientists to present new and original work in the area of microelectronic device reliability. IRPS is now co-sponsored by the IEEE Reliability Society and the IEEE Electron Devices Society. This co-sponsored event has drawn participants from the United States, Europe, Asia and all other parts of the world. IRPS 2009 promotes the reliability and performance of integrated circuits and microelectronic assemblies through an improved understanding of failure mechanisms in the user’s environment, while demonstrating the latest state-of-the-art developments in electronic reliability.

The focus of the symposium is the 3-day plenary/parallel sessions featuring original work that identifies new microelectronic failure or degradation mechanisms, improves understanding of known failure mechanisms, demonstrates new or innovative analytical techniques, or demonstrates ways to build-in reliability. Specific areas to be addressed during the 2009 IRPS are reliability concerns associated with silicon (integrated circuits, discrete devices, MEMS), non-silicon (bipolar, BiCMOS, LEDs and diode lasers, optical fiber and flat panel displays), and emerging technologies including organic electronics and nanotechnology.

The deadline for abstract submission is October 3 2008.

In the Call for Papers, it is said that IRPS can accept papers which "identify new or improve our understanding of the physics of failure and modeling of mechanisms in electronic and optoelectronic devices, materials, and systems".

Therefore, IRPS is a very attractive conference to present results on modeling of failure mechanisms.

Other opportunities at the symposium include:

• A 2-day Tutorial Program. Attendees have the opportunity to learn a new area in some technical depth from an industry expert or brush up on the fundamentals with introductory tutorials. There are typically about 20 tutorials that are offered on topics ranging from back-end reliability to gate dielectric and transistor reliability to circuit/product reliability to assembly/ packaging reliability.



• Reliability Year-In-Review Seminars. These seminars provide a summary of important work published from the previous year in key reliability areas. Industry experts serve as the “tour guide” and save you time by collecting and summarizing this information to bring you up to date in a particular area as efficiently as possible.



• Evening Session Workshops enhance the synergy of the symposium by affording the attendees an opportunity to meet in informal groups to discuss key reliability physics topics with the guidance of experienced moderators. Some of the workshop topics are directly coupled to the tutorial program to allow more discussion on a particular topic.



• Equipment Demonstrations held in parallel with tutorials and technical sessions are a unique aspect of this symposium. Manufacturers of state-of-the-art analytical and test and stress equipment are on hand to demonstrate their products and systems to individuals and small groups. Attendees are encouraged to bring samples or questions for onsite analysis and discussion.



• An Evening Poster Session has become an important part of the IRPS for authors and attendees to discuss recent research and results in a very interactive environment.

EDS Mini-Colloquium on New Frontiers on Compact Modeling

The IEEE Electron Device Society (EDS) organizes Mini-Colloquium (MQ) on New Frontiers on Compact Modeling on October 10 in Santa Clara University, Santa Clara CA, USA.

This MQ is focused on the emerging compact device and interconnect models. Six EDS distinguished lecturers have been invited:

J. J. Liou: "Compact modeling of silicon controlled rectifier for electrostatic discharge (ESD) computer aided design applications"

M. J. Deen: "Noise issues in advanced silicon devices and circuits"

N. Sadachika: "Modeling and characterization of RF/analog and noise using HiSIM2"

B. Yu, Y. Taur, J. Song: "Compact modeling of multiple-gate MOSFETs"

L.F. Register: "Nanoscale MOSFET physics: Observations from non-compact modeling studies"

P.K. Yu: "Wafer bonding for heterogeneous integration"

The Chair person will be Samar Saha, IEEE EDS Compact Modeling Technical Committee Chair, from Silterra USA Inc., San Jose, CA.

MOS-AK Meeting in San Francisco!

For the first time there will be a third MOS-AK meeting in one year, and for the first time, the MOS-AK Meeting will be held outside Europe!

In December 2008 a MOS-AK meeting will take place in San Francisco, California, co-located with two important events: the Compact Modeling Council (CMC) Meeting and IEDM'2008.

The call for abstracts is open. If you are interesting in making one presentation, please contact Wladek Grabinski: ")'>

The MOS-AK meeting is one of the main forums on compact modeling in Europe. So far, two editions of the meeting were held: one in spring and another one in September, co-located with the ESSDERC and ESSCIRC conferences. Of course, most of the participants use to be from Europe. It will be very interesting to have a MOS-AK meeting in the US, and have an active participation of compact model developers from America!

"Be Flexible" 2008

The 2008 "Be Flexible" Forum will be held in Munich (Germany) on December 2-3 2008 at the Hotel Le Meridien (Munich).

This Forum `be-flexible´ was created by Fraunhofer IZM-Munich to deal with the most recent research and innovations in the world of flexible electronics. It is an interesting event for exchanges of experiences of scientists, applied researchers, equipment suppliers and users in flexible electronics. It is also a good opportunity to meet people from the leading companies and suppliers.

The Forum will consist of two Workshops: Thin Semiconductor Devices (December 2) and Flexible Electronics Systems (December 3). Some interesting papers will be presented.

Besides, December 4 will be an Open Day to visit the Fraunhofer IZM facilities.

Global Plastic Electronics Conference

The 4th Global Plastic Electronics Conference and Showcase will be held in Berlin, Germany, on October 27-29 2008. The venue will be the Maritim Hotel Berlin.

The program consists of nine parallel symposia: Flexible Displays, Inorganic-Organic Hybrids, Lighting & Signage, Bateries & Printed Power, Organic Photovoltaics, Organic Based Sensors, Labels & Tags, and Smart Textiles.


The Global Plastic Electronics Conference and Showcase will be a very appropriate place to learn about the recent advances on plastic electronics, and also to do networking. The plenary speakers are leading authorities in the field, as well as some of the presenters.

The Call for Posters is still open! It is a good oportunity to present a scientific poster and have a chance to meet the leaders in plastic electronics.

Besides, more than 30 companies will participate in the Showcase. As said in the brochure, Science and Industry will meet in this conference.

RFIC'09

The 2009 IEEE RFIC (Radio Frequency Integrated Circuits) Symposium will be held in Boston, Massachussets, on June 7-9 in conjunction with the IEEE MTT-S International Microwave Symposium (IMS), as part of the Microwave Week 2009.

The IEEE RFIC Symposium is one of the most important IEEE conferences dedicated to the latest innovations in RF and microwave integrated circuits.

The technical areas of RFIC 2009 include RFIC design, RFIC circuits, design methodology, system engineering, RF testing and packaging... And I wish to hightlight that one of the topics explicitly mentioned in the Call for Papers is "Modeling and CAD: RFIC Modeling, Characterization of Active and Passive Devices".

Certainly, RFIC'08, as well as IEEE MTT-S IMS, will allow an easy interaction between high-frequency compact model developers and their potential users.

The deadline for paper submission is January 6 2009.

IMS'09

The IEEE MTT-S International Microwave Symposium 2009 (IMS 2009) will be held in Boston, Massachussets from June 7 to June 12 2009.

IMS is the largest conference in the field of RF and microwave theory and techniques.

IMS'08 will include workshops, short courses, panels and special sessions

In such a large conference, there are many parallel sessions. The scope of IMS is large, and papers on compact modeling of semiconductor devices in the RF and microwave regime can be presented at IMS. In fact, IMS is a very adequate forum for that, because of the presence of the potential users of the device models (designers of RF and microwave circuits).

IMS will be part of the Microwave Week 2009, which will also include a microwave exhibition, the RFIC Symposium and the ARFTG Conference.

The deadline for paper submission is December 8 2009.

Last but not least, IMS'08 includes a very interesting social programme.
Certainly Boston is an exciting city that offers many places and activities to enjoy!

EUROSOI 2009

The 2009 EUROSOI Workshop will be held at Chalmers University, Göteborg (Sweden) on January 19-21 2009.

The EUROSOI Workshop started as an event related to a former Coordination Action (called EUROSOI) funded by the European Commission. This Thematic Network, which includes most of the European teams working on SOI technology, will continue to exist at least until 2011, under the name of EUROSOI+, receiving more funding from the European Commission.

The EUROSOI Workshop has become an international forum to discuss the recent advances on all aspects of SOI technology: materials, devices, modeling, simulation and circuits.

EUROSOI 2008 will be organized by the Chalmers University. The Chairman is Prof Olof Engström, a recognized researcher in nanoscale semiconductor devices, including SOI technology.

The deadline for abstract submission is November 15 2008

Topics include all areas related to SOI technology, devices and circuits. The "SOI MOSFET modeling" topic is explicitly mentioned.

Göteborg is a leading conferences and event city in Europe. There is a strong joint commitment between the business community and the city council to support major events and conferences offering professionalism and excellent organizational skills.

Do not expect a very nice weather in Göteborg in January, but there are many things to see and enjoy in Göteborg.

ISPSD'09

The 21st IEEE International Symposium on Power Semiconductor Devices and ICs will take place in Barcelona (Catalonia, Spain) on June 14-18.

The deadline for abstract submission is October 24 2008.

ISPSD is the main international conference on the areas of power semiconductor devices, power integrated circuits, their hybrid technologies, and applications.

Topics include: processes, materials, CAD/Simulation, devices, power ICs, packaging and applications.

For researchers interested in compact modeling of power semiconductor devices, ISPSD is a top event to present and get to know the last results in this field. "Device & circuit simulation" is explicitly mentioned as one of the subtopic in the "CAD/Simulation" topic. Compact modeling fits very well this subject. And of course, there is a subtopic of "Modeling" in the "Device" topic.

The Conference will take place mainly at the Axa Winterthur Auditorium but some parallel sessions will be held at the NH Constanza Hotel which is just beside the Auditorium.

Certainly Barcelona is a wonderful place to have such an important event. There are many superb attractions in Barcelona: historical landmarks, the well-known modernistic buildings in Gaudi-style, the "Barri Gòtic" (middle-age downtown), the Museum of Fine Arts, or the stadium of the Barça Football Club. And one can find nice beaches very close to Barcelona. The weather in June is usually very good, warm enough to go to the beach, without been too hot.

Position in CMOS Compact Modelling

The IHP - Innovations for High Performance Microelectronics (Frankfurt Oder, Germany) invites applications for a position in CMOS Compact Modelling and Technology Support.

The IHP is seeking a candidate with a Master degree in Electrical Engineering or Physics. The main tasks will be:

The main tasks will be:

- SPICE compact modelling of CMOS based devices in IHPs 0.25µm and 0.13µm
technologies

- Electrical measurements and characterization on device level

- Automation of modelling and measurement procedures

- Support statistical analysis of electrical test data

The successful candidates must be highly motivated with basic knowledge in semiconductor device physics and electrical measurement and characterization.

Applicants have to send their application letter/e-mail by September 22, 2008 (if they arrive a few days later they may be considered too) including CV, copies of (scanned) certificates, and addresses of at least one referee to:

Dr. Christel Quick

IHP GmbH

Im Technologiepark 25

15236 Frankfurt (Oder)

Germany

Phone: +49 335 5625 330

Fax: +49 335 5625 666

Email: quick@ihp-microelectronics.com

The IHP is a non-profit making organization which pursues interdisciplinary application-oriented research in the fields of high performance microelectronics and communication, particularly Materials Research, Technology Research, Circuit Design and System Design.

This position offers a unique opportunity to work at the forefront of semiconductor technology in an upcoming new field. The IHP offers a challenging, multinational environment, with excellent career prospects.

IEEE 2009 ICMTS Call for Papers

The IEEE 2009 ICMTS has launched the final call for papers (deadline: Sept. 15, 2008). The complete Call for Papers is on their website at: http://www.see.ed.ac.uk/ICMTS. Authors are asked to submit a two or three page extended abstract in PDF file format (font-embedded) including a 500- to 1500-word summary, major figures, and data for review.

This edition will be held between March 30 – April 2, 2009, Mandalay Beach Resort, Oxnard, CA, USA, and there is a suggested topic including "Device and Circuit Modeling, Parameter Extraction", so it seems a nice opportunity to visit the USA, and California.... (no links included, because it is too well known a location)... but I include a picture of the hotel:


tempting, isn't it?

Post Doctoral Fellowship at UNIK (Norway), in Advanced CMOS Device Modeling

Position Description: One Post Doctoral fellowship for 18 months in the research group of Professor Tor A. Fjeldly in the area of advanced electronic device modeling, simulation and characterization.

The candidate will work at UNIK - University Graduate Center (www.unik.no)located near Oslo. UNIK is affiliated with University of Oslo (www.uio.no) and Norwegian University of Science and Technology (NTNU) (www.ntnu.no).
Terms of Employment: The salaries and terms at UNIK are in accordance with Norwegian governmental regulations. The annual salary for the post doctoral fellow is 435 000 NOK (about 81 000 USD as of mid-August 2008), including five weeks per year of paid vacation per year of actual service. Health benefits and full salary during illness are provided.

Project: The position is financed by the European Union project COMON - Compact Modelling Network, which is coordinated by Prof. Benjamin Iñiguez (Universitat Rovira i Virgili, Spain)

For a more detailed description of the project see:

http://brage.unik.no/personer/torfj/Projects/COMON/COMON_Annex.pdf

Research Topics:
• Compact modeling of nanoscale MOSFETs
• Model validation
• Parameter extraction techniques
• Model implementation

Startup and Deadline: Applicants are encouraged to apply at the earliest convenience. The deadline for the application is September 15, 2008. The startup date is flexible and can be chosen by the candidate in consultation with Professor Fjeldly. The COMON project is provisionally scheduled to start on October 1, 2008.

How to Apply: Applicants must submit official academic records for their bachelor, masters, and Ph.D. education, and a complete publication list. It is a requirement to hold a Ph.D. or an equivalent degree for being considered for this position. At least three academic references (name, position, e-mail, and telephone number) should be
included in the application.

Applicants are encouraged to submit their applications electronically to:
postmottak@unik.no and torfj@unik.no
Home-page of Prof. Fjeldly: http://brage.unik.no/personer/torfj
Office phone: +47-64844700 or +47-64844747
Otherwise, send by regular mail to:
UNIK - University Graduate Center
Attn: Tor A. Fjeldly
Instituttveien 25, P. O. Box 70
N-2027 Kjeller, Norway
Background: The candidates must have a solid background in electronics, semiconductor device physics, and mathematics. The ability to program in Matlab or other similar programming languages is also essential.
Candidate Evaluation Criteria: To evaluate the candidates, the following prioritized criteria will be used:
1) International publications (journal & conference) on relevant topics, i.e., scientific productivity and the time spent to produce the scientific work.
2) University education
• Grades: To be considered, the applicant should have mainly A or B for relevant courses and overall good grades
to demonstrate the capacity to learn new material
• The time used to complete the Bachelors, Masters, and Ph.D. university degrees should follow the normal study
time period
• Proficiency in English as documented by TOEFL, IELTS, or equivalent practical use of English.
• GRE score if available
• Completion of courses indicating relevant knowledge in
– Electronics
– Semiconductor device physics
– Mathematics
• Relevance of Ph.D. (and Masters) research topics
3) Industrial experience in electronics
4) Teaching experience
5) Females are given priority when competing with men of equal qualifications.
Description of UNIK - University Graduate Center: UNIK is a graduate educational institution for Master’s, graduate engineering and doctoral students, primarily affiliated with University of Oslo or Norwegian University of Science and Technology (NTNU), but also for continuing education students from commerce and
industry. Courses are offered in four academic fields:
• Electronics and Photonics
• Networking, Information Security, and Signal Processing for
Communications
• Cybernetics and Industrial Mathematics
• Energy and the Environment
UNIK offers courses and supervision on behalf of University of Oslo and NTNU. For more information see: www.unik.no.
Help to find a place to live: UNIK will help the chosen candidate to find a place to live near UNIK. UNIK will help the candidate and his/her family to sign up for courses in Norwegian language, if desired.

Papers on IEEE Trans on Electron Devices (Aug 2008)

Well, it seems that this has been a very productive issue:

Accurate Statistical Description of Random Dopant-Induced Threshold Voltage Variability
Millar, C. Reid, D. Roy, G. Roy, S. Asenov, A. (link)

Analytical Threshold Voltage Model for Double-Gate MOSFETs With Localized Charges
Kang, H. Han, J.-W. Choi, Y.-K. (link)

Origin of the Asymmetry in the Magnitude of the Statistical Variability of n- and p-Channel Poly-Si Gate Bulk MOSFETs
Asenov, A. Cathignol, A. Cheng, B. McKenna, K. P. Brown, A. R. Shluger, A. L. Chanemougame, D. Rochereau, K. Ghibaudo, G. (link)

A Charge-Based Model for Long-Channel Cylindrical Surrounding-Gate MOSFETs From Intrinsic Channel to Heavily Doped Body
Liu, F. He, J. Zhang, L. Zhang, J. Hu, J. Ma, C. Chan, M. (link)

Drain Current Model Including Velocity Saturation for Symmetric Double-Gate MOSFETs
Hariharan, V. Vasi, J. Rao, V. R. (link)

A Unified Analytic Drain–Current Model for Multiple-Gate MOSFETs
Yu, B. Song, J. Yuan, Y. Lu, W.-Y. Taur, Y. (link)

A Quasi Two-Dimensional Conduction Model for Polycrystalline Silicon Thin-Film Transistor Based on Discrete Grains
Wong, M. Chow, T. Wong, C. C. Zhang, D. (link)

Simulation of the Impact of Process Variation on the Optimized 10-nm FinFET
Khan, H. R. Mamaluy, D. Vasileska, D. (link)

Investigation of the Transport Properties of Silicon Nanowires Using Deterministic and Monte Carlo Approaches to the Solution of the Boltzmann Transport Equation
Lenzi, M. Palestri, P. Gnani, E. Reggiani, S. Gnudi, A. Esseni, D. Selmi, L. Baccarani, G. (link)

A Physical Model of High Temperature 4H-SiC MOSFETs
Potbhare, S. Goldsman, N. Lelis, A. McGarrity, J. M. McLean, F. B. Habersat, D. (link)

3C-Silicon Carbide Nanowire FET: An Experimental and Theoretical Approach
Rogdakis, K. Lee, S.-Y. Bescond, M. Lee, S.-K. Bano, E. Zekentes, K. (link)

Characterization, Modeling, and Application of 10-kV SiC MOSFET
Wang, J. Zhao, T. Li, J. Huang, A. Q. Callanan, R. Husna, F. Agarwal, A. (link)

Nice papers (July, 2008)

No, we're not dead, but overworked... Here you have some nice papers, from various sources, including one which is unexpected...

A simple analytical model for the front and back gate threshold voltages of a fully-depleted asymmetric SOI MOSFET
Chung Ha Suh, Solid-State Electronics (abstract)

Analysis and Modeling of Threshold Voltage Mismatch for CMOS at 65 nm and Beyond
Jeffrey B. Johnson, Terence B. Hook, and Yoo-Mi Lee, IEEE ELECTRON DEVICE LETTERS, VOL. 29, NO. 7, JULY 20 (abstract)

An Analytical Model Based on Surface Potential for a-Si:H Thin-Film Transistors
Yuan Liu, Student Member, IEEE, Ruo-he Yao, Bin Li, Member, IEEE, and Wan-Ling Deng, JOURNAL OF DISPLAY TECHNOLOGY, VOL. 4, NO. 2, JUNE 2008 (abstract)

Papers on the IEEE TED, vol 55 (7)

Some nice papers:

An Analytical Gate Tunneling Current Model for MOSFETs Having Ultrathin Gate Oxides
Mondal, I.; Dutta, A. K.
Abstract

A Fully Three-Dimensional Atomistic Quantum Mechanical Study on Random Dopant-Induced Effects in 25-nm MOSFETs
Jiang, X.-W.; Deng, H.-X.; Luo, J.-W.; Li, S.-S.; Wang, L.-W.
Abstract

A Physical-Based PSPICE Compact Model for Poly(3-hexylthiophene) Organic Field-Effect Transistors
Meixner, R. M.; Gobel, H. H.; Qiu, H.; Ucurum, C.; Klix, W.; Stenzel, R.; Yildirim, F. A.; Bauhofer, W.; Krautschneider, W. H.
Abstract

IEEE International Workshop on Compact Thin-Film Transistor Modeling for Circuit Simulation

The first IEEE International Workshop on Compact Thin-Film Transistor Modeling for Circuit Simulation will be held in the Moller Center, in Cambridge, UK, on September 11-12 2008.

This interesting workshop is organized by the IEEE EDS Compact Modeling Technical Committee, in collaboration with the London Center for Nanotechnology, University College of London, UK, the Electrical Engineering Division, Engineering Department, Cambridge University, UK, and the IEEE UK-RI (AP/ED/LEO/MTT) joint Chapter.

Compact modeling of TFTs has become nowadays a very hot topic, due to the extension of the applications of TFTs. This workshop will provide a forum for discussions and current developments on compact TFT modeling.

Topics include:

• Physics of TFTs and operating principles
• Compact TFT device models for circuit simulation
• Model implementation and circuit analysis techniques
• Model parameter extraction techniques
• Applications of compact TFT models in emerging products
• Compact models for interconnects in active matrix flat panels

The deadline for abstract submission is July 15.

I will give an invited presentation in this workshop. And there will be other interesting invited presentations.

This is the first workshop that is devoted to compact TFT modeling. I recommend the TFT modeling and TFT circuit design communities to attebnd this workshop.

Besides, in conjunction with the workshop on “Compact TFT Modeling for Circuit Simulation,” IEEE Electron Devices Society (EDS) Compact Modeling Technical Committee (CMTC) in collaboration with IEEE UK-RI AP/ED/LEO/MTT Chapter has organized EDS mini-colloquia (MQ) on September 12, 2008 at Moller Centre, Cambridge, UK.

SINANO-NANOSIL Workshop

The SINANO-NANOSIL Workshop will take place in Edinburgh on September 19th, 2008, during the ESSDERC-ESSCIRC Conference.

This Workshop, continuation of the former SINANO Workshop, is a very valuable discussion forum in the area of nanoelectronics devices. The SINANO-NANOSIL Workshop is supported by the SINANO Institute, which is a new European entity created by the main laboratories of the European academic community working in nanoelectronics, and by the European Network of Excellence NANOSIL which targets Silicon-based Nanodevices and is funded by the European Commission for the 7th Framework Programme, from 2008 to 2011. The former SINANO Workshop was funded by the prebvious Network of Excellence, called SINANO.

The program of the SINANO-NANOSIL Workshop consists of several presentations given by a number of representatives of NANOSIL partners:

9:00 New channel materials for ultimate CMOS
Siegfried Mantl (Institut für Bio- und Nanosysteme, Forschungszentrum Juelich)

9:30 Innovative device architectures for Nanoscale CMOS
Nadine Collaert (IMEC)

10:00 Coffee break

10:30 Comparative analysis of Stress-induced performance enhancement in NMOS and PMOS transistors
David Esseni (Udine University)

11:00 Characterization methods for Nanodevices
Sorin Cristoloveanu (IMEP)

11:30 Emerging Nanotechnology for integration of Nanostructures in Nanoelectronic devices
Thierry Baron (LTM)

12:00 Lunch

13:30 Small Slope Switches
Adrian Ionescu (EPFL)

14:00 3D Multichannels and stacked Nanowires Technologies
Thomas Ernst (LETI)

14:30 Carbon Nanotube - Silicon heterojunctions for Nanoelectronics and Nanosensors
Jimmy Xu (Brown University)

15:00 Atomic functionalities in Silicon devices: go beyond the FET by using single dopants and artificial silicon atoms
Marc Sanquer (INAC)

15:30 End of the Workshop

AM-FPD'08

The 15th International Workshop on Active-Matrix Flatpanel Displays and Devices (AM-FPD-08, former AM-LCD) will be held from July 2 to 4 2008 at the National Museum of Emerging Science and Innovation (Miraikan), Tokyo, Japan.

AM-FPD has extended the goals of former AM-LCD workshop in order to address, apart from AM-LCD technology, AM-OLED displays and other AM-FPD technologies. The topics of AM-FPD also include TFT devices, circuits and systems, LC technologies, related materials and crystallization.

Besides, a symposium "Emerging Technologies for Future Displays" is scheduled. This symposium will consist of four sessions: "Basic properties for fututre TFTs", "Advanced TFT technologies for future applications", "Technologies for LCD" and "Future technologies for Organic Devices".

The authors of the best papers will be invited to submit extended versions of their papers for publication in the Japanese Journal of Applied Physics, in a special issue called "Active-Matrix Flatpanel Displays and Devices-TFT Technologies and FPD Materials".

AM-FPD is one of the top conferences in the field of TFTs. Papers are very interesting, and include several invited presentations.

A number of papers address TFT compact modeling. H. Ikeda (Sony, Japan) presents one paper entitled "Surface Potential-BAsed Polycrystalline- Silicon TFT Model for Circuit Simulation". M. Kimura (Ryukoku University, Japan) presents "Physical Model of Current-Voltage Characteristic for TFT".

Other papers address issues such as LCD & FPDs, TFT crystallization technologies, TFT process technologies, characterization and reliability of TFTs, OLEDs, Oxide Semiconductor TFTs, and new applications of TFTs

BMAS'08

The 2008 IEEE International Behavioral Modeling and Simulation Conference (BMAS 2008) will be held in San Jose, CA, on September 25-26, in conjunction with the 2008 Custom Integrated Circuits Conference (CICC), in the Doubletree Hotel in San Jose, at the heart of Silicon Valley.

BMAS addresses behavioral modeling and simulation for analog electronic circuits and systems. One of the main areas of topics is "Semiconductor Device Compact Modeling", which includes: " Compact device modeling lanuages and compilers", "Standard and new compact device models implemented in Verilog-A and VHDL-AMS", and "Compact device models for emerging technologies and topical issues (nano-devices, distributed thermal effect, leakaging issues, manufacturability, radiation effects, etc)".

The deadline for paper submission is June 30 2008.

For compact and behavioral modeling researchers, BMAS is no doubt a very interesting conference to attend, and for circuit designers, it is a very good complement to CCIC.

Edinburgh ESSDERC/ESSCIRC Workshop: 1st announcement for MOS-AK

I post the announcement I've got from Wladek Grabinski concerning the MOS-AK Workshop:

MOS-AK Workshop on compact modeling, organized for sixth subsequent time as an
integral part of the ESSDERC/ESSCIRC conference, aims to strengthen a network
and discussion forum among experts in the field, create an open platform for
information exchange related to compact/Spice modeling, bring people in the
compact modeling field together, as well as obtain feedback from technology
developers, circuit designers, and CAD tool vendors.

The topics of the Workshop cover all important aspects of compact model development,
implementation, deployment and standardization within the main theme - compact models
for mainstream CMOS/SOI circuit simulation. The specific workshop goal will be to
classify the most important directions for the future development of the compact
models and to clearly identify areas that need further research.

This workshop is designed for device process engineers (CMOS, SOI, BiCMOS, SiGe)
who are interested in device modeling; ICs designers (RF/IF/Analog/Mixed-Signal/SoC)
and those starting in that area as well as device characterization, modeling and
parameter extraction engineers. The content will be beneficial for anyone who needs
to learn what is really behind IC simulation in modern device models.

The technical program of MOS-AK Workshop consists of one day of tutorials given by
noted academic and industry experts, also a posters session is foreseen which will
be dedicated but not limited to the VHDL-AMS/Verilog-A model standardization:

http://www.mos-ak.org/edinburgh

The workshop program is open and you are welcome to submit poster to our poster
session where we will be focusing on different aspects of the Verilog-A compact
model standardization. Selected papers/posters will be recommended for further
published in the IJNM and SEE - MOS-AK publication partners.

Tentative list of the speakers already includes following names:
 * Narain Arora, Silterra
 * David M. Binkley, UNC Charlotte
 * Matthias Bucher, TUC
 * Christian Enz, CSEM
 * Benjamin Iniguez, URV
 * Tom J. Kazmierski, University of Southampton
 * Ehrenfried Seebacher, austriamicrosystems
 * Sadayuki Yoshitomi, TOSHIBA

The workshop program is open and you are welcome to submit poster to our poster
session where we will be focusing on different aspects of the Verilog-A compact
model standardization. Selected papers/posters will be recommended for further
published in the IJNM and SEE - MOS-AK publication partners.

--- Important dates:
--------------------
* 2nd announcement       - July 19
* Final workshop program -  Aug.19
* MOS-AK Workshop        - Sept.19 at the Edinburgh International Conference
Centre (EICC)

Further information including recommended hotels and driving directions will be
posted at our web site, soon; please visit regularly: http://www.mos-ak.org

Let me remark that this is also a nice opportunity to visit Edinburgh (see these
links 1 and 2), and make some whisky tasting (see the links 1 and 2)!

Graduate Student Meeting on Electronic Engineering

The Graduated Student Meeting on Electronic Engineering (formerly Nanoelectronics and Photonics Systems Workshop), has been an annual event, created and organized by the Universitat Rovira i Virgili (URV), in Tarragona (Catalonia, Spain) since 2003. It consists of two days of plenary talks given by invited prestigious researchers (from different countries) about selected topics related to electronic engineering and two poster sessions were PhD students in this field will present their work.

This Graduated Student Meeting has become a very useful forum for PhD students and researchers in the field of Electronic Engineering. The present edition will take place in June 19th and 20th.

This year, the Graduated Student Meeting is being sponsored by the NANOSIL European Network of Excellence. One of the invited speakers, Prof. Sorin Cristoloveanu (IMEP-INP Grenoble, France), is one of the leading authorities in the field of SOI technology and characterization. His talk is entitled "Selected Characterization Techniques for SOI Materials and Devices"

Another invited speaker, Prof. Antonio Cerdeira (CINVESTAV, Mexico City) will conduct a lecture on "Compact Model for Symmetric Double-Gate MOSFETS"
Prof Cerdeira has a long experience and outstanding publicactions in compact model and every year spends several months as an invited researcher in the Universitat Rovira i Virgili.

Both Prof. Cristoloveanu and Prof. Cerdeira have been invited as Distinguished Lecturers of the Electron Devices Society of the IEEE.

Other talks will address photonic crystals (Dr D Gerace), dynamical systems (Dr B Robert) and nanorods (Dr C Blackman).

Awards for the best posters in two categories: one category for Master students and another category for Doctoral Students.

2-pages abstracts corresponding to poster presentations and plenary talks will be published in the Proceedings. The deadline for abstracts reception is June 11th.

Tarragona is located in the south of Catalonia, in the northeast corner of the Iberian Peninsula.
Tarraco (the Roman name for Tarragona) was one of the most important cities in the Roman Empire. On 30 November 2000, the UNESCO committee officially declared the Roman archaeological complex of Tàrraco a World Heritage Site. This recognition is intended to help ensure the conservation of the monuments, as well as to introduce them to the broader international public.

In June the weather is warm enough to go to the beaches in or around Tarragona, but comfortable enough to walk and do sightseeing in the city. Thanks to its Mediterranean climate, its clean beaches with fine and gloden sand, and its singular artistic and architectural heritage, Tarragona is one of the most important tourism hubs in Europe.

I encourage Ph D students to send posters and attend this interesting Meeting!

Adieu Electronics: The End is Near (Perhaps Nearer than You Think)

I've been reading a very interesting post in Electronics Design, Strategy, News. The author, Steve Leibson, says that it seems we're running out of some of the necessary elements in semiconductor fabrication... Have a look at the post, and don't miss the comments....

In any case, it seems that this is a very good moment to be developing models for new devices! :-)