Agilent, China University team up on LTE testing

Mike Kawasaki, education program manager at Agilent, said that the company sees the R&D collaboration with Southeast University as a continuation of Agilent's drive to be a key technology partner for innovative research in academia. "This collaboration enables Agilent to make a contribution to the future of wireless communication and gives the university access to our resources, empowering further success of scientists in academia," he said. Read more...

Postdoctoral Marie Curie Fellowships on Compact Modeling

The European (7th Framework Programme) Call for Postdoctoral Individual Marie Curie Fellowships is open until August 18 2009.

I am looking for one or two candidates to work in my research group at the Universitat Rovira i Virgili (Tarragona, Spain) in the field of compact modeling of advanced semiconductor devices. Therefore, I would like to receive CVs from potential applicants. Once I have selected the candidates, we will make the application.

The candidates must have a Ph D in Electrical Engineering, Electronic Engineering, Physics or Telecommunication Engineering.


There are two open Calls: the one for Intra European Fellowships (FP7-PEOPLE-2009-IEF) and the one for International Incoming Fellowships (FP7-PEOPLE-2009-IIF). Therefore, candidates from European countries can apply for an Intra European Fellowship and candidates from outside Europe can apply for an International Incoming Fellowship.

These felowships can be for one or two years. Salaries are extremely good and the prestige of having this type of fellowship is very high. For this reason, there is a tough competition to get these fellowships.

I am looking for candidates for these Marie Curie Grants, both from Europe and outside Europe. Candidates must have a good CV (preferably with more than 4 publications in international journals, in order to have chances). In order to fit the Marie Curie requirements, their age should be below 35.

If successful, the postdoctoral researchers will work on the characterization of compact modeling of any of the advanced semiconductor devices targeted by our research European projects: nanoscale MOSFETs, SOI and Multi-Gate MOSFETs, strained-Si/SiGe MOSFETs, Schottky-Barrier MOSFETs, nanowire FETs, III-V HEMTs and organic TFTs.

The specific device/s in which the postdoctoral researcher will work will depend on his/her preference and background.

Candidates must send me by e-mail (to benjamin.iniguez@gmail.com) a CV or resume by AUGUST 6. Successful applicants will be informed by August 7, and then we will start to make the application. The successful candidates will be informed on the steps to do.

Tarragona is a small city (110000 inhabitants) on the Mediterranean coast, about 100 Km south from Barcelona, and very well connected to Barcelona and the main Spanish cities by rail and highway. Tarragona is a very old city, very important during the Roman Empire, and with a lot of historical landmarks.

The quality of life in Tarragona is excellent. Mediterranean and mild climate the whole year. Wonderful beaches around the city (even at the city). Mountains close to the city (even the Pyrenees are not far). Besides, the city is very quiet, but with an intense nightlife.

My research group in the Department of Electronic Engineering, Universitat Rovira i Virgili (URV) is one of the strongest groups in compact modeling in Europe. We are leading one European project on compact modeling (in which a total of 15 European universities and companies participate). We also participate on two other European projects (one about nanoscale MOSFETs and another one about organic Thin Film Transistors).

I am looking forward to receiving excellent applications!

Benjamin Iñiguez
Department of Electronic Engineering
Tarragona, SPAIN
Universitat Rovira i Virgili (URV)
E-mail: benjamin.iniguez@gmail.com

Papers in IEEE TED, Vol 56 (8), Aug. 2009

Random-Dopant-Induced Variability in Nano-CMOS Devices and Digital Circuits

Li, Y.; Hwang, C.-H.; Li, T.-Y.
Page(s): 1588-1597

A New Three-Dimensional Capacitor Model for Accurate Simulation of Parasitic Capacitances in Nanoscale MOSFETs

Guo, J.-C.; Yeh, C.-T.
Page(s): 1598-1607

A Simple Semiempirical Short-Channel MOSFET Current–Voltage Model Continuous Across All Regions of Operation and Employing Only Physical Parameters

Khakifirooz, A.; Nayfeh, O. M.; Antoniadis, D.
Page(s): 1674-1680

SINANO-NANOSIL Workshop

The SINANO-NANOSIL Workshop will take place in Athens on September 18th, 2008, during the ESSDERC-ESSCIRC Conference.

This Workshop, continuation of the former SINANO Workshop, is a very valuable discussion forum in the area of nanoelectronics devices.

The aim of this Workshop is to present the status and trends of CMOS and beyond-CMOS nanodevices for terascale ICs and to establish a discussion forum in the field of nanoelectronics devices.

The SINANO-NANOSIL Workshop is supported by the SINANO Institute, which is a new European entity created by the main laboratories of the European academic community working in nanoelectronics, and by the European Network of Excellence NANOSIL which targets Silicon-based Nanodevices and is funded by the European Commission for the 7th Framework Programme, from 2008 to 2011. The former SINANO Workshop was funded by the prebvious Network of Excellence, called SINANO.

The program of the SINANO-NANOSIL Workshop consists of several presentations given by a number of representatives of NANOSIL partners:

9:00 Limitations in future gate stack materials
O. Engstrom
Chalmers University

9:30 Metallic source/drain for advanced MOS architectures: from material engineering to device integration
E. Dubois,
IEMN

10:00 Coffee break

10:30 Advanced Memory devices using multi-gate and 3D structures
B. DeSalvo
LETI

11:00 Tunnel FET or Ferroelectric FET to achieve a sub-60mV/decade small swing switch
A. Ionescu
EPFL

11:30 Electron Transport in Graphene Quantum Dots and Quantum Point Contacts
L. Ponomarenko
University of Manchester

12:00 Lunch

13:30 Variability in Nanoscale CMOS and Nanowires
A. Asenov
University of Glasgow

14:00 Simulation of gate leakage currents in UTB MOSFETs and Nanowires
A. Schenk,
ETH-Zentrum

14:30 3D quantum transport simulations of Si Nanowires: impact of elastic and inelastic scattering
M. Pala
IMEP-LAHC, Grenoble INP-Minatec

15:00 Deterministic solution of the 1D Boltzmann transport equation
G. Baccarani, E. Gnani, A. Gnudi and S. Reggiani
ARCES-IUNET

15:30 End of the Workshop

9:00 Limitations in future gate stack materials

O. Engstrom

Chalmers University

9:30 Metallic source/drain for advanced MOS architectures: from material engineering to device integration

E. Dubois,

IEMN

10:00 Coffee break

10:30 Advanced Memory devices using multi-gate and 3D structures

B. DeSalvo

LETI

11:00 Tunnel FET or Ferroelectric FET to achieve a sub-60mV/decade small swing switch

A. Ionescu

EPFL

11:30 Electron Transport in Graphene Quantum Dots and Quantum Point Contacts

L. Ponomarenko
University of Manchester

12:00 Lunch

13:30 Variability in Nanoscale CMOS and Nanowires

A. Asenov

University of Glasgow

14:00 Simulation of gate leakage currents in UTB MOSFETs and Nanowires

A. Schenk,

ETH-Zentrum

14:30 3D quantum transport simulations of Si Nanowires: impact of elastic and inelastic scattering

M. Pala

IMEP-LAHC, Grenoble INP-Minatec

15:00 Deterministic solution of the 1D Boltzmann transport equation

G. Baccarani, E. Gnani, A. Gnudi and S. Reggiani

ARCES-IUNET

15:30 End of the Workshop

ESSCIRC/ESSDERC early registration deadline ***26/7/2009***

Some information from Matthias Bucher

Dear Colleagues,

Please let me draw your attention to the deadline for early registration for ESSDERC/ESSCIRC 2009 in Athens, 14-18/9/2009, is this Sunday, 26 July. For those who have not registered yet, consider the reduced registration fees, http://www.esscirc2009.org/?pid=3.

I also would like to draw your attention to the Tutorials on Monday 14/9/2009, http://www.esscirc2009.org/?pid=7. Of course you are aware the MOS-AK workshop is held on Friday 18/9/2009, please **do** register as well! (even though it is free, and even for those of you who might not attend ESSDERC/ESSCIRC).

As an additional information, I’m attaching below some links to hotels that you might want to consider booking, in the Acropolis and Plaka region, about 20-25 minutes (either metro and/or walking) or 15 minutes by taxi, from the Caravel hotel where the conference is held. Hotels very close to the Caravel are probably already booked (those indicated on the conference site) or very expensive (Hilton, and Caravel). Don't delay booking, I hope these are of some help.

Acropolis Museum Boutique hotel, 48 Sygrou Ave., 11720 Athens
http://www.booking.com/hotel/gr/acropolis-museum-boutique.en.html?sid=86c27c055ff3d2b31320a517ff769305

Airotel Parthenon, 6 Makri Str., 11742 Athens
http://www.booking.com/hotel/gr/parthenon.en.html?sid=86c27c055ff3d2b31320a517ff769305

Acropolis Select Hotel, 37-39 Falirou Str., 11742 Athens
http://www.tripadvisor.com/Hotel_Review-g189400-d230390-Reviews-Acropolis_Select_Hotel-Athens_Attica.html

or hotels in the "Plaka" area (again close to Acropolis and close to metro stations)

Amazon Hotel, Mitropoleos 19 & Pentelis 7, 10557 Athens
http://www.booking.com/hotel/gr/amazonathens.html

PLAKA HOTEL ATHENS, 7 Kapnikareas & Mitropoleos, Athens
http://www.holiday-in-athens.com/athens/plaka-hotel-athens.html

Are memristors the future of Artifical Intelligence?

Read more...

Post-Silicon Solutions Emerging

Post-Silicon Solutions Emerging:

Researchers have an array of new technologies in the pipeline to boost CMOS logic and memory performance, Sematech Vice President Raj Jammy said Tuesday at the Device Scaling TechXPOT at SEMICON West. High-mobility graphene channels, gates built around nanowires, finFETs with III-V materials -- all promise to blow past the power/performance capabilities of silicon CMOS.

David Lammers, News Editor -- Semiconductor International, 7/15/2009

Researchers have an array of new technologies in the pipeline to boost CMOS logic and memory performance, Sematech Vice President Raj Jammy said Tuesday at the Device Scaling TechXPOT at SEMICON West.

"We need disruptive materials and technologies," said Raj Jammy of Sematech.

High-mobility graphene channels, gates built around nanowires, finFETs with III-V materials -- all promise to blow past the power/performance capabilities of silicon CMOS. Jammy, in charge of materials and emerging technologies research at Sematech, warned that "people entrenched in the silicon world" may need to rethink as scaling of today's CMOS transistors becomes increasingly difficult.

"We need disruptive materials and technologies," Jammy said, describing R&D progress on several post-22 nm options. Progress is being made on heterogeneous devices, where germanium is used as the channel in the pFET and indium gallium arsenide (InGaAs), for example, on the nFET. Nanowires with a gate-all-around design are drawing more R&D attention, and work continues on finFETs -- vertical structures that allow better control of the channel.

Memory R&D is equally vibrant. For decades, mainstream memories have been based on charge storage. "But when you make these devices really small, charge storage is no longer possible." On the horizon are phase change memories (PCRAMs) and metallic resistive RAMs (ReRAMs), though Jammy acknowledged that the question regarding ReRAM technology is: "Does it work at less than 20 nm?"

Also under study are zero-leakage nanoelectrical-mechanical system (NEMS) devices, which Jammy said "exhibit instant on and off." And because they are mechanical, they can safely operate in hazardous environments, such as a nuclear power plant.

Schubert Chu of Applied Materials spoke of the potential of carbon-doped silicon for nFET strain.

Schubert Chu, an Applied Materials product manager for epi/LPCVD products, examined the possibility of embedded silicon carbon (eSiC) being used to enhance the performance of the nFET. While embedded silicon germanium (eSiGe) has served to effectively strain the pFET, SiC has been a tougher challenge, largely because the carbon atoms tend to move around.

Chu said that an AMD-led team has shown a 30% improvement with nFETs strained by SiC structures. "Silicon carbon is on track to be adopted at the 22 nm generation."

SiGe stressors face challenges as the germanium content moves from 25-30% at the 45 nm node to >40% at the 22 nm node. Applied Materials has developed a "Siconi" pre-clean option for its Centura epitaxial deposition tool, which Chu said will extend epi strain technologies.

Jammy said the industry faces serious cost challenges. "When we hear that it may cost $80M for a EUV scanner, we are not going in the right direction on costs," he said.

Organic semiconductor researchers honoured by Institute of Physics

From the OSADirect Newsleter:

The 2009 Faraday Medal, one of the Institute's three gold medals, has been awarded to Professor Donal Bradley FRS for his pioneering work in the field of plastic electronics. Professor Bradley who holds the Lee Lucas Chair in Experimental Physics, is Director of the newly established Centre for Plastic Electronics at Imperial.

Professor Bradley's research focuses on optimising plastic semiconductors for use in a wide range of electronic devices, with applications spanning displays, lighting, electronics, solar energy, communications and medical diagnostics.

Professor Bradley said, "What a wonderful way to celebrate the twentieth anniversary of conjugated polymer LEDs - a discovery that helped to launch plastic electronics on the path to its present day vibrancy as an academic research field with great commercial potential. I am delighted to have been able to walk that path in the company of so many talented students, postdoctoral researchers and academic and industrial colleagues – this award recognises the fruits of a great many, very enjoyable collaborative interactions."

Professor Jenny Nelson has been awarded the Joule Medal. Prof. Nelson is currently working on the use of molecular or 'plastic' electronic materials in solar cells, in order to reduce the cost of solar electricity. Once the basic properties of the materials are properly understood, design rules can be developed for new materials and types of device with better performance.

Professor Nelson said, "I am absolutely thrilled and honoured to receive the Joule Medal for our research into photovoltaic materials. I'm delighted that both the importance of the subject and my own group's contribution to it have been recognised in this way."

20th Anniversary of Innovation

View from The Top Executive Interviews "20th Anniversary of Innovation", John Tanner, CEO Tanner EDA Follow audio interview...

Lynguent Debuts Radiation Hardened By Design, BSIM4 Compact Model Toolkits

Lynguent®, Inc., announced two new toolkits for its ModLyng[tm] Integrated Modeling Environment (IME): Radiation Hardened By Design (RHBD) Toolkit and BSIM4 Compact Model Toolkit. The RHBD Toolkit includes models and tools which provide a modeling and analysis capability for Single Event Upset (SEU) behaviors in deep sub-micro processes. The BSIM4 Compact Model Toolkit includes a high fidelity BSIM4 model which provides more flexibility than has ever been available for adding new effects to existing processes built upon the BSIM foundation. These toolkits, when used with the ModLyng IME, enable semiconductor and systems companies to easily enhance their IC design flows with radiation SEU capability and thus save weeks in qualifying their designs and cell libraries for radiation hardness.

Read more...

New Book:

Compact MOSFET Models for VLSI Design
A. B. Bhattacharyya
ISBN: 978-0-470-82342-2
Hardcover 512 pages April 2009


This book is essential for students specializing in VLSI Design and indispensible for design professionals in the microelectronics and VLSI industries. Written to serve a number of experience levels, it can be used either as a course textbook or practitioner’s reference. Read more...

Access the MATLAB code, solution manual, and lecture materials at the companion website.

IC Insights expects an 18% "surge" in the IC market

I post here a very interesting article, even if not related to compact modelling, from EDN:(visit them for more interesting articles)

IC market second-half 'surge' predicted

IC Insights expects an 18% "surge" in the IC market in the second half of the year and claims there is clear evidence that the much-anticipated turning point toward recovery has already occurred.

By Suzanne Deffree, Managing Editor, News -- Electronic News, 7/2/2009

The second half of 2009 will be much better than the first for the semiconductor industry, and will be marked by an IC market "surge," according to IC Insights.

The market research company this week reported that while the first half of 2009 was hit hard by seasonal weakness for electronic system sales, a major IC inventory adjustment, and the global recession at its worst, the second half of 2009 is expected to usher in strong seasonal strength for electronic system sales, a period of IC inventory replenishment, and positive worldwide GDP growth.

"In IC Insights' opinion, the bottom of the current cycle in the worldwide economy and semiconductor industry was reached in Q1 2009," Bill McClean, president of IC Insights, said in a statement on the company's mid-year update. "While the 'velocity' of the semiconductor industry recovery is subject to debate (slow, moderate, fast, etc), at least the discussion over the next few quarters will be about how much sequential growth can be expected in instead of how far the markets are going to fall."

Also see: Demand surge expected in second half, IC Insights says Major upsets in semiconductor top 20 ranking, IC Insights reports Bottom hit in Q1, 5% growth for Q2 expected, IC Insights reports

IC Insights has long been encouraging the idea that, when viewed on a quarterly basis, a much more positive and "relevant" outlook business conditions can be achieved.

For example, according to the company's data, worldwide GDP growth is forecast to be negative this year of down 0.8% on a weak first half with growth down, but the second half of the year is expected to register positive growth of 2%. (See figure 1 below.) The same pattern is forecast for the US economy, as well, with the second half showing growth of 1.3% as compared to the first half.

Specific to the electronics industry, IC Insights reported seasonal strength is likely to propel second-half cell phone and PC unit shipments up by 18% and 15%, respectively, as compared to the first half.

Overall, IC Insights said it expects an 18% "surge" in IC market sales in the second half, as compared to the first half. "In fact, the double-digit Q2 2009/Q1 2009 IC market increase is clear evidence of the fact that the much-anticipated turning point has already occurred," McClean said.

According to IC Insights, the IC foundry market is expected to continue its "sharp recovery" in the second half of 2009. McClean noted that the IC foundry market almost doubled in Q2 as compared to Q1.

"There is no doubt that, as a group, the semiconductor equipment suppliers have taken the worst 'beating' of any of the companies involved in the current semiconductor industry downturn," McClean said. "However, the second half of 2009 is expected to offer some relief for these suppliers as semiconductor industry capital spending is forecast to jump by 28% as compared to the first half of 2009."

McClean noted that many of the major semiconductor suppliers that IC Insights tracks are planning to spend the majority of their capital spending budgets in the second half of 2009. Offering example, he said Hynix spent 30% of its 2009 spending budget in the first half, but plans to spend the remaining 70% in the second half.