[FSiC2026] Open EDA · Open Silicon · Sovereign by Design

FSiC2026

Free Silicon Conference 2026

Open EDA · Open Silicon · Sovereign by Design

What is FSiC? The annual gathering of the free and open-source silicon community building open EDA tools, open PDKs, and free hardware. Three days of talks and tutorials about designing chips with software you can read, share, and modify.

Who should come? Chip designers, EDA developers, researchers, students, and anyone curious about building silicon without proprietary lock-in. All experience levels welcome.

When? 6–8 July 2026

Where? University of Ljubljana, 

Faculty of Electrical Engineering

Tržaška cesta 25

SI-1000 Ljubljana

Registration closes 22 June: https://pretix.eu/FSiC/2026/

FSiC2026 Program: https://wiki.f-si.org/index.php/FSiC2026

[Lecture 13-16] supplementary by Prof. Kim

Prof. Kwantae Kim, Analog Integrated Circuits at Aalto University, recorded additional videos that cover walkthroughs of the CAD exercises in his Integrated Analog Systems course. These videos should provide useful guidance for ADC design simulation and verification practice! 

• Integrated Analog Systems D - Lecture 13S CAD (Bootstrapped Sampling Switch)
  https://www.youtube.com/watch?v=VSDzmijax3c
• Integrated Analog Systems D - Lecture 14S CAD (Linearity and FFT)
  https://www.youtube.com/watch?v=qwJ_tlZTaq8
• Integrated Analog Systems D - Lecture 15S CAD (Transient Noise and VerilogA Modeling)
  https://www.youtube.com/watch?v=YW2nnI3DD_c
• Integrated Analog Systems D - Lecture 16S CAD (ADC ENOB Verification)
  https://www.youtube.com/watch?v=BIFXidfTYxE

Visit also webpage: https://kwantaekim.github.io

Revolution EDA Mistral AI Experiments

Revolution EDA MistralAI Experiments

by Murat Eskiyerli  

There was a recent article by Prof Razavi, where the problems of Large Language Models in identifying various analogue integrated circuit blocks were recounted.

Revolution EDA uses structured JSON data format to store design files. JSON also happens to be very easy for LLMs to parse and understand. In fact, Mistral AI has a JSON mode. Mistral AI is the latest addition to the growing number of LLMs that Revolution EDA is able to use.

We did ask a few questions to Mistral AI to test its understanding of designs in Revolution EDA and its potential to help designers. The results have been very encouraging. The future analogue integrated circuit designers will be able to use large language models like Mistral AI to quickly gain understanding of a circuit and improve on it.

The transcription below is taken exactly from the interaction with Mistral AI except for small formatting changes [read more...]

[Newsletter] Revolution EDA April 2026

Revolution EDA has two updates to share this month: 

• a browser-based cloud trial environment is now live, and 
• hierarchical Layout vs Schematic (LVS) verification has been added to the platform

Cloud Trial Environment

[paper] Multi-Agent Self-Evolved ABC

Cunxi Yu and Haoxing Ren

Autonomous Evolution of EDA Tools: Multi-Agent Self-Evolved ABC

In 63rd ACM/IEEE Design Automation Conference (DAC ’26)

July 26–29, 2026, Long Beach, CA

DOI: 10.1145/3770743.3804221

Abstract: This paper introduces the first self-evolving logic synthesis framework, which leverages Large Language Model (LLM) agents to autonomously improve the source code of ABC, the widely adopted logic synthesis system. Our framework operates on the entire integrated ABC codebase, and the output repository preserves its single-binary execution model and command interface. In the initial evolution cycle, we bootstrap the system using existing prior open-source synthesis components, covering flow tuning, logic minimization, and technology mapping, but without manually injecting new heuristics. On top of this foundation, a team of LLM-based agents iteratively rewrites and evolves specific sub-components of ABC following our “programming guidance“ prompts under a unified correctness and QoR-driven evaluation loop. Each evolution cycle proposes code modifications, compiles the integrated binary, validates correctness, and evaluates quality-of-results (QoR) on multi-suite benchmarks including ISCAS 85/89/99, VTR, EPFL, and IWLS 2005. Through continuous feedback, the system discovers optimizations beyond human-designed heuristics, effectively learning new synthesis strategies that enhance QoR. We detail the architecture of this self-improving system, its integration with ABC, and results demonstrating that the framework can autonomously and progressively improve EDA tool at full million-line scale.

Fig: Overview of the multi-agent self-evolving framework for ABC. Specialized LLM agents evolve distinct subsystems (flow optimization, core algorithms, and mapping), with each iteration undergoing compilation, formal CEC verification, and full QoR evaluation. A planning agent coordinates global decisions, a coding agent implements edits, and all agents follow a shared rulebase and unified evaluation pipeline to enable coordinated, correctness-preserving improvements.

Acknowledgment: The authors would like to thank Prof. Zhiru Zhang and his students for their valuable feedback and insightful discussions.

[OpenSUSI] Kicks off Five-Year Plan

Industry-Academia Collaboration Project Launches for Real Chip Manufacturing 

Using NDA-Free PDK - Tokai Rika, Kyushu University, AIST Solutions, 

OpenSUSI Kicks Off Five-Year Plan for FY2026

Tokai Rika Co., Ltd., Kyushu University, AIST Solutions Co., Ltd., and OpenSUSI have announced a joint project on a five-year plan to develop semiconductor human resources and verify their implementation through industry-academia collaboration to actually manufacture chips using PDK (Process Design Kit) that does not rely on NDAs (non-disclosure agreements). The 2026 launch ceremony was held. The biggest feature of this project is that it allows students to experience a series of processes from design to chip manufacturing under an open design environment using NDA-free PDKs #OpenPDKs

Positioning and future development in FY2026 as the first year that this project will be fully developed over a five-year span. Based on an open design and manufacturing environment utilizing NDA-free PDK #OpenPDK, we will continue and develop the following initiatives:

• Continuation and advancement of hands-on semiconductor human resource development
• Providing opportunities for actual chip manufacturing and verification using NDA-free PDK
• Building a practical and highly reproducible education and implementation model through industry-academia integration
• In exchange for the cost support for this program, we will embed the company's logo on the prototype chip to spread awareness of semiconductor design human resource development as a social contribution activity

(From left) Junichi Okamura, Representative Director of OpenSUSI, 

Haruichi Kanaya, Professor of Kyushu University, 

Taketoshi Sakurai, Executive Officer of Tokai Rika, 

and Seiji Osaka, President and CEO of AIST Solutions

If you are interested or interested in this matter, please contact us at:

OpenSUSI Secretariat <secretary@opensusi.org>

 

[DATE2026] Open Source Related Talks

DATE 2026 Verona, Italy

Open Source Related Talks

Monday, 20 April - Wednesday, 22 April 2026

<https://date26.date-conference.com/programme>

Label	Title	Authors
TS02.8	ML-DSA-OSH: An Efficient, Open-Source Hardware Implementation of ML-DSA	Quinten Norga; Suparna Kundu; Ingrid Verbauwhede
LK03	Democratizing Silicon: The Rise of Open-Source EDA and Europe’s Strategic Roadmap	Luca Benini
TS10.1	PICOSNN: Partially Incoherent Configurable Optical Computing Architecture for SNN Acceleration	Bowen Duan; Zhenhua Zhu; Zhengyang Duan; Huazhong Yang; Yuan Xie; Yu Wang
TS16.1	Non-Volatile Spintronic Flip-Flops with Checkpoint Preservation Supported in RISC-V Platform	Jiongzhe Su; Mingtao Chen; Zhanpeng Qiu; Bo Liu; Hao Cai
LBR01.4	Float Fight - Verifying Floating-Point Behavior In Risc-V Simulators	Katharina Ruep, Manfred Schlaegl and Daniel Grosse
LBR01.7	Hybrid Virtual Platform + FPGA Co-Emulation Framework	Lorenzo Ruotolo; Giovanni Pollo; Mohamed Amine Hamdi; Matteo Risso; Yukai Chen; Enrico Macii; Massimo Poncino; Sara Vinco; Alessio Burrello; Daniele Jahier Pagliari
TS20.1	Fault-Tolerance Mapping of Spiking Neural Networks to RRAM-Based Neuromorphic Hardware	Yuqing Xiong; Chao Xiao; Zhijie Yang; Lei Wang; Mengying Zhao
TS21.4	Substrate: A Statically Typed Framework for Designing Highly Configurable Analog and Mixed-Signal Circuit Generators	Rahul Kumar; Rohan Kumar; Borivoje Nikolic
SD03	Open-Source Hardware Landscape
SD03.1	Open Silicon Fabrication – Made in Europe	Gerhard Kahmen, IHP GmbH, DE
SD03.2	From Schematic To Silicon: Mixed Signal Ic Design In Open Source Flows	Harald Pretl, JKU Linz, AT
SD03.3	Bringing Software Design Thinking To Chip Design	Tomi Rantakari, ChipFlow, GB

26th Workshop Analog Circuits

26th Workshop Analog Circuits 

12.03.2026 and 13.03.2026

at Leibniz University Hannover

The workshop series offers a platform to present one's own ideas and discuss results with science and industry. The focus is on integrated analog and mixed-signal circuits.

The workshop will take place on 12.03.2026 and 13.03.2026 in the Royal Horse Stable of the University of Hannover.  Registration - Participation in the workshop is free of charge.

The programme will be compiled after the call for papers has been completed and is avalable online 

In the run-up to the 26th Workshop on Analog Circuits, the DE:Sign cooperation event on the topic of "Open Source Tools for Analog Design" will take place on the morning of 12.03.2026. In this event, the funded projects will present their current status on open design tools and methods for analogue design. Participants will receive an overview of the contribution of the respective projects to the development of technology open, accessible, and sustainable design chains in the sense of the DE:Sign guideline.

If you have any questions, please contact the organizers by e-mail at: analog2026@ims.uni-hannover.de

Aalto Microelectronics Fair

Aalto Microelectronics Fair

March 20, 2026, 9.00-15.30

Aalto Yliopisto, Kandidaattikeskus, H304, Otakaari 1, 02150 Espoo

Time	Session
8:30–9:00	Morning coffee
9:00–9:15	Opening Aleksi Korsman
	Keynotes
9:15–10:00	Keynote 1: “OpenPDK - Global Scholar Platform”, Wladek Grabinski, Open PDK Initiative
10:05–10:50	Keynote 2: “Open Source Design Tools in SME IC Design Companies”, Ari Paasio, Kovilta
	Research overviews
11:00–11:15	Research overview: Kari Stadius
11:15–11:30	Research overview: Prof. Marko Kosunen
11:30–11:45	Research overview: Prof. Kwantae Kim
11:45–12:45	Lunch (and posters)
12:45–13:15	Student talk: “Five years of RISC‑V processor design at Aalto”, Aleksi Korsman
13:15–13:45	Student talk: “Beyond Neural Networks: Overcoming the Symbolic Bottleneck via Approximate Logarithm Acceleration”, Lingyun Yao
	Posters
13:45–14:00	Poster intro
14:00–15:00	Posters with coffee and snacks
15:00–15:30	Feedback and closing

Should you have any questions, please email Marko Kosunen

[chapter] Compact/SPICE Modeling

Wladek Grabinski and Daniel Tomaszewski

Compact/SPICE Modeling

In: Rudan, M., Brunetti, R., Reggiani, S. (eds) 

Springer Handbook of Semiconductor Devices

DOI 10.1007/978-3-030-79827-7_34

Abstract: The microelectronics and nano-electronics industry strongly relies on compact models to reduce a new microelectronic product development costs. The goals of this review are to highlight critical issues for the development of compact models for microelectronics and nano-electronics. In this chapter, we’ve covered the main principles of the compact device modeling. Also discussed are the possibilities of integrating compact models into circuit simulation and design tools, with an emphasis on the Verilog-A standardization, which simplify model implementation into EDA tool.

 

[mos-ak] [OpenPDK] IHP Analog Academy

IHP Analog Academy

https://lnkd.in/eQnNX4ug

We, IHP Analog Academy, are excited to present this deep dive into analog, RF, and mixed-signal IC design, powered by open-source FOSS CAD/EDA tools and the IHP Open PDK.

This hands-on course is designed for engineers, researchers, and students eager to gain practical experience with the SG13G2 process at the 130nm technology node. Originally hosted on-site at IHP in Frankfurt (Oder), participants spent five intensive days exploring everything from fundamental analog simulation to advanced RF, 3D EM modeling, and mixed-signal integration. And now we're excited to release it to the open-source community!

The course covers:

- Bandgap reference design and simulation using the gm/Id methodology

- RF design of a 50 GHz Medium Power Amplifier with EM simulation

- Mixed-signal integration and verification of an 8-bit SAR ADC

Each module emphasizes a real-world design flow using tools like:

ngspice, Xyce, KLayout, OpenEMS, QUCS, and Python for data analysis.

Over time, we will expand the repository with:

- More modules

- Updated toolchain support

- Improvements to existing flows

Explore the IHP Open PDK:

- Open PDK GitHub Repository https://github.com/IHP-GmbH/IHP-Open-PDK 

- Interactive Help via ChatGPT https://chat.openai.com

Note: This is not an introductory IC design course. A basic understanding of electronics and microelectronics is assumed. We're proud to contribute this initiative to the community to help lower the barrier to IC design using open-source tools. We encourage contributions via GitHub Issues or Pull Requests! Your feedback and contributions, are welcome!

Lead Author: Phillip Ferreira Baade-Pedersen

Co-Author: Christian Wittke

The Development of this course is funded by the public German project FMD-QNC (16ME083) from BMFTR (Federal Ministry of Research, Technology and Space / Bundesministerium für Forschung, Technologie und Raumfahrt): https://www.elektronikforschung.de/projekte/fmd-qnc

#opensource #analog #mixedsignal #rf #design

[C4P] ICEE 2025

7th International Conference on Emerging Electronics (ICEE 2025)

Hilton Embassy Manyata Business Park, Bengaluru (IN)

December 13-16, 2025

Upcoming ICEE 2025 is a flagship IEEE EDS four-day conference, organized to foster cutting-edge discussions and collaborations in semiconductor technologies. ICEE 2025 will feature a diverse range of sessions, including, Technical and rump sessions, Industry-academia discussions, Plenary talks by distinguished experts, Policy sessions on the future of semiconductor technologies.

ICEE 2025 invites papers (4 page Abstract submission deadline: Aug.25 2025) on a diverse and comprehensive range of topics that span materials, processes, devices, circuits, systems, modeling, and reliability. This program is curated by an international team of academic and industry leaders. This edition of ICEE is especially important, given the ambitions of major global economies (such as USA, EU, Japan, India, etc.) in semiconductor manufacturing. This focus is reflected in the composition of ICEE's technical program and organizing committee, with top industry leaders on board. ICEE'25 edition plans to offer 3 Plenary Talks, 5 Keynote Talks, 150+ Invited and Platform/Oral Talks, 100+ Posters, Tutorial Sessions, Evening Industry Sessions, and Industry Exhibits with 800+ International Audiences and Industry Participation. The conference will offer opportunities to contribute, network, learn, collaborate and grow in the areas listed below. For the contributed papers, please find below the call for paper, ICEE themes/tracks, submission guidelines and 4-page abstract templates. In case of questions, please feel free to write to us at secretary@ieee-icee.org. Please keep checking the website and our social media handles for new updates [read more]

[book] From Code to Chip

Jakob Ratschenberger and Harald Pretl

From Code to Chip:

Open-Source Automated Analog Layout Design

pp: XV, 120 Publisher: Springer Cham (10 January 2025)

eBook ISBN 978-3-031-68562-0

This book shows how the layout of an analog circuit can be automatically generated in a fully open-source way. Based on an exemplary design flow, it introduces and explains the necessary steps for transforming a SPICE netlist into a layout, which can be inspected by the open-source layout editor Magic VLSI. This is done by using the industry’s first open-source process design kit SKY130. Furthermore, the implementation of the design flow in the programming language Python is available as open-source on GitHub. 

Authors' Affiliations

Johannes Kepler University, Linz, Austria

Table of contents (8 chapters)

• Front Matter pp. i-xv
• Download chapter PDF 
• Introduction pp. 1-4
• Theoretical Basics pp. 5-13
• Circuit Capturing pp. 15-36
• PDK—Design Rule Capturing pp. 37-41
• Placement pp. 43-55
• Routing pp. 57-71
• Experimental Results pp. 73-99
• Outlook pp. 101-103
• Back Matter pp. 105-120

 

SSCS April Technical Webinar

SSCS April Technical Webinar

Getting Started with Open Source Silicon, Presented By: Matthew Venn

Abstract: In this presentation, Matt Venn will share his experience of getting started with chip design using the free and open source tools. Going from zero to 20 chips in 3 years, there are plenty of successes and failures to share. Matt will then move on to sharing the best resources, inspirational example projects, and showcase some of his own tools. The presentation will finish with a demonstration showing just how easy and cheap it is to get your own chip manufactured today.

Biography: Matt Venn is a science & technology communicator and electronic engineer. He has been involved with open source silicon for the last 3 years and has sent 20 chips for manufacture. He has helped over 600 people learn the tools, with 300 people taking part in manufacturable designs:

• https://zerotoasiccourse.com/
• https://tinytapeout.com

Date: 2024-04-19 Time: 11 AM ET

Location Webinar - Online

Contact Aeisha VanBuskirk – a.vanbuskirk@ieee.org

Register Here

[FOSSDEM 2024] Open PDK Initiative

FOSDEM 2024 was a two-day event organized by volunteers to promote the widespread use of free and open source software. Took place at the ULB Solbosch campus in the beautiful city of Brussels (Belgium), FOSDEM is widely recognized as the best FOSS conference in Europe.

There were two DevRooms to discuss the status and further FOSS CAD/EDA IC design tools developments and open PDK initiative:

• Libre-SOC, FPGA and VLSI DevRoom
• Verilog-AMS in Gnucap
• FOSS CAD/EDA tools supporting the open access PDK initiative
• Open Hardware and CAD/CAM DevRoom
• ngspice circuit simulator - stand-alone and embedded into KiCad

FOSDEM'24 Inauguration Session

ISHI-kai January 2024 event

2024年1月イベント「オープンソースPDK団体」勉強会国内外のオ
ープンソースPDKやEDAの状況について、キーマンに語っていただきます

With the recent rise in the semiconductor industry, the movement of open source PDK and EDA in Japan and overseas has become active. Therefore, in this study session, key people will talk about the status of open source PDK and EDA in Japan and overseas.

Schedule

Friday, January 26, 2024, 18:00-21:00 (Reception: 18:30)

Venue (onsite)

Google Shibuya Office
3-21-3 Shibuya, Shibuya-ku, Tokyo
Shibuya Stream Google reception meeting

Online Broadcast: 

Google Meet: https://meet.google.com/ksa-tjaw-ges

Participation Fee

free

Timetable

Time	Speaker	Title	Lecture Outline
Until 18:30	ISHI-kai	reception	The entrance to the facility closes at this time, so if you are participating locally, please come by this time as much as possible.
18:00 ～ 18:30	ISHI-kai	Chat time	-
18:30 ~ 19:15 (Lecture: 30min, Q&A: 15min)	Takeshi Hamamoto Minimal Fab Propulsion Organization Device Engineer	minimal Fab open PDK	1) What is a minimal fab 2) openPDK 3) Design Contest at Semicon 2023
19:15 ~ 20:00 (Lecture: 30min., Q&A: 15min.)	Junichi Okamura IEEE Senior Member	OpenPDK and the World	-
20:00 ~ 20:45 (Lecture: 30min., Q&A: 15min.)	@noritsuna	About the upcoming open source PDK shuttle	(To be released at a later date)
21:00	ISHI-kai	closing

What is ISHI-kai?

The association was named ISHI-kai (Inter-linked Society on Homemade IC Kai). The name was conceived from the Society Community (Association) that handles open (democratized) ISHI = stone = Silicon = semiconductors (ASIC/LSI/IC) and connects various fields.

OpenMPW (Open Multi Project Wafer), which appeared as a forerunner, is a shuttle program created by Google investing in Efabless, and includes the tools necessary for making semiconductors (ASIC/LSI/IC) (EDA/PDK) to ISHI manufacturing in IC fabs). This is exactly the "openness of semiconductors (ASIC/LSI/IC) and EDA/PDK" of the open source movement (democratization of software) that started with GNU!

Therefore, this association was established as a user society community (association) that focuses not only on experts in semiconductors (ASIC/LSI/IC) in the past, but also on those who see the potential of the open source movement of semiconductors (ASIC/LSI/IC) in the future and those who want to create new semiconductors (ASIC/LSI/IC).

We/ISHI-kai will continue to work toward a world where semiconductors (ASIC/LSI/IC) and EDA/PDK can be used by everyone, just as OSs, compilers, libraries, apps, electronic boards, 3D CAD and 3D printers that we/ISHI-kaire only available to experts can now be used by everyone as open source software, open hardware, open modeling, etc.

As for the future activity plan, we/ISHI-kai have a policy of revolutionizing the semiconductor (ASIC/LSI/IC) field by involving people from other fields, and we/ISHI-kai will hold events such as hands-on seminars for ultra-beginners for other fields and in-depth study sessions for experts, form a team to challenge the OpenMPW shuttle and Chipathon from around the world, and Maker we/ISHI-kai would like to participate in events such as Faire, so thank you.

Precautions

As events move online, we/ISHI-kai ask participants to act in accordance with the spirit of the Code of Conduct. If you have any problems, please contact the organizer. If it is judged that there is no improvement in the request even if there is no abuse such as vandalism or malicious intent, we/ISHI-kai may respond on a case-by-case basis. 

https://www.contributor-covenant.org/ja/version/2/0/code_of_conduct/

Acknowledgements

Thanks to the kindness of Google for providing a real/onsite venue.

[webinar] Open Source Silicon Landscape

Unveiling the Open Source Silicon Landscape: 

a cutting-edge approach for the European semiconductor industry

5 December 2023

Who should attend and why:

• Policymakers at the regional, national, and European level who want to strengthen their respective semiconductor ecosystem while collaborating and contributing to the Union’s industry as a whole
• Research and academia representatives who are interested in deepening their knowledge or discovering the potential of the Open Source Silicon landscape
• SMEs in the semiconductor industry who aim to expand and innovate their business by using a cutting-edge approach
• Start-ups that are eager to elevate their business to the next level by embracing vanguard strategies
• Citizen scientists and the general public who would like to have a better understanding of the new horizons in the semiconductor landscape
• Experts active in industrial development who are interested in integrating potential new approaches

Registration:

The event is free of charge, but registration is mandatory. Registrants will receive the link to access the event by email.

Agenda:

11:00 - 11:05	Welcome
11:05 - 11:10	Introducing Open Source Silicon
11:10 - 11:20	BACKGROUND Open source silicon between software and hardware Background
11:20 - 11:40	POLICY BRIEF PRESENTATION Open source silicon’s position in the semiconductor value chain
11:40 - 12:35	PANEL Key opportunities and threats relevant to open source silicon strategies
12:35 - 12:45	Q&A and conclusions

[video] Interviews from FSiC, Paris, 2023

Interviews from the Free Silicon Conference, Paris, 2023

The 2023 Free Silicon Conference (FSiC) took place in Paris (Sorbonne Université, 4 Place Jussieu, Paris) on July 10 - 12 2023 (Monday to Wednesday). The conference brought together experts and enthusiasts who want to build a complete Free and Open Source CAD ecosystem for designing analog and digital integrated circuits. The conference covered the full spectrum of the design process, from system architecture, to layout and verification.

Interviews with selected Free Silicon Conference Participation by Matt Venn are available online:

00:00 FSiC 2023 Intro, Matt Venn

00:23 Luca Alloatti, FSiC Organizing Committee

01:59 Thomas Benz, ETH Zurich

06:05 Jørgen Kragh Jakobsen, IC Works - Open Source Chip Design

08:57 Thomas Parry, SPHERICAL

11:05 Rene Scholz, IHP Microelectronics

14:06 Dan Fritchman, UC Berkeley
18:41 Harald Pretl, Johannes Kepler University Linz

All the conference proceedings (slide presentations and prerecorded talks) are also available at the FSiC website.

[paper] Chip-Chat

Jason Blocklove, Siddharth Garg, Ramesh Karri, and Hammond Pearce^

Chip-Chat: Challenges and Opportunities in Conversational Hardware Design

arXiv preprint arXiv:2305.13243 [cs.LG] 22 May 2023

New York University, NY USA

^University of New South Wales Sydney, Australia

Abstract: Modern hardware design starts with specifications provided in natural language. These are then translated by hardware engineers into appropriate Hardware Description Languages (HDLs) such as Verilog before synthesizing circuit elements. Automating this translation could reduce sources of human error from the engineering process. But, it is only recently that artificial intelligence (AI) has demonstrated capabilities for machine-based end-to-end design translations. Commercially available instruction-tuned Large Language Models (LLMs) such as OpenAI’s ChatGPT and Google’s Bard claim to be able to produce code in a variety of programming languages; but studies examining them for hardware are still lacking. In this work, we thus explore the challenges faced and opportunities presented when leveraging these recent advances in LLMs for hardware design. Using a suite of 8 representative benchmarks, we examined the capabilities and limitations of the state of the art conversational LLMs when producing Verilog for functional and verification purposes. Given that the LLMs performed best when used interactively, we then performed a longer, fully conversational case study where a hardware engineer co-designed a novel 8-bit accumulator-based microprocessor architecture. We sent the benchmarks and processor to tapeout in a Skywater 130nm shuttle, meaning that these ‘Chip-Chats’ resulted in what we believe to be the world’s first wholly-AI-written HDL for tapeout.

Fig: Processor synthesis information - Above (a) Components. Left: (b) Final processorGDS render by ‘kLayout’, I/O ports on left side, grid lines = 0.001 um.

Opportunities: Still, when the human feedback is provided to the more capable ChatGPT-4 model, or it is used to co-design, the language model seems to be a ‘force multiplier’, allowing for rapid design space exploration and iteration. In general, ChatGPT-4 could produce functionally correct code, which could free up designer time when implementing common modules. Potential future work could involve a larger user study to investigate this potential, as well as the development of conversational LLMs specific to hardware design to improve upon the results.

OpenPDK Networking Workshop

OpenPDK, OpenTooling and Open Source Design

An Initiative to Push Development

Date:
Networking Workshop FMD-QNC on 27-28 June 2023
Location:
IHP; Im Technologiepark 25; 15236 Frankfurt (Oder)
Contact:
Sergei Andreev; Phone: +49 335 5625 523

Free Registration: 

OnLine

The workshop is organised by IHP and FMD (Research Fab Microelectronics Germany) within the framework of the FMD-QNC Project.

Within the project FMD-QNC analog circuit design with open source software shall be enabled. For this purpose, both the open source design tools and a process design kit of the semiconductor technology used must support the entire design flow with sufficient quality. IHP provides its 130 nm BiCMOS technology SG13G2 for open source design. This technology is particularly suited for high frequency and mixed signal design applications. While basic tool support already exists for digital circuit design, it is still very rudimentary for analog designs and especially for high frequency designs. A considerable effort has to be put into the development of the design tools as well as into the creation of the technology specific Process Design Kit (PDK).

The 2-day workshop is intended to promote exchange and networking between tool developers, the PDK developers at IHP and designers. Tool developers are to present the capabilities of the tools as well as planned enhancements. Designers are to present ideas that can be used for training chip designers. Requirements for open source design tools for digital design, mixed signal design, and high frequency design are to be highlighted.

Discussions will identify and prioritize gaps for a complete design flow in the open source tools and PDK. The workshop will thus help to concrete the planning for the Open Design Platform and to create a roadmap for future work.

Presentation	Presenter/Institution	Timeline
Day 1
Welcome by coordinator FMD-QNC	Dr. Andreas Bruning Research Fab Microelectronics Germany	9:00-9:10
Introduction FMD-QNC project status and IHP OpenPDK Roadmap	Dr. Rene Scholz IHP	9:10-9:30
Status OpenPDK and OpenTooling for SG13G2 BiCMOS technology	Sergei Andreev IHP	9:30-10:00
An Ultra-Low-Power High-Density Wireless Biomedical Sensing System	Prof. Harald Pretl Johannes Kepler University Linz	10:00-10:30
Teaching digital design by using open-source EDA tools	Prof. Steffen Reith Rhein Main University of Applied Sciences	10:30-11:00
Coffee break		11:00-11:40
CMOS Rail-to-Rail Operational Amplifier for HPGe Radiation Detector	Prof. Herman Jalli Ng Karlsruhe University of Applied Sciences	11:40-12:10
Design-flow approaches for mmWave and sub-THz integrated transceiver circuits for radar and communication	Sasha Breun FAU Erlangen	12:10-12:40
Lunch break		12:40-13:40
TBD	Dr. Frank K. Gurkaynak ETH Zurich	13:40-14:10
TBD	Joachim Hebeler Karlsruhe Institute of Technology	14:10-14:40
Coffee break		14:40-15:10
TBD	Prof.  Dietmar Kissinger Ulm University	15:10-15:40
LibMan - an easy way to manage your open source design flow	Dr. Anton Datsuk IHP	15:40-16:10
Get together (Barbecue)		17:00-…
Day 2
ngspice - status and future developments	Prof. Holger Vogt	9:00-9:20
DMT - Python Toolkit for Device Modeling	Mario Krattenmacher SemiMod	9:20-9:40
OpenVAF - Next Generation Verilog-A Compiler with ngspice integration	Mario Krattenmacher SemiMod	9:40-10:00
Coffee break		10:00-10:40
Best practices for implementing and optimizing KLayout DRC and LVS decks	Matthias Köfferlein	10:40-11:00
Generating DRC and LVS Runsets for KLayout	Dr. Andreas Krinke TU Dresden	11:00-11:20
OpenEMS in open source EDA	Jan Taro Svejda University of Duisburg-Essen	11:20-11:40
Lunch break		11:40-12:40
Panel discussion on the roadmap – open source tools for IC design Topics: Digital design flow Analog design flow Challenges in RF design	Dr. Norbert Herfurth IHP Panelists: TBD	12:40-14:10