[mos-ak] [online publications] 16th International MOS-AK Workshop Silicon Valley, Dec. 13, 2023

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Enabling Compact Modeling R&D Exchange

www.mos-ak.org

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Recent, 16th International MOS-AK Workshop hosted by Keysight Technologies in Santa Clara, CA 95051, on Dec. 13, 2023, featured invited talks from EDS Distinguished Lecturers (DL) and leading experts in the field. The selected R&D topics include self-heating and trapping effects in GaN HEMTs, Si2 CMC updates, integrated antennas, European open source PDK Initiative, re-energizing analog design using the open-source ecosystem, SPICE modeling of Si, GaN and SiC power FET devices, new models to capture generic device physics, quantum computing and simulation, open source neuromorphic computing, and custom IC designs using open source OpenFASOC. The workshop presentations are listed below:

T_0	Opening and MOS-AK Intro Wladek Grabinski MOS-AK (EU)
T_1	Welcome and A Brief History of Keysight Nilesh Kamdar Keysight EDA
T_2	Accurate Modeling of the Self-Heating and Trapping Effects in GaN HEMTs DOI:10.5281/zenodo.1042343 Yiao Li Keysight Technologies
T_3	Si2 Compact Model Coalition 2023 Updates DOI: 10.5281/zenodo.10423502 Peter M. Lee and Colin Shaw Si2 Compact Model Coalition

T_4	Some efforts toward the modeling of integrated antennas DOI: 10.5281/zenodo.10401753 Roberto S. Murphy-Arteaga, IEEE EDS DL INAOE, Puebla, Mexico
T_5	European Open Source PDK Initiative DOI: 10.5281/zenodo.10423518 Wladek Grabinski, IEEE EDS DL MOS-AK (EU)

T_6	Re-Energizing Analog Design using the Open-Source Ecosystem DOI: 10.5281/zenodo.10423729 Boris Murmann University of Hawaii
T_7	SPICE Modeling of Si, GaN and SiC Power FET Devices DOI: 10.5281/zenodo.10423740 Bogdan Tudor Silvaco, Inc.
T_8	A Transformer-Based Foundation Model to Capture Generic Device Physics DOI: 10.5281/zenodo.10423765 Hyunbo Cho Alsemy Inc.

T_9	Quantum Computing and Simulation DOI: 10.5281/zenodo.10423785 Hiu Yung Wong San Jose State University
T_10	Open Source Neuromorphic Computing DOI: 10.5281/zenodo.10423809 Jason Eshraghian // online Neuromorphic Computing Group at UC Santa Cruz
T_11	Accelerating custom Circuits using OpenFASOC DOI: 10.5281/zenodo.xxx Mehdi Saligane // online UMich (US)

The MOS-AK Association plans to continue its standardization efforts by organizing future compact modeling meetings, workshops and panels around the globe thru the 2024 Year, including:

• FOSDEM, Bruxelles (BE) Feb. 3-4, 2024
• MOS-AK/EDTM, Bangalore (IN) March 3-6, 2024
• 6th MOS-AK/LADEC, Guatemala City (GT) May 8-10, 2024
• Special CM Session, MIXDES, Gdańsk (PL) June 27-29, 2024
• 8th Sino MOS-AK Workshop (CN), August 2024
• 21st MOS-AK at ESSERC, Bruges (BE) Sept. 9-12, 2024
• 17th MOS-AK/Silicon Valley, (CMC/IEDM Timeframe) Dec. 2024

-- W.Grabinski on the behalf of the International MOS-AK Committee

22122023

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IFS2024 - Semiconductor Industry Update

Semiconductor Industry Update Webinar 

Registration Now Open

Last year's IFS forecast called for a double-digit decline in 2023, contrary to perceived wisdom favored ongoing industry growth. Our forecast proved right.

With 2023 now firmly in the rear-view mirror, all eyes are fixed on 2024's outlook. This time around, industry consensus favors strong double-digit growth, driven by Gen AI, strong demand for GPUs, and a recovery in memory and, on an annualized basis, the math clearly shows the chip industry value growth is powering ahead.

But, inventory levels remain stubbornly high with wafer fab utilization rates low, casting a shadow over the future
• When will unit growth return?
• Can the world economy continue to defy gravity forever?
• Is the current surge in ASPs sustainable?
• Is the 'recovery' real or just a reflection of last year's bad data providing a weak base for comparison?

Find out the answer to these and other key questions at Future Horizons' IFS2024 annual industry update outlook webinar, Jan 16, 2024, 3pm UK GMT
https://www.futurehorizons.com/page/136/Industry-Update-Webinar

Register at https://us02web.zoom.us/webinar/register/7416911384194/WN_NHk_8-UiS3KSh90PA3dptw

What Will You Hear
This one-hour broadcast will focus on the chip industry outlook, including:
• What happened in 2023 vs. last year's January forecast?
• What is the market forecast for 2024?
• What's happening in CapEx, investment, and onshoring trends?
• What are the likely opportunities and implications for the industry?
• How to build resilient business strategies, plus
• Opportunity to ask specific questions in advance, during and after the webinar.

Who Should Attend
All companies, small and large, from startups to established market leaders.
• Key decision-makers in the design, manufacture, or supply of semiconductors.
• Government organizations in industry, trade, and investment.
• Those involved in M&A, investment, or finance within the electronics industry.
• Senior industry executives planning future marketing strategy.

Your Trusted Industry Advisor
Founded in 1989, Future Horizons has been in the business of forecasting and analyzing the semiconductor market for 35 years and has been a trusted advisor to governments, investors, startups, and most of the top global semiconductor firms. Our forecast track record and hands-on industry experience, dating back to the first commercial IC, longer than any other analyst and most industry execs, make this a must-attend event for key decision makers in semiconductors, electronics, and all related industries. We always present accurate and insightful analysis at these events, consistently helping our clients save time and money with our insightful and accurate analysis of the industry.

Fee
For a small investment of UK £150 plus £30 UK VAT you will gain accurate industry insight to make good strategic decisions in these uncertain times
• Discount available for 3 or more attendees from the same company/organisation
• Can't attend? No need to miss out, order the webinar video recording and slides instead.
• If already registered or not directly suitable for you, please pass it to a colleague or associate.
• The event can also be repeated on-line or in-person in-house for your added convenience and flexibility.

Register now at https://us02web.zoom.us/webinar/register/7416911384194/WN_NHk_8-UiS3KSh90PA3dptw

Malcolm Penn
Chairman & CEO

Follow us on Twitter, like us on Facebook and join our Linked In Group and receive regular industry news, information and comments.
Registered Company: 4380991 / mail@futurehorizons.com

[paper] PSP RF Model

Xiaonian Liu1, 2, and Yansen Liu1, 2

Scalable PSP RF Model for 0.11 µm MOSFETs

Progress In Electromagnetics Research Letters, Vol. 113, 43–51, 2023

1 School of Physics and Electronics, Hunan Normal University, Changsha 410081, China
2 Key Laboratory of Physics and Devices in Post-Moore Era, College of Hunan Province, Changsha 410081, China.

Abstract: An accurate, efficient and scalable SPICE model is essential for modern integrated circuits design, especially for radio frequency (RF) circuit design. A PSP based scalable RF model is extracted and verified in 0.11 µm CMOS manufacturing process. The S parameter measurement system and open-short de-embedding technique is applied. The macro-model equivalent subcircuit and parameters extraction strategy are discussed. The extracted model can match the de-embedded S parameters data well. By combining the model parameters’ dependencies on each geometry quantity, the scalable expression of parameters with all geometry quantities included can be obtained. This work can be a reference for the RF MOSFETs modeling and RF circuit design.

Fig: The PSP RF subcircuit model and its S-par s fitting

results of NMOS with Wf = 2 µm, Lf = 0.12 µm, nf = 16

Acknowledgment: This work is supported by the National Natural Science Foundation of China under Grant 62204083, and the Youth Fund of Education Department of Hunan Province under Grant 21B0057.

[paper] Device for the Detection and Quantification of Exosomes

Diego Barrettino1, Christoph Zumbühl1, Raphael Kummer1, Markus Thalmann1, Carolina Balbi2, Giuseppe Vassalli2, Rosane Moura Dos Santos3 and Jean-Michel Sallese3

Low-Cost Portable Medical Device for the Detection and Quantification of Exosomes

2023 IEEE SENSORS, Vienna, Austria, 2023, pp. 1-4,

doi: 10.1109/SENSORS56945.2023.10325271. 

1 Lucerne University of Applied Sciences and Arts (HSLU), Institute of Electrical Engineering, CH- 6048 Horw, Switzerland
2 Istituto Cardiocentro Ticino, Via Tesserete 48, CH-6900 Lugano, Switzerland
3 Swiss Federal Institute of Technology Lausanne (EPFL), EPFL SCI STI EDLAB, Station 11, CH-1015 Lausanne, Switzerland

Abstract: The design, fabrication and testing of a low-cost portable medical device for the detection and quantification of exosomes is presented in this paper. The portable medical device comprises a sensor array that can detect the presence of exosomes and quantify its concentration, a microfluidic device that handles the human serum containing the exosomes, and all the necessary readout and control electronics. Measurement results performed with exosomes showed that the portable medical device can detect exosomes with a concentration of 2.5x108 /µL thus paving the way to a wide range of diagnostic applications.

Fig. Exosome immobilized on top of the functionalized (antibody CD63 +protein G
+ polydopamine + graphene oxide) JLFET biosensor and tagged with a gold (Au) nanoparticle attached to an exosome biomarker (antibody CD31)

[C4P] 50th ESSERC, Sept. 9-12. 2024, Bruges (BE)

CALL FOR PAPERS

https://www.esserc2024.org/papers

The aim of ESSERC (European Solid-State Electronics Conference) is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits. It is a continuation of the past ESSDERC-ESSCIRC conferences. The level of integration for system-on-chip design is rapidly increasing. This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers and system designers is necessary. 

ESSERC is governed by a Steering Committee and consists of Plenary Keynote Presentations, invited papers and session on technology, circuits and joint papers bridging both device and circuit communities, respectively. 

PAPERS SUBMISSION DEADLINE: APRIL 5, 2024

Papers submitted for review must clearly state:

• The purpose of the work
• How and to what extent it advances the state-of-the art
• Specific results and their impact

Only work that has not been previously published or submitted elsewhere will be considered. Submission of a paper for review and subsequent acceptance is considered as a commitment that the work will not be publicly available prior to the conference. Measurement results or calibration against measured data is required to support the claims of the submitted paper.

After selection of papers, the authors will be informed about the decision of the Technical Program Committee by e-mail by 24 May 2024.

At the same time, the complete program will be published on the conference website. An oral presentation will be given at the Conference for each accepted paper. No-shows will result in the exclusion of the papers from any conference related publication. The submitted final PDF files should be IEEE Xplore compliant.

For each paper independently, at least one (co-)author is required to register for the Conference (one registration one paper policy). Registration fees and deadlines will be soon available

CONFERENCE TRACKS (although not limited, papers are solicited for the following main topics):

1. Advanced Technology, Process and Materials
2. Analog, Power and RF Devices
3. Compact Modeling and Process/Device Simulation
   
   TCAD and advanced simulation techniques and studies, compact/ SPICE modeling of electronic, optical, organic, emerging, and hybrid devices and their IC implementation and interconnection. Verilog-A models of semiconductor devices (including bio/ med sensors, MEMS, microwave, RF, high voltage and power, emerging technologies, and novel devices), parameter extraction, reliability and variability, performance evaluation and open-source benchmarking/implementation methodologies. Modeling of interactions between process, device and circuit design, design/technology co-optimization, foundry/fabless interface strategies. Numerical, analytical, statistical modeling and simulation of electronic, optical and hybrid devices, interconnect, isolation, and 2D/3D integration. Simulations of material properties and fabrication processes. Advanced physical phenomena (quantum mechanical and non-stationary transport phenomena, ballistic transport). Mechanical and/or electro-thermal modeling and simulation. Simulations of reliability aspects of materials and devices.
4. Analog Circuits
5. Data Converters
6. RF & mm-Wave Circuits
7. Frequency Generation Circuits
8. Digital Circuits & Systems
9. Power Management
10. Wireless Systems
11. Wireline and Optical Circuits and Systems
12. Emerging Computing Devices and Circuits
13. Architectures and Circuits for AI and ML
14. Devices & Circuits for Sensors, Imagers and Displays

WHY BRUGES?

Bruges is a place that lives and breathes history. Visiting this historic city means travelling back in time to the Middle Ages. It is both magical and authentic. Brugge in medieval times was known as a commercial metropolis in the heart of Europe. 

Bruges is one of Europe’s best-preserved cities, evidenced by the fact that its historic city center has been designated an UNESCO World Heritage Site. The iconic spires of its cathedral and bell tower, its cobbled streets, winding canals and whitewashed façades are almost painfully picturesque.

In the 15th century, Brugge was the cradle of the Flemish Primitives and a center of patronage and painting development for artists such as Jan van Eyck and Hans Memling. Many of their works were exported and influenced painting styles all over Europe. Exceptionally important collections have remained in the city until today. Travelers from all over the world are coming to Belgium to visit Bruges.

[mos-ak] [Final Program] 16th International MOS-AK Workshop Silicon Valley, Dec. 13, 2023

Arbeitskreis Modellierung von Systemen und Parameterextraktion 

Modeling of Systems and Parameter Extraction Working Group

16th International MOS-AK Workshop

Silicon Valley, December 13, 2023

Together with Keysight Technologies team, the MOS-AK workshop host as well as International MOS-AK Board of R&D Advisers and all the Extended MOS-AK TPC Committee, we have the pleasure to invite to consecutive, 16th International MOS-AK Workshop in Silicon Valley.

Scheduled 16th MOS-AK SPICE/Compact Modeling Workshop organized in the Silicon Valley, aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and TCAD/EDA tool developers and vendors. The content will be beneficial for anyone who needs to learn what is really behind the FOSS CAD/EDA IC simulation in modern device models in Open Access PDKs.

The MOS-AK workshop program is available online:

<https://www.mos-ak.org/silicon_valley_2023/>

Venue:

Keysight Technologies

5301 Stevens Creek Boulevard

Santa Clara, CA 95051

Online Free Registration; 

any related enquiries can be sent to registration@mos-ak.org

-- W.Grabinski on the behalf of International MOS-AK Committee

WG291023

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[paper] Noise modeling for cryogenic applications

Giovani Britton^1,2, Salvador Mir², Estelle Lauga-Larroze², Benjamin Dormieu¹, Quentin Berlingard^3,4, Mickael Casse³ and Philippe Galy¹

Noise modeling using look-up tables and DC measurements for cryogenic applications.

VLSI-SoC 2023 - 31st IFIP/IEEE International Conference on Very Large Scale Integration,

Oct 2023, Sharjah, United Arab Emirates.

DOI: 10.1109/VLSI-SoC57769.2023.10321896
hal-04305746

1STMicroelectronics, Crolles, France

2Univ. Grenoble Alpes, CNRS, Grenoble-INP, TIMA

3Univ. Grenoble Alpes, CEA, LETI

4Univ. Grenoble Alpes, CNRS, Grenoble-INP, IMEP-LAHC

Abstract : There is today a lack of mature transistor-level compact models for the simulation of integrated circuits at cryogenic temperatures. This is particularly the case for the simulation of the noise behavior which is critical for most applications. In this paper, we aim at an efficient prediction of the white noise behavior of basic amplifying stages working at RF frequencies and cryogenic temperatures. For this, we propose the use of DC measurements that are incorporated in a LookUp Table (LUT) and fed to a mathematical noise model. We illustrate the approach for the case of a transistor in common source configuration. The results of circuit simulation of the noise parameters in the standard temperature range are very close to the estimation of the same parameters using the LUT with just DC measurements. The approach can be readily extended to the analysis of circuits with multiple components. Next, the LUT approach is used for estimating the noise parameters at cryogenic conditions, considering DC measurements that have been carried out at these temperatures. The paper illustrates the feasibility of carrying out a cryogenic design using a LUT-based approach while accurate compact models are not yet available.

Fig : Measurement data and EKV or ACM generated parameters are added

to the LUT generated by the interface between EDA tools

Acknowledgments : This work was supported by the French program Conventions Industrielles de Formation par la Recherche (CIFRE) and Labex MINOS of French program ANR-10-LABX-55-01.

[PhD] ULTRARAM™ at Lancaster University

Lancaster University, Physics Department has three open PhD Projects, Programmes & Scholarships

• Scaling ULTRARAM™ on FindAPhD.com
  The PhD project will further advance the development of ULTRARAM™ memory. ULTRARAM™ is an ultra-efficient, multi-award-winning memory technology that combines the non-volatility of flash with the speed and endurance of dynamic random access (DRAM).
• Vertical-cavity surface-emitting lasers for below-screen consumer (and other) applications at Lancaster University on FindAPhD.com
  The PhD project will further develop a patented approach to implementing vertical-cavity surface-emitting lasers (VCSELs) operating at telecoms wavelengths
• Novel compound-semiconductor logic for computing applications on FindAPhD.com
  The PhD project will further develop a patent-pending alternative approach to digital logic that abandons the CMOS paradigm underpinning computing

Supervisor: Prof. M. Hayne

Application deadline: 29 February 2024 // Competition Funded PhD Project (UK Students Only)

Chips JU Launch Event

 

https://www.chipsjulaunchevent.eu/

Agenda Day 1: Embracing the voice of stakeholders

12:00 - 14:30	Registration
13:00 - 15:30	Networking lunch and exhibition "Walk of Fame" opening and guided tour
15:30 - 15:40	Welcome and opening, Jari Kinaret, Executive Director of the Chips JU
15.40 - 16:00	Keynote speech, Thierry Breton, European Commissioner for Internal Market
16:00 - 16:20	Intro speeches "EU strategic autonomy and economic security"
	Nikolai Setzer, CEO, Continental AG
	Jaime Martorell, Special Commissioner for Microelectronics and Semiconductors, Spain
16:20 - 17:20	1st Panel discussion with a moderator
	Thomas Skordas, DDG, CNECT, European Commission
	Pierre Barnabé, CEO, Soitec
	Roger Dassen, CFO, ASML
	Luc Van den hove, President and CEO, imec
	Frédérique Le Grévès, President & CEO, STMicroelectronics France
	Cinzia Silvestri, CEO, Bi/ond
	Alain Jarre, Chairman and CEO, RECIF Technologies
17:20 - 17:40	Coffee break
17:40 - 18:00	Intro speeches "Maintaining and boosting European technology leadership"
	Jochen Hanebeck, CEO, Infineon Technologies AG
	Jo Brouns, Flemish Minister for Economy, Innovation, Work, Social Economy, and Agriculture
18:00 - 19:00	2nd Panel discussion with a moderator
	Signe Ratso, Deputy Director-General, DG RTD, European Commission
	European Semiconductor Board Member (name tbc)
	Stefan Finkbeiner, CEO, Bosch Sensortec GmbH
	Maurice Geraets, Executive Director, NXP Semiconductors Netherlands B.V.
	Sébastien Dauvé, CEO, CEA-Leti
	Eva Maydell, Member of the European Parliament
	Joost van Kuijk, CEO/CMO, Adimec
19:00 - 19:05	Closing remarks by the moderator
19:15	Shuttle bus to the social event venue
20:00 - 22:30	Social event and walking dinner “Art & History Museum of Belgium”

Day 2 Part 1: Presentation of the Initiative

08:00 - 09:00	Registration & welcome coffee
09:00 - 09:10	Intro speech by Lucilla Sioli, Director DG CNECT.A, European Commission
09:10 - 09:40	New advanced pilot lines: Yves Gigase, Head of Programmes, Anton Chichkov, Programme Officer, Chips JU
09:40 - 09:55	Network of competence centre: Yves Gigase, Head of Programmes, and Anton Chichkov, Programme Officer, Chips JU
09:55 - 10:10
	Cuting-edge quantum chips: Gustav Kalbe, acting Director DG CNECT C, and
	Christian Trefzger, Policy Officer, DG CNECT, European Commission
10:10 - 10:25	Chips Fund: EC, EIB, EIC joint presentation
10:25 - 10:55	Q&A
10:55 - 11:25	Coffee break, networking and exhibition
11:25 - 12:15	Interactive session on Advanced design platform: Marco Ceccarelli and Matihew Xuereb, Policy Officers, DG CNECT, European Commission
12:15 - 13:40	Networking lunch.

Day 2 Part 2: Chips JU R&I Programme

13:40 - 13:50	Intro speech by Jean-Luc di Paola-Galloni, Chair of the Chips JU Private Members Board
13:50 - 14:50	3rd Panel discussion with a moderator
	Lucilla Sioli, Director, DG CNECT.A, European Commission
	Michael Paulweber, Director Global ITS Research & Technology, AVL List
	Régis Hamelin, CTO, Blumorpho
	Francis Balestra, Director of Research CNRS
	Ferdinand Bell, Head of Public Collaborative Programs, NXP Semiconductors, Germany GmbH
	Christoph Kutier, Vice-Chair, Fraunhofer Microelectronics Group/FMD
	Bert de Jonge, CEO, VERUM
14:50 - 15:20	ECS SRIA 2024 – What is new? Patrick Cogez, Technical Director, AENEAS IA
15:20 - 15:50	Upcoming Chips JU calls and focus topics
	Yves Gigase, Head of Programmes, and Anton Chichkov, Programme Officer, Chips JU
15:50 - 16:00	Closing remarks Jari Kinaret, Executive Director of the Chips JU
16:00 - 17:30	Coffee break, networking and exhibition

[webinar] Open Source Silicon Landscape

Unveiling the Open Source Silicon Landscape: 

a cutting-edge approach for the European semiconductor industry

5 December 2023

Who should attend and why:

• Policymakers at the regional, national, and European level who want to strengthen their respective semiconductor ecosystem while collaborating and contributing to the Union’s industry as a whole
• Research and academia representatives who are interested in deepening their knowledge or discovering the potential of the Open Source Silicon landscape
• SMEs in the semiconductor industry who aim to expand and innovate their business by using a cutting-edge approach
• Start-ups that are eager to elevate their business to the next level by embracing vanguard strategies
• Citizen scientists and the general public who would like to have a better understanding of the new horizons in the semiconductor landscape
• Experts active in industrial development who are interested in integrating potential new approaches

Registration:

The event is free of charge, but registration is mandatory. Registrants will receive the link to access the event by email.

Agenda:

11:00 - 11:05	Welcome
11:05 - 11:10	Introducing Open Source Silicon
11:10 - 11:20	BACKGROUND Open source silicon between software and hardware Background
11:20 - 11:40	POLICY BRIEF PRESENTATION Open source silicon’s position in the semiconductor value chain
11:40 - 12:35	PANEL Key opportunities and threats relevant to open source silicon strategies
12:35 - 12:45	Q&A and conclusions

[C4P] LAEDC 2024

CALL FOR PAPERS & POSTERS

LAEDC 2024 R&D topics of interest include, but are not limited to:

All electron-based devices Electron Devices for Quantum Computing RF-MMW-5G Semiconductor-, MEMS- and Nanotechnologies Packaging, 3D integration Sensors and actuators Display technology Modeling and simulation Reliability and yield Device characterization Reliability Agrivoltaics

Flexible electronics Biomedical Devices Circuit-device interaction Novel materials and process modules Technology roadmaps Electron device engineering education Electron device outreach Optoelectronics, photovoltaic and photonic devices and systems Humanitarian Projects STEM Initiatives Energy harvesting 2D Materials and Devices

IMPORTANT DATES:

• Paper submission deadline: January 15, February 19, 2024
• Author notification: April 1, 2024
• LAEDC Conference Dates: MAY 8-10 2024

SPECIAL SESSIONS:

• MOS-AK Workshop
• IEEE EDS MQ
• LAEDC Summer School
• IEEE WIE/YP Session
• Humanitarian Technology Session

ABOUT GUATEMALA:

Guatemala, country of Central America. The dominance of an Indigenous culture within its interior uplands distinguishes Guatemala from its Central American neighbours. The origin of the name Guatemala is Indigenous, but its derivation and meaning are undetermined. Some hold that the original form was Quauhtemallan (indicating an Aztec rather than a Mayan origin), meaning “land of trees,” and others hold that it is derived from Guhatezmalha, meaning “mountain of vomiting water” - referring no doubt to such volcanic eruptions as the one that destroyed Santiago de los Caballeros de Guatemala (now Antigua Guatemala), the first permanent Spanish capital of the region’s captaincy general. The country’s contemporary capital, Guatemala City, is a major metropolitan centre. Quetzaltenango, in the western highlands, is the nucleus of the Indigenous population.

Chipsalliance Technology Update - Nov. 2023

November 9, 2023

Check out the presentations below, and watch the replay here

• Project Open Se Cura (slides)
  Kenny Vassigh, Bangfei Pan, Cindy Liu, Kai Yick, Google, Michael Gielda, Antmicro, Brian Murray, Verisilicon
• Caliptra Workgroup Update (slides)
  Andres Lagar-Cavilla, Google
• Enabling UVM testbenches in Verilator (slides)
  Michael Gielda, Karol Gugala, Antmicro
• FuseSOC: Package manager and build abstraction tool for FPGA/ASIC development (slides)
  Olof Kindgren, Qamcom
• CHIPYard: An Open Source RISC-V Design Framework (slides)
  Sagar Karandikar, U.C. Berkeley

Watch the Replay

[paper] Boropheneand Metal Interface

Vaishnavi Vishnubhotla, Sanchali Mitra, and Santanu Mahapatraa

First-principles based study of 8-Pmmn boropheneand metal interface

J. Appl. Phys. 134, 034301 (2023); doi: 10.1063/5.0144328

DOI 10.1063/5.0144328

Nano-Scale Device Research Laboratory, Department of Electronic Systems Engineering, 

Indian Institute of Science (IISc) Bangalore, India

Abstract: Borophene, the lightest member of mono-elemental 2D materials family, has attracted much attention due to its intriguing polymorphism. Among many polymorphs, digitally discovered 8-Pmmn stands out owing to its unique tilted-Dirac fermions. However, the property of interfaces between 8-Pmmn and metal substrates has so far remained unexplored, which has critical importance of its application in any electronic devices. Here, with the help of density functional theory, we show that the unique tilted-Dirac property is completely lost when 8-Pmmn borophene is interfaced with common electrode materials such as Au, Ag, and Ti. This is attributed to the high chemical reactivity of borophene as observed from crystal orbital Hamilton population and electron localization function analysis. In an effort to restore the Dirac property, we insert a graphene/hexagonal-boron-nitride (hBN) layer between 8-Pmmn and metal, a technique used in recent experiments for other 2D materials. We show that while the insertion of graphene successfully restores the Dirac nature for all three metals, hBN fails to do so while interfacing with Ti. The quantum chemical insights presented in this work may aid in to access the Dirac properties of 8-Pmmn in experiments.

FIG: (a) Top and side views of 3 × 3 × 1 supercell of 8-Pmmn borophene. The lattice parameters are a = 3.26 Å, b = 4.52 Å, and h = 2.19 Å. The inner and ridge atoms are denoted by blue and green atoms, respectively. (b) Crystal orbital Hamilton population (COHP) analysis and (c) electron localization function (ELF) plot for graphene and 8-Pmmn borophene.

Acknowledgments: The authors acknowledge the Supercomputer Education and Research Center (SERC), Indian Institute of Science (IISc), Bangalore, for CPU- and GPU-based computations. The computational charges were aided by the Mathematical Research Impact Centric Support (MATRICS) scheme of Science and Engineering Research Board (SERB), Government of India, under Grant No. MTR/2019/000047.

[paper] PSP RF Model

Xiaonian Liu^{1, 2} and Yansen Liu¹

A Scalable PSP RF Model for 0.11 µm MOSFETs

Progress In Electromagnetics Research Letters, Vol. 113, 43–51, 2023

DOI :10.2528/PIERL23081405

1 School of Physics and Electronics, Hunan Normal University, Changsha 410081, China.
2 Key Laboratory of Physics and Devices in Post-Moore Era, College of Hunan Province, Changsha 410081, China.

Abstract : An accurate, efficient and scalable SPICE model is essential for modern integrated circuits design, especially for radio frequency (RF) circuit design. A PSP based scalable RF model is extracted and verified in 0.11 CMOS manufacturing process. The S parameter measurement system and open-short de-embedding technique is applied. The macro-model equivalent subcircuit and parameters extraction strategy are discussed. The extracted model can match the de-embedded S parameters data well. By combining the model parameters’ dependencies on each geometry quantity, the scalable expression of parameters with all geometry quantities included can be obtained. This work can be a reference for the RF MOSFETs modeling and RF circuit design.

Fig: The RF PSP Model Subcircuit

Acknowledgment : This work is supported by the National Natural Science Foundation of China under Grant 62204083, and the Youth Fund of Education Department of Hunan Province under Grant 21B0057.

Cutting-Edge IC Design Workshop

U.S. - Japan Collaboration Workshop
(Phase-1)
Tuesday, December 5 2023; 8:00 - 12:00 AM  (JST)
Wednesday, December 6 2023; 8:00 - 12:00 AM (JST) 

Online

The semiconductor industry is facing a number of challenges in building a stable supply chain. The importance of semiconductors was reaffirmed at the global level, and various initiatives were announced to revitalize and support the semiconductor industry, including investment in infrastructure development and human resource development for cutting-edge foundries. Against this backdrop, it is hoped that the creation of next-generation semiconductor technology and the further expansion of the industry will be achieved based on strong cooperation between Japan and the United States. As a phase 1 toward this goal, this workshop will discuss cutting-edge IC design technologies such as open source IC design, ecosystem construction, and human resource development. This workshop was supported by the U.S. Consulate in Fukuoka.

Application deadline is December 12. Please apply individually for DAY-1 and DAY-1the following form (you can also apply for only one of them).

• DAY-1 Application (Click here)
• DAY-2 Application (Click here)

[Participation fee] Free

[Notice] Simultaneous interpretation is available in English and at ZOOM Webinar.

DAY-1: Dec. 5th, 8:00-11:35 AM (JST)

8:00 - 8:05 Opening Remark and Overview of the Workshop, Mehdi Saligane, University of Michigan, Koji Inoue, Kyushu University

8:05 - 8:10 Welcome Remarks from the U.S. Consulate in Fukuoka

8:10 - 8:40 TBD, Steve Kosier, Skywater

8:40 - 9:10 The Emerging Ecosystem of Open-Source IC Design: IEEE SSCS Activities and Future Goals, Boris Murmann, Chair of the SSCS TC OSE, University of Hawaii

9:10 - 9:40 Human resource development for Semiconductor Technologies in Fukuoka, Koji Inoue, Fukuoka Semiconductor Reskilling Center/Kyushu University, Hideharu Kanaya, Kyushu University,

9:40 - 9:50 Break

9:50 - 10:20 Lab to Fab in the Cloud: Semiconductor Innovation at Amazon, David Pellerin, AWS 

10:20 - 10:50 TBD, Kai Yick, Google Research ML

10:50 - 11:20 Analog and Mixed-Signal IC Design Automation, David Wentzloff, University of Michigan

11:20 - 11:30 Q&A + Panel Discussion

11:30 - 11:35 Conclusion, Mehdi Saligane, University of Michigan

DAY-2: Dec. 6th, 8:00-11:30 AM (JST)

8:00 - 8:05 Opening Remark and Overview of the Workshop, Mehdi Saligane, University of Michigan, Koji Inoue, Kyushu University

8:05 - 8:35 Innovation by Collaboration: CHIPS Alliance, Rob Mains, CHIPS Alliance, Linux Foundation 

8:35 - 9:05 Developing CMOS+X Platforms for Artificial Intelligence and Beyond, Brian Hoskins, NIST 

9:05 - 9:35 Agile-X: Agile Chip Design and Fabrication Platform, Makoto Ikeda, University of Tokyo

9:35 - 9:45 Break

9:45 - 10:15 The future of semiconductor : chips and chiplets, Dan J. Dechene, IBM Research

10:15 - 10:45 AI Chip Design Center – open hub for chip innovation -, Kunio Uchiyama, National Institute of Advanced Industrial Science and Technology  

10:45 - 11:15 Democratizing EDA Tooling and Chip Design, Johan Euphrosine, Google (Tentative)

11:15 - 11:25 Q&A + Panel Discussion

11:25 - 11:30 Conclusion and Overview of the phase-2 workshop activities, Mehdi Saligane, University of Michigan, Koji Inoue, Kyushu University

[お問い合わせ] ic-design-ws 'at' slrc.kyushu-u.ac.jp　（ 'at' を @ で置き換えてください）

GoIT project at Open Source Experience Event

Laboratoire d'Informatique de Paris 6 (LIP6) Sorbonne and CNRS will attend Open Source Experience event on 6-7 December in Paris to present GoIT project

Come and join the European open source community meeting!!

[ read more... ]

Free Silicon Foundation Roadmap

The Free Silicon Foundation (F-Si) has prepared a list of recommendations and a roadmap for the European Commission for the development of open-source silicon in the EU. 

The full text is available to download here 

Executive summary 

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Chapter 1: Table of Contents

After a brief introduction (Chapter 2) which defines the necessary terminology and introduces the political background (Chapter 3), in Chapter 4 we argue that open-source Electronic Design Automation (EDA) tools and open-source silicon are essential instruments to achieve many of the goals set by the Chips Act. This chapter does not provide any recommendations yet.

Chapter 5 we analyse the “Design Platform” foreseen by the Chips Act in the light of the feedback obtained by interrogating multiple European SMEs involved in chip design. Potential problems were identified with the foreseen cloud-based infrastructures. These are related with security, privacy, the too large spectrum of tools, forced upgrades, increased control by EDA vendors, and increased risk of discovery of patent infringement. To mitigate these problems we recommend to support, besides cloud installations, also local EDA installations, and we recommend to support open-source EDA flows besides the commercial flows.

Chapter 6 we analyse the role of standards and standards-setting bodies in the context of open-source. In particular, we highlight how open-source development has needs which are substantially different from the mainstream industrial approach to standardization. We highlight in particular a set of necessary conditions that, in our experience, standards must fulfil in order to be adopted by the open-source community.

Chapter 7 we discuss academia. We argue that academia can and should play a significant role in the development of open-source EDA tools and open-source silicon. For fostering open-source development in universities, we recommend that the metrics to evaluate academics should include open-source projects aside to publications, citations, etc. Next, we highlight how there are two classes of academics, which are both essential: developers of EDA tools and users of EDA tools. Given the near complete disappearance of the former, we recommend that a new generation of professors is hired to develop open-source EDA tools and to revive the corresponding knowledge in Europe. In this Chapter we finally highlight how people who have not been exposed to open-source solutions often don’t appreciate its potential therefore creating a cultural bias. In conclusion, also because of other conflicts of interest, we recommend introducing new and independent personnel in academia.

Chapter 8 we present an open letter about ecological sustainability. The signatories of this letter recommend: 

1. more sober technology, 

2. the “6Rs” (Refurbish, Reuse, Repair, Reliability, Reduce, Recycle) for electronic devices, 

3. external and independent auditors for Life Cycle Assessments (LCAs), 

4. encouraging world-wide regulations to limit the environmental impact in the ICT sector.

Chapter 9 we discuss patent threats and possible upcoming problems for open-source development. Unfortunately, we have no consolidated recommendations yet.

Chapter 10 we briefly discuss possible implications of Artificial Intelligence on chip design. We warn that the advent of AI might produce an increased silicon-technology gap between owners of AI and the others. We recommend putting in place mechanisms to prevent a further power unbalance between large and small actors. A possible mechanism consists of guaranteeing a fully open (i.e. down to silicon) development of AI. 

Chapter 11 we discuss the Cyber Resilience Act (CRA) and we recommend that: 

1. the concept of open-silicon is added to the CRA, and 

2. open-silicon is recognized as a key ingredient to achieve some of the hardware cybersecurity goals.

Chapter 12 we finally present a roadmap for open-source silicon development. First we make a list of open-silicon chips which can be realised immediately or in the near future and highlight their impact. We then recommend to rapidly finance projects similar (in scope and management) to the DARPA OpenRoad project for open-source EDA development. This is our strongest and most important recommendation. Next, we list all political handles that policy can operate to foster open-silicon development. Finally, we present a recommended timeline for the different activities and we conclude.

Acknowledgements

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This document was prepared with help from many people working in university, small organizations and SMEs. Starting from the end of September 2023, it has been reviewed by about twenty people. We are very grateful to all of them for their inputs and feedback.

Funding and disclaimer 

---

This work is funded by the European Union. Views and opinions expressed are however those of the author(s) only and do not necessarily reflect those of the European Union or of the European Commission. Neither the European Union nor the European Commission can be held responsible for them.

Project name: “Go IT!” ID number: 101070660

Verilog-AMS in Gnucap

Mixed-Signal Modelling and Simulation with Verilog-AMS

Verilog-AMS is a standardised modelling language widely used in analog and mixed-signal design, but without an open reference implementation. The language supports high-level behavioural descriptions as well as structural descriptions of systems and components. This Project will make substantial progress towards a Gnucap based free/libre Verilog-AMS implementation. Gnucap is a modular mixed-signal circuit simulator, and has been released under a copyleft license with the intent to avoid patent issues. Gnucap provides partial support for structural Verilog and encompasses an analog modelling language that has influenced the Verilog standards. We will enhance data structures and algorithms in Gnucap, and improve Verilog support on the simulator level. We will implement a Verilog-AMS behavioural model generator targetting Gnucap with the intent to support simulators with similar architecture later on. The project's own website:

http://gnucap.org/dokuwiki/doku.php/gnucap:projects:nlnet:verilogams

Task 1. modelgen-verilog: Provide a replacement for ADMS

Task 2. Verilog-AMS compliance on the simulator level

Task 3. Compiler optimisations

Acknowledgement: This project was funded through the NGI0 Entrust Fund, a fund established by NLnet with financial support from the European Commission's Next Generation Internet programme, under the aegis of DG Communications Networks, Content and Technology under grant agreement No 101069594.

The first IC designed in B&H has been fabricated

On 18 May 2023, the Faculty of Electrical Engineering of the University of Banja Luka, Bosnia and Herzegovina, presented the first integrated chip of semiconductor technology, which represents the most sophisticated technological process.

FIG: IC oscillates as per design specification and pre/post-layout simulation

Faculty of Electrical Engineering has become one of the higher education institutions where one of the most important engineering disciplines of today and the future is studied according to the best world programmes, with the direct application of industrial standards in teaching, thus preparing the next generation of engineers to be the flywheel of economic revival through innovation.

It took students and professors at the Faculty of Electrical Engineering five years to develop the first integrated chip. Student Vanja Žerić is one of the innovators of this idea, and he states that the knowledge gained was a prerequisite to start the production.

"We are talking about two chips, one of which is a stabilizer or a voltage regulator that has the ability to stabilize the voltage from 1.8 to 3.3 volts. The second was an oscillator that is essential for a chip like this.'', Vanja said.

Assistant Professor of the Faculty of Electrical Engineering, Aleksandar Pajkanović, PhD, who teaches several courses in the field of chip development at the Department of Electronics, pointed out that the CMOS technological process is the most sophisticated technology that exists in the world, and that it is commercially available, and that they have mastered it and demonstrated it through the implementation of the chip.

"It is particularly important to point out that this technology is significant as a military and industrial strategic resource as well as in higher education, and the most important thing is that we are now among world universities that study this field. It is usual for the implementation of chips to be done in doctoral studies, but with great efforts we managed to do it with third-year students. This chip is not intended for commercialization, as we developed it to demonstrate the capability and mastery of such advanced technology." Prof. Pajkanović stressed.

The details of that development are in the following references:

[1] A. Pajkanovic, “On the Application of Free CAD Software to Electronic Circuit Curricula”, 3rd IcETRAN2016, Zlatibor, Serbia, 2016

[2] A. Pajkanovic and Z. Ivanovic, “A Report on Recent Development in Application of Free CAD Software to IC Curricula,” 5th IcETRAN2018, Palic, Serbia, 2018.

[3] A. Pajkanovic, “Introducing Chisel to IC Design Curriculum at the Faculty of Electrical Engineering in Banja Luka”, 8th RISCV Workshop, Barcelona, Spain, 2018

[4] A. Pajkanovic, “CMOS IC Design from Schematic Level to Silicon within IC Curricula Using Free CAD Software”, INDEL2020, Banja Luka, B&H, 2020.

[5] A. Pajkanovic, “Free/Open Source EDA Tools Application in Digital IC Design Curricula”, 8th IcETRAN2021, Stanisici, B&H, 2021.

[6] A. Pajkanovic, “Open Source CMOS General Purpose Operational Amplifier", MIEL 2021

[7] A. Pajkanovic, "Free IC Design in Education", PSSOH 2021

[read more...]

 

[workshop] FreeCAD 3D parametric modeler

PSG COLLEGE OF TECHNOLOGY, COIMBATORE

9 DECEMBER, 2023

About the FreeCAD

FreeCAD is a general purpose open source parametric 3D CAD modeller. FreeCAD is aimed directly at mechanical engineering and product design but, being very generic, also fits in a wider range of uses around engineering, such as architecture, finite element analysis, 3D printing, and other tasks. FreeCAD offers tools to produce, export and edit solid, full-precision models, export them for 3D printing or CNC machining, create 2D drawings and views of your models, perform analyses such as Finite Element Analyses, or export model data such as quantities or bills of materials. FreeCAD features tools similar to other popular CAD packages and therefore also falls into the category of CAD, PLM, CAx, CAE and BIM. It is a feature based parametric modeler with a modular software architecture, making it possible to provide additional functionality without modifying the core system. As with other CAD modelers, it has many 2D components in order to sketch planar shapes or create production drawings. FreeCAD is also fundamentally a social project, as it is developed and maintained by a community of developers and users united by their passion for FreeCAD. In precise FreeCAD is:

• Made to build for the real world
• A powerful solid-based geometry kernel
• A wi(l)dly parametric environment
• File formats frenzy
• A parametric constraints-based 2D sketcher
• A large (and growing) multi-specialty ecosystem

About the Workshop 

The workshop will be conducted through spoken tutorial videos of 10 minutes duration. After the workshop, a link for the video tutorials will be shared to the participants for further learning. As it is an open source software, FreeCAD can be used free of cost for educational and industrial design purposes. Participants of this workshop can install this software on their laptop during this workshop and take it with them. Target participants of this workshop include: practicing engineers, faculty members, research scholars and students.

Registration details
The registration fee for the participants (Inclusive of GST) :

• Faculty members / Students / Research Scholars : Rs. 900/-
• Industry participants : Rs.1200/-

No TA/ DA/ ACCOMMODATION will be provided. Payment of registration fee for the workshop can be made through online mode

https://forms.gle/xqcQLSTnJcYLK2DNA

Last date for registration: November 25, 2023

For any queries, contact

The Organizing Secretaries,

FreeCAD Workshop, PSG College of Technology,

Peelamedu, Coimbatore-641004

email : vsk.amcs@psgtech.ac.in / mrp.prod@psgtech.ac.in

Mobile : 9952418357

[paper] Surface-Potential-Based Compact Modeling

M. Miura-Mattausch, T. Iizuka, H. Kikuchihara, H. J. Mattausch, and S. Saha

Evolution of Surface-Potential-Based Compact Modeling

IEEE EDS NEWSLETTER

OCTOBER 2023 VOL. 30, NO. 4 ISSN: 1074 1879

Abstract: Conventionally, a compact model of an electronic device is developed for utilization in circuit simulation. This means that the main task of the compact model is to accurately describe the characteristics of a device as a function of the applied voltages by simple equations in order to predict the performance of circuits using this device with sufficient precision. This overview article focuses on the compact modeling of the metal-oxide-semiconductor field-effect transistor (MOSFET)-device structure, which has the largest variety of applications. However, the modeling methodology is valid for any type of transistor or electronic device. The development of the compact modeling approach, based on the potential distribution induced within a transistor, is reviewed. The purpose of a compact model is to describe the transistor characteristics in a simple but accurate way, to enable correct circuit-performance prediction. Therefore, the basic physics of observed phenomena must be modeled by simplified and yet physically correct equations. To meet such requirements, potential-based modeling is a natural fit. A compact model and TCAD are both based on the same transistor equations. The difference is that TCAD considers the distribution of all physical quantities within a device, and a compact model integrates these distributions to calculate transistor characteristics at its nodes. The shortcomings of resulting simplifications, introduced for analytical integration, can be examined using TCAD, to identify observed phenomena still missing in the compact modeling. In this way, compact modeling is performed by learning from measurements macroscopically and from TCAD microscopically.

Fig: Schematic of a HV LDMOS FET (top) 

and its potential distribution (bottom)