Jul 30, 2016

Researchers develop ultrathin, transparent oxide #TFT for #wearable #display https://t.co/Z314WvUs3J #papers


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July 29, 2016 at 11:51PM
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Jul 29, 2016

Optimization of CMOS-ISFET-Based Biomolecular Sensing: Analysis and Demonstration in DNA Detection https://t.co/t6fbc5xrR3 #papers


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July 29, 2016 at 10:25AM
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Jul 26, 2016

#papers #TINA: Creating Analog Components with #Verilog-A https://t.co/TGtUANqt6b


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July 26, 2016 at 01:44PM
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#nanoHub #papers: A Verilog-A Compact Model for Negative Capacitance FET https://t.co/m05FR5u0gR https://t.co/QpJoXZ3m98


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July 26, 2016 at 01:42PM
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ESOF 2016 - #EC #Research & #Innovation https://t.co/CENYnfTIhl #papers #openinnovation https://t.co/TwOJ8wntia


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July 26, 2016 at 10:06AM
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ESOF 2016 - #EC #Research & #Innovation https://t.co/CENYnfTIhl #papers #openinnovation


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July 26, 2016 at 10:06AM
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Jul 25, 2016

FOSDEM 2017 - Next FOSDEM: 4 & 5 February 2017 https://t.co/xH7IAxXLyr #papers https://t.co/TlZzFKZVB9


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July 25, 2016 at 04:59PM
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FOSDEM 2017 - Next FOSDEM: 4 & 5 February 2017 https://t.co/xH7IAxXLyr #papers


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July 25, 2016 at 04:59PM
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Implementation and quality testing for HICUM/L2 compact models implemented in Verilog-A https://t.co/xXnNhTZcgb #papers


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July 25, 2016 at 02:11PM
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Jul 22, 2016

VeSFET is a twin-gate device with 3D vertical terminals and channel based on SOI conventional CMOS https://t.co/AGiySLvzUj #papers


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July 22, 2016 at 03:18PM
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Jul 20, 2016

Leti-UTSOI Compact Model

The Leti-UTSOI compact model is the only one to be totally dedicated to the FDSOI technology. In its recent version, the Leti-UTSOI model has reached its maturity. In collaboration with STM, its robustness was validated by successfully complying with the full test suite recommended by the CMC. The Leti-UTSOI model is now currently used at STM in the IC design division. It is now available in an industrial design-kit. The documentation and some model cards (typical) are available below:
The Leti-UTSOI Verilog-A code can also be obtained contacting LETI UTSOI Developers.


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Location: Grenoble, France

Leti-UTSOI Compact Model

The Leti-UTSOI compact model is the only one to be totally dedicated to the FDSOI technology. In its recent version, the Leti-UTSOI model has reached its maturity. In collaboration with STM, its robustness was validated by successfully complying with the full test suite recommended by the CMC. The Leti-UTSOI model is now currently used at STM in the IC design division. It is now available in an industrial design-kit. The documentation and some model cards (typical) are available below:
The Leti-UTSOI Verilog-A code can also be obtained contacting LETI UTSOI Developers.


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Location: Grenoble, France

LETI Compact Modeling Links

LETI compact modeling links points to the Workshops and Conferences:

MOS-AK (Modeling of Systems and Parameter Extraction Working Group)
S3S (IEEE SOI-3D Subthreshold Microelectronics Technology Unified Conference)

IEDM (IEEE International Electron Devices Meeting)
VLSI  (29th International Conference on VLSI Design)
SISPAD (Simulation of Semiconductor Processes and Devices)

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Location: Grenoble, France

Jul 17, 2016

Simple Yet Effective ESD Testing Methods for Higher Reliability https://t.co/5CaZptRQQr #semi #papers


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July 17, 2016 at 01:08PM
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Jul 16, 2016

#Intel Adds Tsu-Jae #King #Liu, Taking Step Toward #Board Diversity https://t.co/vV9ndoVPtf #semi #feedly #papers


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July 16, 2016 at 05:52PM
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Jul 14, 2016

A flexible #memristive #model with simplex basis function https://t.co/iuavZ4S7Qc #papers


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July 14, 2016 at 02:19PM
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A flexible #memristive #model with simplex basis function https://t.co/iuavZ4S7Qc #papers


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July 14, 2016 at 02:19PM
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Jul 8, 2016

3year €33m European project REFERENCE to extend RF-SOI technology for above-1Gb/s 4G+ modules https://t.co/zlMd9QABXm #tech #feedly #papers


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July 08, 2016 at 11:34PM
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An improved model for substrate in RF SOI MOSFET varactor https://t.co/iK16GyX82y #papers #feedly


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July 08, 2016 at 10:12PM
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[mos-ak] [2nd Announcement and Call for Papers] MOS-AK ESSDERC/ESSCIRC Workshop; Lausanne September 12, 2016

 MOS-AK ESSDERC/ESSCIRC Workshop  
  Lausanne September 12, 2016 
   2nd Announcement and Call for Papers  

 Together with International MOS-AK Board of R&D Advisers: Larry Nagel, Omega Enterprises Consulting (USA), Andrei Vladimirescu, UCB (USA); ISEP (FR) and local workshop coordinator Jean-Michel Sallese, EPFL (CH) as well as all the Extended MOS-AK TPC Committee, we have pleasure to invite to the 14th consecutive MOS-AK ESSDERC/ESSCIRC Workshop which will be held at Swisstech Convention Centre in Lausanne on September 12, 2016. Planned MOS-AK workshop is organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. 

Important Dates:
  • Call for Papers - June 2016
  • 2nd Announcement - July 2016
  • Final Workshop Program - August 2016
  • MOS-AK Workshop - Sept.12 2016
Venue:
Swisstech Convention Centre EPFL                                        
Route Louis-Favre 2
CH-1024 Ecublens

Topics to be covered include the following among other related to the compact/SPICE modeling :
  • Advances in semiconductor technologies and processing
  • Compact Modeling (CM) of the electron devices
  • Verilog-A language for CM standardization
  • New CM techniques and extraction software
  • Open Source TCAD/EDA modeling and simulation
  • CM of passive, active, sensors and actuators
  • Emerging Devices, TFT, CMOS and SOI-based memory cells
  • Microwave, RF device modeling, high voltage device modeling
  • Nanoscale CMOS devices and circuits
  • Technology R&D, DFY, DFT and reliability/ageing IC Designs
  • Foundry/Fabless Interface Strategies
Speakers: tentative list of MOS-AK Experts:
  • Marco Bellini, ABB (CH)
  • Mike Brinson, LondonMet, (UK)
  • Matthias Bucher, TUC (GR)
  • Mansun Chan, UST (HK)
  • James Greer, ASCENT, Tyndall (IE)
  • Benjamin Iniguez, URV (SP)
  • Alexander Kloes, THM (D)
  • Muhammad Nawaz, ABB (SE)
  • Denis Rideau, ST (F)
  • Jean-Michel Sallese, EPFL (CH)
  • Andrei Vladimirescu, UCB (USA); ISEP (FR); Keynote
  • Lining Zhang, UST (HK)
Online MOS-AK Abstract Submission:
Prospective authors should submit an abstract to abstracts@mos-ak.org

Online Workshop Registration:
http://esscirc-essderc2016.epfl.ch/registration
(any related inquiries can be sent to register@mos-ak.org)

Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication in a special issue of the International Journal of High Speed Electronics and Systems

Extended MOS-AK Committee
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Location: Lausanne, Switzerland

Jul 6, 2016

"Measurement and analysis techniques for device agnostic electrical cha" #papers by James E Moore https://t.co/ryg6hgFn5f


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July 06, 2016 at 08:56AM
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Jul 1, 2016

Dual-Gate JFET #Modeling https://t.co/Cwroa516sK


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July 01, 2016 at 04:20PM
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Tutorial on Signal Processing in Linux with Octave https://t.co/Lzoeytzqwt #todo #feedly #papers


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July 01, 2016 at 08:13AM
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