[workshop] QC:DCEP 2023

Workshop on

Quantum Computing: Devices, Cryogenic Electronics and Packaging

A Seasonal School of the IEEE Circuits & Systems Society

Tues/Wed, 24-25 October, 2023 at SEMI World Hdqtrs, Milpitas, CA USA

Welcome to the first year of this new Workshop from the IEEE Circuits and Systems Society, organized and run by three Silicon Valley IEEE chapters: Circuits and Systems, Electron Devices and Electronics Packaging.

QC:DCEP 2023 is planned to be a hybrid event, with both in-person and WebEx participation. Registration is now open. On-site seating is limited. Review the Advance Program.

The intent of this workshop is to bring together engineers of electrical, mechanical, materials and computer science disciplines and physicists to describe the state-of-the-art in all the interconnected fields and the opportunities and challenges for future generations of quantum computers.

Confirmed plenary and invited talks:

Technical Challenges facing Quantum Computing with Superconducting Transmon Qubits Dr. Daniel Tennant, Rigetting Computing		Superconducting Multi-Chip Module (SMCM) Rabindra N. Das, MIT Lincoln Laboratory
Introduction to Quantinuum and TKET Dr. Kathrin Spendier, Quantinuum		Understanding and Addressing Challenges in Superconducting Qubit Scale Jennifer Smith, UC-Santa Barbara
Integrated Quantum-Classical Applications with CUDA Quantum Dr. Jin-Sung Kim, NVIDIA		A 22nm FD-SOI-CMOS Scalable Quantum Processor SoC with Fully Integrated Control Electronics at 3.5K Dr. Imran Bashir, Equal1
Network Architecture for a Scalable Spin Qubit Processor Prof. Jonathan Baugh, Univ. of Waterloo		Quantum Computing with Silicon Spins Dr. Dominik Zumbuhl, Univ of Basel
Quantum Error Correction in Bosonic Qubits Marina Kudra, PhD, Intermodulation Products		Thermal Management Challenges in Cryogenic System Integration: Spin Qubit Biasing with a CMOS DAC at mK Temperature Lea Schreckenberg, Forschungszentrum Jülich GmbH

plus additional technical talks 

Drawings will be held for two GeForce RTX-4090 graphics cards, donated by NVIDIA — one will be awarded to an on-site speaker, while the other will be awarded to an on-site attendee. These new gaming accelerators for Windows PCs are not yet on sale. Need not be present to win. We invite you to register for QC:DCEP 2023 using our EventBrite site. Register today!

[C4P] 36th ICMTS 2024

36th International Conference on Microelectronic Test Structures

April 15-18, 2024, Edinburgh, Scotland

Looking for the best opportunity to present and discuss your ideas and results about test structures, measurements and characterization? This is your chance! Join the 36th ICMTS conference. A Tutorial Short Course will precede the main conference. Several of the best measurement, equipment design, and manufacturing experts, will participate in the equipment exhibition and presentations. The conference will bring together designers and users of test structures to discuss recent developments and future directions, in a one-track program, with convivial breaks allowing attendees to discuss and exchange viewpoints and challenges.

A Best Paper award will be presented by the Technical Program Committee. The conference is co-sponsored by the IEEE Electron Devices Society and all accepted papers, if presented, will be submitted for possible inclusion on IEEEXplore®. Original papers are solicited presenting new developments in topics relevant to ICMTS, including but not limited to, test structures, measurements, and results, in the following areas:

• Design
• Methodologies, Verification
• Within-die circuits for process characterization/monitoring
• Design enablement – Characterization and validation of digital and analog libraries
• Devices and Circuit Modelling
• Measurement techniques
• DC, AC and RF measurements: setup, test and analysis
• Reliability test - including thermal stability, failure analysis etc.
• Statistical analysis, variability, throughput increase, smart test strategies
• Use of machine learning and AI in analysis of data sets - parameter extraction etc.
• Wafer probing, within-die measurements, in-line metrology
• Throughput, testing strategies, yield enhancement and process control tests
• Applications
• Emerging memory technologies (single cell, arrays, and application in neural networks)
• Emerging transistor technologies for digital/analog/power applications
• Photonic devices - silicon integration, new displays (OLED, μ-displays)
• Flexible electronics and sensors (organic and inorganic materials)
• M(N)EMS, actuators, sensors, PV cells and other emerging devices

The author’s abstract submission consists of up to four pages in PDF format (font-embedded). The first page should include a title, a 50-word summary, author name(s), full address, contact number and e-mail of the lead author, and any preference for oral or poster session presentation. The body of the abstract should consist of one page of text (800 to 1000 words) and up to two pages of major figures and tables. The selection process will be based on the technical merit and will be highly weighted in favour of abstracts with high test structure content, giving a clear illustration of the test structure and including measurements and data analysis.

The abstract submission deadline is October 27th, 2023.

Abstracts can be submitted via the ICMTS 2024 website www.icmts.net using the “Abstract Submission” link on the front page. Notice of paper acceptance will be sent to the selected authors by 12th January 2024, with instructions for the expanded manuscript preparation for the conference proceedings. The deadline for submission of the final paper will be Early March, 2024 (TBC).

Please join the ICMTS LI group, if you have interest in all things test and measurement.

Details of the venue, hotel, registration, etc. will be posted when available at the ICMTS 2024 official website.

For further technical information, please contact the technical program chair:

Francesco Driussi, Università di Udine

3rd MFEM Community Workshop, October 26, 2023

MFEM is a free, open source, lightweight, scalable C++ library for finite element methods.

Features

• Arbitrary high-order finite element meshes and spaces.
• Wide variety of finite element discretization approaches.
• Conforming and nonconforming adaptive mesh refinement.
• Scalable from laptops to GPU-accelerated supercomputers.
• ... and many more.
• See MFEM Gallery, Publications, Videos and News pages.

MFEM is used in many projects, including BLAST, Cardioid, Palace, VisIt, RF-SciDAC, FASTMath, xSDK, and CEED in the Exascale Computing Project.

Annual workshop 

MFEM host an annual workshop and FEM@LLNL seminar series. The MFEM team has  announced the 3rd MFEM Community Workshop, which will take place on October 26, 2023, virtually, using Zoom for videoconferencing. The goal of the workshop is to foster collaboration among all MFEM users and developers, share the latest MFEM features with the broader community, deepen application engagements, and solicit feedback to guide future development directions for the project.

Registration
If you plan to attend, please register no later than October 19th. There is no registration fee. Zoom details will be distributed to participants prior to the event date. For questions, please contact the meeting organizers at mfem@llnl.gov.

[paper] Model for Cryo-CMOS Subthreshold Swing

Arnout Beckers, Jakob Michl, Alexander Grill, Member IEEE; Ben Kaczer, Marie Garcia Bardon, Bertrand Parvais, Bogdan Govoreanu, Kristiaan De Greve, Gaspard Hiblot, 

and Geert Hellings, Senior Member IEEE

Physics-Based and Closed-Form Model for Cryo-CMOS Subthreshold Swing

in IEEE Transactions on Nanotechnology, vol. 22, pp. 590-596, 2023,

DOI 10.1109/TNANO.2023.3314811.

IMEC, Leuven (B)

Institute for Microelectronics, TU Vienna (A)

Vrije Universiteit Brussel (B)

KU Leuven (B)

Abstract: Cryogenic semiconductor device models are essential in designing control systems for quantum devices and in benchmarking the benefits of cryogenic cooling for high-performance computing. In particular, the saturation of subthreshold swing due to band tails is an important phenomenon to include in low-temperature analytical MOSFET models, as it predicts theoretical lower bounds on the leakage power and supply voltage in tailored cryogenic CMOS technologies with tuned threshold voltages. Previous physics-based modeling required to evaluate functions with no closed-form solutions, defeating the purpose of fast and efficient model evaluation. Thus far, only the empirically proposed expressions are in closed form. This article bridges this gap by deriving a physics-based and closed-form model for the full saturating trend of the subthreshold swing from room down to low temperature. The proposed model is compared against experimental data taken on some long and short devices from a commercial 28-nm bulk CMOS technology down to 4.2 K.

FIG: (a) TEM picture of a mature imec technology node. (b) Electrostatic potential fluctuations near the channel/oxide interface. (c) Gaussian distributed depths of the potential wells. (d) Including the binding energy in the wells in the quantum picture gives a Laplace distribution of P(Eb). (e-f) Convolution (*) of P(Eb) with the sharp-edged 2-D DOS leads to a logistic/Fermi-like DOS function with an exponential tail.

[paper] Characterization and Modeling of SOI LBJTs at 4K

Yuanke Zhang, Yuefeng Chen, Yifang Zhang, Jun Xu, Chao Luo, and Guoping Guo

Characterization and Modeling of Silicon-on-Insulator 

Lateral Bipolar Junction Transistors at Liquid Helium Temperature

IEEE TED Vol. XX, No. XX, preprint arXiv:2309.09257 (2023).

University of Science and Technology of China (USTC), Hefei 230026, Anhui, China

CAS Key Lab ofQuantum Information, Hefei 230026, Anhui, China.

Abstract: Conventional silicon bipolars are not suitable for low-temperature operation due to the deterioration of current gain (β). In this paper, we characterize lateral bipolar junction transistors (LBJTs) fabricated on silicon-on insulator (SOI) wafers down to liquid helium temperature (4 K). The positive SOI substrate bias could greatly increase the collector current and have a negligible effect on the base current, which significantly alleviates β degradation at low temperatures. We present a physical-based compact LBJT model for 4 K simulation, in which the collector current (IC) consists of the tunneling current and the additional current component near the buried oxide (BOX)/silicon interface caused by the substrate modulation effect. This model is able to fit the Gummel characteristics of LBJTs very well and has promising applications in amplifier circuits simulation for silicon-based qubits signals.

Fig: IC (solid lines) and IB (dash lines) versus VBE of LBJT at different temperatures 

under (a) VBOX = 0 V; (b) VBOX = 12 V, VCE = 1 V.

Acknowledgement: The device fabrication was done by Prof. Zhen Zhang’s group in the Angstrom Microstructure Laboratory (MSL) at Uppsala University. Dr. Qitao Hu, Dr. Si Chen, Prof. Zhen Zhang are acknowledged for the device design and fabrication, and the technical staff of MSL are acknowledged for their process support.

Palace: 3D Finite Element Solver for Computational Electromagnetics

Palace, for PArallel LArge-scale Computational Electromagnetics, is an open-source, parallel finite element code for full-wave 3D electromagnetic simulations in the frequency or time domain, using the MFEM finite element discretization library.

Key features:

• Eigenmode calculations with optional material or radiative loss including lumped impedance boundaries. Automatic postprocessing of energy-participation ratios (EPRs) for circuit quantization and interface or bulk participation ratios for predicting dielectric loss.
• Frequency domain driven simulations with surface current excitation and lumped or numeric wave port boundaries. Wideband frequency response calculation using uniform frequency space sampling or an adaptive fast frequency sweep algorithm.
• Explicit or fully-implicit time domain solver for transient electromagnetic analysis.
• Lumped capacitance and inductance matrix extraction via electrostatic and magnetostatic problem formulations.
• Support for a wide range of mesh file formats for structured and unstructured meshes, with built-in uniform or region-based parallel mesh refinement.
• Arbitrary high-order finite element spaces and curvilinear mesh support thanks to the MFEM library.
• Scalable algorithms for the solution of linear systems of equations, including geometric multigrid (GMG), parallel sparse direct solvers, and algebraic multigrid (AMG) preconditioners, for fast performance on platforms ranging from laptops to HPC systems.

Crosstalk Between Coplanar Waveguides Example: Views of the mesh boundaries for these two configurations are shown below. In both cases the computational domain is discretized using an unstructured tetrahedral mesh. 

[workshop] gdsfactory

gdsfactory workshop, UCSB Photonics Society

August 24, 2023 in Henley Hall, UCSB

The first gdsfactory hands-on workshop organized as part of the  UCSB  Photonics Society. Thomas Dorch from Freedom Photonics and Andrei Isichenko presented gdsfactory. Last year gdsfactory seminar by Joaquin Matres, the maintainer of gdsfactory - you can access the video recording here. This workshop was a hands on; things to do before the workshop

1. Install anaconda python 3 on your computer. If you don't have it installed, the links below are for miniconda, a "lightweight" version of anaconda. Windows: link. Mac: link (select if Intel or M1).
2. Download a Python IDE. Either Visual Studio Code or Pycharm. Personally I prefer VS Code
3. Download klayout. Windows: link. Mac: link (works on M1 mac, Ventura 13.4).

gdsfactory team will be running the tutorial using python notebooks (.ipynb). These can be run through JupyterLab, VS code (install this extension), or through Google Colab. You have the option to skip all the steps above and run the notebooks entirely in Google Colab (but with some limitations in klayout integration). You can try it out using this notebooks in this repository, focused on workshop_part1.ipynb. In Google Drive you should have the option to select "open with Google Colaboratory"

Click the "Open in Colab" link above to get started, and save a copy of the notebook to your Google Drive.

Google Drive Links to the notebooks:

https://drive.google.com/file/d/1x6kHQ9nHb1HB4HOEiEr1BG_y5lQ8si3e/view?usp=sharing

https://drive.google.com/file/d/1Ppz-CDrFezfLTIAHeBLYopl6Q4oyt8a4/view?usp=sharing

[Workshop] QIP

Silicon Quantum Information Processing (QIP) Workshop

Glasgow Marriott Hotel

Wednesday, Sept. 20, 2023

Silicon Quantum Information Processing (QIP) is highly appealing due to excellent spin qubit performances and the expertise of the integrated circuit industry in device scaling. Demonstrations of long-lived, high-fidelity silicon qubits, multi-qubit gates and spin–photon coupling, are promising for the control and interconnect of QIP architectures. Recently, spin qubits in related semiconductors (e.g. germanium) have also emerged as promising implementations of scalable quantum hardware. The formidable challenge of scaling these systems to the level required for meaningful computational applications has also brought to the fore the need for robust cryo-CMOS electronics, which will enable fast control and data processing, as well as schemes to correct errors and protect against decoherence. This meeting will bring together leading researchers from the QIP communities of silicon and related semiconductors, as well as cryo-CMOS designers and engineers who are working at different layers of the “quantum stack”.

10:00AM- 10:10AM	Introduction
10:10AM- 10:40AM	Pablo Cova Farina Quantum dot ladders for quantum computation and simulation
10:40AM-11:00AM	Federico Fedele Automatic techniques for fast and automatic all-rf tuning of quantum devices
11:00AM-11:30AM	Mark Johnson Rapid characterisation of over 1000 silicon quantum dots
11:30AM-11:50AM	Break and refreshments
11:50AM-12:20PM	Gian Salis How are hole-spin qubits in Ge/SiGe heterostructures driven and why do they decohere?
12:20PM-12:40PM	Ross Leon Exchange control in a MOS double quantum dot made on a 300mm process
12:40PM-1:10PM	Asen Asenov A Methodology for Cryogenic PDK Re-Centering Using Experimental Data and TCAD Simulations
1:10PM-2:30PM	Lunch
2:30PM-3:00PM	Masoud Babaie A Cryo-CMOS Receiver for Spin Qubit Gate-Based Readout: from Modelling to Implementation and Verification
3:00PM-3:20PM	Mathieu de Krujif Measurement of classical electronics heating a local quantum dot thermometer in silicon
3:20PM-3:40PM	Janne Lehtinen Custom CMOS platform for quantum processor units
3:40PM-4:00PM	Stavroula Kapoulea Towards the Development of Quantum Computing System-On-Chip: Bringing Electronics Closer to Qubits
4:00PM-4:10PM	Concluding remarks
4:10PM-5:00PM	Refreshments
5:00PM-6:00PM	Lab tour
7:00PM-9:00PM	Conference Dinner

[book] Advanced Ultra Low-Power Semiconductor Devices

Advanced Ultra Low-Power Semiconductor Devices

Design and Applications

Edited by Shubham Tayal, Abhishek Kumar Upadhyay, Shiromani Balmukund Rahi, and Young Suh Song

ISBN: 9781394166411 | (C)2023  Hardcover | 306 pages

Description

This outstanding new volume offers a comprehensive overview of cutting-edge semiconductor components tailored for ultra-low power applications. These components, pivotal to the foundation of electronic devices, play a central role in shaping the landscape of electronics. With a focus on emerging low-power electronic devices and their application across domains like wireless communication, biosensing, and circuits, this book presents an invaluable resource for understanding this dynamic field.

Bringing together experts and researchers from various facets of the VLSI domain, the book addresses the challenges posed by advanced low-power devices. This collaborative effort aims to propel engineering innovations and refine the practical implementation of these technologies. Specific chapters delve into intricate topics such as Tunnel FET, negative capacitance FET device circuits, and advanced FETs tailored for diverse circuit applications.

Beyond device-centric discussions, the book delves into the design intricacies of low-power memory systems, the fascinating realm of neuromorphic computing, and the pivotal issue of thermal reliability. Authors provide a robust foundation in device physics and circuitry while also exploring novel materials and architectures like transistors built on pioneering channel/dielectric materials. This exploration is driven by the need to achieve both minimal power consumption and ultra-fast switching speeds, meeting the relentless demands of the semiconductor industry. The books scope encompasses concepts like MOSFET, FinFET, GAA MOSFET, the 5-nm and 7-nm technology nodes, NCFET, ferroelectric materials, subthreshold swing, high-k materials, as well as advanced and emerging materials pivotal for the semiconductor industrys future.

[conference] 10th Micro Nano 2023

10th International Conference "Micro Nano 2023"

Location: Demokritos Congress Center

Dates: November 2nd-5th 2023

The Micro Nano 2023 Organizing Committee is looking forward to welcoming you to Athens to the 10th International Conference on Micro-Nanoelectronics, Micro-Nanosciences and Nanotechnologies (https://2023.micro-nano.gr), our annual event that brings together Academia, Research and Industry to discuss the latest advancements of the field.

We are happy to announce that the abstract submission is already open and would like to prompt you to submit your work by September 18th. Also, take advantage of the early bird registration discounts, which are open until October the 9th

Visit https://2023.micro-nano.gr/call-for-paper/ to submit your abstract 

and https://2023.micro-nano.gr/fees-registration/ for registration details.

We would like to remind you that this year’s conference includes a Celebratory Special Event for the conference’s 10th Anniversary, scheduled as an Opening Ceremony on the first day (November 2nd, 2023) to commemorate and celebrate 40 years of Microelectronics in Greece. We are also excited about this year’s 

plenary speakers: https://2023.micro-nano.gr/plenary-speakers/

and invited https://2023.micro-nano.gr/invited-speakers/

Check our website for more information on the stimulating presentations that lie ahead.

Dates to remember:

• Abstract submission deadline: September 18th, 2023
• Early-bird registration: October 9th, 2023
• Late poster presentation: October 23rd, 2023

Venue:

• Special Event: Main Hall of the National and Kapodistrian University of Athens (Panepistimiou 30)
• Special Event (Nov.2): “40 years of Microelectronics in Greece”
  https://2023.micro-nano.gr/special-event/

Technical Program: 

• Demokritos Congress Center, NCSR “Demokritos”
  https://2023.micro-nano.gr/final-program/

We are looking forward to seeing you all in November!

On behalf of the Organizing Committee,

Prof. Margarita Chatzichristidi, Conference Chair

Dr. Eleni Makarona, Conference Co-chair

Conference e-mail address: MicroNano2023@chem.uoa.gr

 

[paper] VNWFET-based technology

VNWFET-based technology: from device modelling to standard cell library

Sara Mannaa, Cedric Marchand, Damien Deleruyelle, Bastien Deveautour, 

Ian O’Connor, Alberto Bosio

2023 IEEE 23rd International Conference on Nanotechnology (NANO),

Jeju City, S.Korea, 2023, pp. 576-581

DOI: 10.1109/NANO58406.2023.10231288

Univ Lyon, ECL, INSA Lyon, CNRS, UCBL, CPE Lyon, INL, UMR5270, 69130 Ecully, France

Abstract: Vertical Nanowire Field Effect Transistors (VNWFETs) are an emerging technology with significant potential to reduce footprint and consequently interconnect capacitance, thereby achieving improved energy-efficiency and being naturally compatible with advanced 3D integration approaches. However, while initial estimations have focused on projections and estimations, no work has so far used a detailed compact model to attempt accurate transistor-level simulations for standard cell library characterization, thus enabling logic synthesis. In this paper, we propose a design flow to make the link from an existing (laboratory-scale) VNWFET technology and the associated compact model, to standard static logic cell design and characterization, and ultimately logic synthesis. To the best of our knowledge, this is the first work to prove the possibility of such a realistic design flow tailored to VNWFET technologies.

Fig: Through actual VNWFET fabrication setting up a design-technology co-optimization (DTCO) approach, the FVLLMONTI vision is to develop regular 3D stacked hardware layers of NNs empowering the most efficient machine translation thanks to fine-grain hardware / software co-optimisation.

Acknowledgment: This work has been founded by FVLLMONTI European Union’s Horizon 2020 research and innovation programme under grant agreement No 101016776.

Call for Book Chapters

Nanoscale Electronic Device Applications of Carbon Nanotubes,

Graphene, Silicene and Molybdenum Disulfide

[C4P] EDTM Conference 2024, Bangalore

8th IEEE Electron Devices Technology and Manufacturing

EDTM Conference 2024

Theme: Strengthening Globalization in Semiconductors

Hilton Bangalore, India, March 3rd- 6th, 2024

https://ewh.ieee.org/conf/edtm/2024/

Call for Paper: We cordially invite you to submit ORIGINAL 3-page Camera-Ready papers to the 2024 IEEE Electron Devices Technology and Manufacturing (IEEE EDTM 2024) Conference for possible presentations. Original papers are sought on any topic within the scope of IEEE EDTM 2024. There are 14 R&D Tracks for IEEE EDTM 2024, among them:

TRACK 9. Modeling and Simulation (MS)

Advances in modeling/simulation of devices, packages and processes; Technology CAD and benchmarking; Atomistic process and device simulation; Compact models for DTCO and STCO; AI/ML-augmented modelling; Material and interconnect modeling; Models for photonic devices.

Important Dates for Authors

• Three-page camera-ready paper submission starts: August 1,2023
• Paper submission deadline: October 15, 2023 October 30, 2023 
• Notification for Acceptance: December 15, 2023

Accepted IEEE EDTM 2024 papers will be considered for competition for the Best Paper Award, Best Student Paper Awards and Best Poster Awards.

More details on paper submission can be found at the Paper Submission webpage.

[Proceedings] MNDCS 2023

Micro and Nanoelectronics Devices, Circuits and Systems

Select Proceedings of MNDCS 2023

Part of the book series: Lecture Notes in Electrical Engineering (LNEE, volume 1067) DOI: 10.1007/978-981-99-4495-8

Editors: Trupti Ranjan Lenka, Samar K. Saha, Lan Fu

This book presents select proceedings of the International Conference on Micro and Nanoelectronics Devices, Circuits and Systems (MNDCS-2023). The book includes cutting-edge research papers in the emerging fields of micro and nanoelectronics devices, circuits, and systems from experts working in these fields over the last decade. The book is a unique collection of chapters from different areas with a common theme and is immensely useful to academic researchers and practitioners in the industry who work in this field.