[mos-ak] MOS-AK/GSA San Francisco, CA Workshop on-line Publications

MOS-AK/GSA San Francisco, CA workshop on-line publications are
available, visit:
http://mos-ak.org/california/

More that 50 registered participants followed 11 technical compact
modeling talks at the MOS-AK/GSA Compact Modeling Workshop in San
Francisco, CA. I would like to thank all MOS-AK/GSA speakers for
sharing their compact modeling competence, R&D experience and
delivering valuable MOS-AK/GSA presentations. I am sure, that our
modeling event in San Francisco, CA was beneficial to all MOS-AK
Workshop attendees.

Organization of our modeling event would not be possible without our
generous sponsors: Accelicon Technologies and Cascade Microtech as
well as the IEEE EDS, technical co-sponsorship. I also would also like
to personally acknowledge local workshop organizers, in particular,
Tim K. Smith for his dedication and personal assistance to provide
smooth workshop logistics.

I hope, we would have a next chance to meet us with your academic and
industrial partners at future MOS-AK/GSA modeling events (check the
list below).

- with regards - WG (for the MOS-AK/GSA Committee)
––––––––––––––––––––––––––––––––––----------------
MOS-AK/California on-line publications <http://mos-ak.org/california/
>
MOS-AK/Seville on-line publications <http://mos-ak.org/seville>
IWCM at ASP-DAC in Yokohama Jan.2011 (with MOS-AK Support)
MOS-AK/Paris at UPMC/LIP6 <http://www.mos-ak.org/paris/>
MIXDES in Gliwice June 16-18, 2011 (with MOS-AK Session)
MOS-AK/Helsinki Sept.16, 2011 (ESSDERC time frame)
––––––––––––––––––––––––––––––––––----------------

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Electronics industry braces for rare-earth-materials shortages

From EDN:

Electronics industry braces for rare-earth-materials shortages:

"China has started to severely restrict the exports of rare-earth materials, which often find use in “green”-technology designs, including hybrid vehicles and energy-efficient lighting, as well as in the medical, defense, and consumer markets. The country delivers nearly 100% of the world’s rare-earth materials: 17 metals that are somewhat hard to refine and that tend to occur in the same ore deposits (Table 1). The cutbacks have resulted in shock waves through the electronics industry and could force design changes in the near future.

China set out on a moderate restriction path this year and then announced in July that it would cut exports by 72% for the remainder of 2010. It plans an overall export reduction of 30% for next year.

These cutbacks have increased the price of rare-earth materials an average of 700%, prompting legislation, which is currently stalled, to restart US rare-earth-materials production. The Western Hemisphere’s one rare-earth-materials producer, Colorado-based Molycorp Minerals, issued an initial public offering of stock in July, raising $390 million to restart its California mine and ramp up processing to counter world shortages.

Part of China’s motivation for reducing rare-earth-materials exports is its desire to emphasize its industrial status. China’s leaders want to move away from raw-materials exports and evolve toward exporting more finished goods.

Production of rare-earth materials fell off worldwide beginning in the 1980s when low prices in China made production unfeasible elsewhere in the world. Tom Valiere, senior vice president and co-founder of Design Chain Associates, says this cutback is a wake-up call for US industry. “We used to lead the world in the export of rare-earth materials,” he says. “In the last 20 years, we’ve become dependent. The whole thing flew under the radar until green technology placed demand on rare-earth materials and we realized they were sole-sourced to China.”

China’s restrictions this year have been part of a multiyear plan to save most of its supply for its own industry. “Each year, China has brought down its exports by X% and never exceeded its quotas,” says Gareth Hatch, co-founder of Technology Metals Research. “The reduction the country made in July was a huge reduction over the first half of the year.”

Worldwide shortages are now occurring. “The world outside China uses a collective 50,000 tons annually,” says Jim Simms, director of public affairs at Molycorp Minerals. “[China] reduced its exporting in 2010 to about 30,000 tons. Since China supplies about 97% of rare-earth materials, the world has to depend on what China exports.”

Simms believes that the demand for the materials will just increase over the coming years. The company expects to produce 20,000 tons by the end of 2012. “My BlackBerry only has about 3/10g of rare-earth materials,” he says, but “a single wind turbine requires about one ton. A car can use about 25 kg.”

Lynas Corp, a rare-earth-materials supply company in Australia, expects to increase rare earths delivery in 2011 to 11,000 tons per year.

Rare-earth materials facts

Rare-earth materials include terbium, which finds use in flat-panel TVs and high-efficiency fluorescent lamps, and neodymium, key to the permanent magnets in high-efficiency electric motors. Rare-earth materials are not indeed rare. The series of nonferrous metals is common in the environment. According to Design Chain Associates, most rare-earth materials are as common as copper, and even the rarest is more common than gold.

Part of the market pressure on rare-earth materials comes from new demand that green technologies has prompted. The market, including electric- and hybrid-vehicle motors and wind turbines, requires magnets.
,..."

WOCSDICE'2011

The abstract submission for the 35th edition of the European "Workshop on Compound Semiconductor Devices and Integrated Circuits" (WOCSDICE 2011) is open.
The conference will be held in Catania (Italy), from  May 29th to June 1st 2011.

Short abstracts, not exceeding 300 words, must be submitted via e-mail at the following address: abstract@wocsdice2011.org
Detailed guidelines for abstract preparation and submission can be found on the conference website (www.wocsdice2011.org) under the session "Abstract Submission". In the website you will find also other practical information concerning the registration and accommodation.

The dead line for short abstracts submission is February 25th, 2011.

Authors will be notified by March 21st, 2011 regarding the status of their paper by e-mail.
For the accepted contributions, an extended abstract, maximum 2 pages of length (4 pages for invited speakers), including figures, tables and references, will be required within April 11th, 2011.

8.3% Efficiency in a OPV

I copy from their webpage:

Konarka's Power Plastic Achieves World Record 8.3% Efficiency Certification from National Energy Renewable Laboratory (NREL)

Lowell, Mass. - Nov. 29, 2010 - Konarka Technologies, Inc., an innovator in development and commercialization of Konarka Power Plastic®, a material that converts light to energy, today announced that the National Energy Renewable Laboratory (NREL) has certified that Konarka’s organic based photovoltaic (OPV) solar cells have demonstrated a record breaking 8.3% efficiency. This is the highest performance recorded by NREL for an organic photovoltaic solar cell.
"The progress Konarka has achieved this year with regard to solar cell efficiency is unprecedented, representing a significant milestone for the industry," commented Howard Berke, chairman, CEO and co-founder of Konarka. "This unsurpassed NREL certification opens new doors for the commercial production of cost-effective, efficient electricity for numerous large scale applications."
Konarka Power Plastic is a patent-protected thin film solar material that converts light to energy. The unique material is lightweight and flexible, lending itself to a wide range of applications where traditional photovoltaics are not effective.
The latest certification results are for Konarka’s large area single-junction solar cell with a surface area of 1 square centimeter. This efficiency rating far exceeds previous single-junction organic photovoltaic cell measurement on that surface area and represents the world record for OPV efficiency.

24th International Conference on Microelectronic Test Structures (ICMTS)

The IEEE Electron Devices Society sponsors the 24th International Conference on Microelectronic Test Structures (ICMTS).

The conference will be held on April 5-7, 2011, in downtown Amsterdam (The Netherlands) at the Royal Academy of Arts and Sciences, and will be preceded by a one-day Tutorial Short Course on Microelectronic Test Structures on April 4. The program further includes a company exhibit and various social events in and around the Academy. 

Registration to the conference is now open. If you wish more info, please visit their website http://icmts2011.ewi.utwente.nl/ for further information.

[mos-ak] Final Program MOS-AK/GSA Workshop in San Francisco

Please visit the MOS-AK/GSA San Francisco web site with the final
workshop program:
http://www.mos-ak.org/california/

* Free On-line Registration Form:
http://www.mos-ak.org/california/registration.php

* Venue: The JW Marriott Union Square, San Francisco, CA
http://www.marriott.com/hotels/travel/sfojw-jw-marriott-san-francisco-union-square/

* Agenda
Dec. 8, 2010: MOS-AK/GSA Workshop co-located with the CMC Meeting and
IEDM Conference
9:00 - 12:00: Morning Session - Chair: Ian Getreu
13:00 - 16:00: Afernoon Session - Chair: Larry Nagel
http://www.mos-ak.org/california/

MOS-AK/GSA Happy Hour at Noma Gallery
after 18:00 - Discussion, networking and...
80 Maiden Ln. 3rd fl, San Francisco, CA
http://www.nomagallerysf.com/artists/NOMA_GALLERY/index.html

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Senior Research Engineer - MEMS circuits

Responsibilities:

Electro-mechanical computing has recently emerged as a very promising solution for ultra-low-power and high temperature circuit applications. The candidate will be responsible of the development of nano-electromechanical components for computation applications (logic and memory devices). This research will include device physics and modeling, design, fabrication in the IME cleanroom and characterization of electro-mechanical devices and circuits. Reliability and failure testing of memory arrays will be conducted.

Requirements:

PhD degree in Mechanical Engineering, Electrical Engineering or Material Sciences. Hands-on experience on wafer level MEMS related works, including microfabrication process and work in a cleanroom environment. Familiar with electrical measurement techniques (device and memory arrays). Strong interest for MEMS multi-physics modeling. Excellent communication skills and teamwork with strong self-motivation. Interaction with industrial/academic partners expected.

Please contact Dr Vincent Pott for more information.

Position to remain open until a candidate is selected (apply online).

First comprehensive and systematic course on statistical variability

I am delighted to bring to your attention the first comprehensive and systematic course on statistical variability.

Dates: 11-12 January 2011 in Grenoble.

This first edition of the course is in collaboration with the SINANO Institute and the FP7 NoE NANOSIL. 

The course covers:

· Variability classification
· Sources of statistical variability
· Simulation of statistical variability
· Variability trends in conventional and novel MOSFETs
· Random telegraph noise statistics
· Statistical aspects of reliability
· Statistical compact model strategies
· Statistical circuit simulation

You can find the syllabus at:
http://www.goldstandardsimulations.com/courses/syllabus/ 

You will be able to register for the course soon at:

http://www.goldstandardsimulations.com/courses/.

[mos-ak] C4P MOS-AK/GSA Workshop in San Francisco on December 8th, 2010

C4P MOS-AK/GSA Workshop in San Francisco on December 8th, 2010
http://www.mos-ak.org/california/

We, together with the lead sponsors Accelicon Technologies and Cascade
Microtech, are delighted to declare that we have confirmed a first-
class location for the MOS-AK/GSA Workshop in San Francisco on
December 8th, 2010: the JW Marriott Union Square <http://
www.marriott.com/hotels/travel/sfojw-jw-marriott-san-francisco-union-square/>.
Attendees will need to secure their own lodging and transportation to
the event. The JW Marriott is centrally located near Union Square,
near IEDM, and public transportation is abundant.

The MOS-AK/GSA Workshop in San Francisco will be organized as in the
timeframe of the IEDM and CMC Meetings. The MOS-AK/GSA Workshop is
HiTech forum to discuss the frontiers of the electron devices modeling
with emphasis on simulation-aware models. Original papers presenting
new developments and advances in the compact/spice modeling and its
Verilog-A standardization are solicited. Suggested topics include (but
are not limited to):
* Compact Modeling (CM) of the electron devices
* Verilog-A language for CM standardization
* New CM techniques and extraction software
* CM of passive, active, sensors and actuators
* Emerging Devices, CMOS and SOI-based memory cells
* Microwave, RF device modeling, high voltage device modeling
* Nanoscale CMOS devices and circuits
* Technology R&D, DFY, DFT and IC Designs
* Foundry/Fabless Interface Strategies

On-line abstract submission will be open on Nov.5, 2010.

Further details and updates http://www.mos-ak.org/california/

Local Organizing Committee:
Junko Nakaya, Cascade Microtech
Tim K.Smith, Accelicon Technologies

Extended MOS-AK/GSA Committee:
Jodi Shelton, President, Global Semiconductor Alliance (GSA)
Chelsea Boone GSA; Senior Research Analyst
Wladek Grabinski, GMC Suisse; MOS-AK/GSA Group Manager
MOS-AK/GSA North America:
Chair: Pekka Ojala, Exar Corporation
Co-Chair: Geoffrey Coram, Analog Devices
Co-Chair: Prof. Jamal Deen, U.McMaster
Co-Chair: Roberto Tinti, Agilent EEsof Division
MOS-AK/GSA South America:
Chair: Prof. Gilson I Wirth; UFRGS; Brazil
Co-Chair: Prof. Carlos Galup-Montor, UFSC; Brazil
Co-Chair: Sergio Bampi, UFRGS, Brazil
Co-Chair: Prof. Antonio Cerdeira Altuzarra, Cinvestav - IPN, Mexico
MOS-AK/GSA Europe:
Chair: Ehrenfried Seebacher, austriamicrosystems AG
Co-Chair: Alexander Petr, XFab
Co-Chair: Prof. Benjamin Iniguez, URV
Co-Chair: James Victory, Sentinel-IC
MOS-AK/GSA Asia/Pacific:
Chair: Goichi Yokomizo, STARC, Japan
Co-Chair: Sadayuki Yoshitomi, Toshiba, Japan
Co-Chair: Prof. Xing Zhou, NTU, Singapore
Co-Chair: Prof. A.B. Bhattacharyya, JIIT

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PRIME 2011 Conference

4-8 July 2011, Madonna di Campiglio (TN), Italy

The main objectives of PRIME 2011 Conference are:

• to encourage favorable exposure to Ph.D. students in the early stages of their careers
• to benchmark Ph.D. research in a friendly and cooperative environment
• to enable sharing of student and supervisor experiences of scientific and engineering research
• to connect Ph.D. students and their supervisors with companies and research centers

Paper Submission

The PRIME 2011 conference will allow only electronic submission of papers in PDF format (maximum file size must not exceed 2 Mbytes). Papers must not exceed four A4 pages with all illustrations and references included. The quality of the conference will be guaranteed by a thoroughly selected Technical Program Committee, which will provide detailed feedback to the authors. The accepted papers in the final camera ready format will be available on IEEE Xplore database. Papers submission will be opened during the first week of January, 2011. Manuscript guidelines as well as instructions on how to submit electronically your paper will be available soon on the conference web page.

E-mail: prime2011@fbk.eu
Website: http://prime2011.fbk.eu/

14 inch Transparent OLED Display Notebook from Samsung mobile

I couldn't resist the temptation to share this...

TriQuint rolls new GaAs foundry process

RF chip maker TriQuint Semiconductor Inc. has released its latest 150-mm gallium arsenide (GaAs) commercial foundry process. The process, dubbed TQP15, is targeted at the Ka-band segment. It is designed for building millimeter wave (mmWave) MMICs for applications such as VSAT, satellite communications and point to point radios [read more...]

New papers (October 27, 2010)

• Why Quasi-Monte Carlo is Better Than Monte Carlo or Latin Hypercube Sampling for Statistical Circuit Analysis (abstract)
• Separate Extraction of Source, Drain, and Substrate Resistances in MOSFETs With Parasitic Junction Current Method (abstract)
• A Physics-Based Compact Model for Polysilicon Resistors (abstract)
• The Equivalent-Thickness Concept for Doped Symmetric DG MOSFETs (abstract)
• An Analytical I–V Model for Surrounding-Gate Transistors That Includes Quantum and Velocity Overshoot Effects (abstract)
• Failure of the Scalar Dielectric Function Approach for the Screening Modeling in Double-Gate SOI MOSFETs and in FinFETs (abstract)
• Device Physics and Characteristics of Graphene Nanoribbon Tunneling FETs (abstract)
• Analytical Threshold Voltage Model Including Effective Conducting Path Effect (ECPE) for Surrounding-Gate MOSFETs (SGMOSFETs) With Localized Charges (abstract)
  

And other papers that I've found interesting:

• Dual Threshold Voltage Organic Thin-Film Transistor Technology (abstract)
• Complementary Organic Circuits Using Evaporated $ hbox{F}_{16}hbox{CuPc}$ and Inkjet Printing of PQT (abstract)
• Low-Voltage High-Performance Pentacene Thin-Film Transistors With Ultrathin PVP/High- $kappa$ HfLaO Hybrid Gate Dielectric (abstract)
• High-Performance Pentacene Thin-Film Transistors Fabricated by Organic Vapor-Jet Printing (abstract)
• Magnetic-Field Area Sensor Using Poly-Si Micro Hall Devices (abstract)
• On-Chip Aging Sensor Circuits for Reliable Nanometer MOSFET Digital Circuits (abstract)
• On Undetectable Faults and Fault Diagnosis (abstract)
  

Job offers in LinkedIn: RF Modeling Device Engineer

Remember, this is only for information. We're not connected to them!

HIRING - Peregrine Semiconductor - RF Modeling Device Engineer

Click Here to Apply: https://home.eease.adp.com/recruit/?id=531727

Job Description:
This position is responsible for:
Member of team responsible for device modeling of Peregrine’s patented high-performance UltraCMOSTM silicon-on-sapphire CMOS process and packaging technology. The candidate will work closely with modeling engineers and CAD to support our design groups and external foundry customers.

Roles & Responsibilities will include:
• Responsible for modeling of passive components.
• Responsible for parasitic analysis of RF active components and BEOL.
• Model extraction for components on-wafer, modules, and packages.
• Manufacturing data analysis to develop statistical and corner models.
• Test chip DOE development, layout, and measurement.
• Provide guidance to design teams on best practice.


Qualifications:

Minimum Requirements:
• Ph.D. in Physics or Electrical Engineering (MS okay with demonstrated experience)
• Understanding of RF device performance metrics
• Experience using SPICE like circuit simulators to develop sub-circuit models.
• Experience using EM simulators (HFSS, Momentum, etc.) to study device performance.
• Demonstrated ability to extract models from measured data.
• Demonstrated problem solving skills.

The following traits are highly valued:
• Strong programming background and ability to develop automation scripts.
• Experience with Matlab, ICCAP, or other tool for model extraction.
• Layout optimization for RF applications.
• Experience configuring and automating test equipment.
• Large signal RF device characterization.

[mos-ak] MOS-AK/GSA Seville Workshop Press Release

Press release:
"MOS-AK/GSA Modeling Working Group Holds Workshop in Seville"
can be found on the GSA site at
http://www.gsaglobal.org/news/article.asp?article=2010/1014

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Modelling people wanted...

I copy from LinkedIn:

Looking for PhD/ MS candidates in device physics , modelling back ground for one of the Semiconductor research and development centre at Bangalore .


see more...

Accurately simulate an LED

Accurately simulate an LED: " View as PDF Read More Design IdeasSolid-state-lighting applicatio..."

SEMI urges less bureaucratic approach to EU research funding

SEMI urges less bureaucratic approach to EU research funding: "San Jose-based manufacturing organization SEMI is advocating for a simplifica..."

The Nobel Prize in Physics 2010 (graphene)

The Royal Swedish Academy of Sciences has decided to award the Nobel Prize in Physics for 2010 to Andre Geim and Konstantin Novoselov, both at University of Manchester, UK “for groundbreaking experiments regarding the two-dimensional material graphene”.


Andre Geim, Dutch citizen. Born 1958 in Sochi, Russia. Ph.D. 1987 from Institute of Solid State Physics, Russian Academy of Sciences, Chernogolovka, Russia. Director of Manchester Centre for Meso-science & Nanotechnology, Langworthy Professor of Physics and Royal Society 2010 Anniversary Research Professor, University of Manchester, UK. 
Konstantin Novoselov, Brittish and Russian citizen. Born 1974 in Nizhny Tagil, Russia. Ph.D. 2004 from Radboud University Nijmegen, The Netherlands. Professor and Royal Society Research Fellow, University of Manchester, UK.

Read the press release...

AWR Announces New PDK for Cree GaN HEMT MMIC Foundry

The Cree GaN HEMT MMIC process features high power density (4-6 watts/mm) transistors, slot vias, and high reliability (up to 225ºC operating channel temperatures), as well as scalable transistors. [more]

[mos-ak] MOS-AK/GSA Seville Workshop on-line Publications

MOS-AK/GSA Seville workshop on-line publications are available:
http://www.mos-ak.org/seville/

More that 50 registered participants followed 2 keynote invited
presentations, 7 technical compact modeling talks as well as 15 poster
presentation at the MOS-AK/GSA ESSEDERC/ESSCIRC Compact Modeling
Workshop. I would like to thank all MOS-AK/GSA speakers and poster
presenters for sharing their compact modeling competence, R&D
experience and delivering valuable MOS-AK/GSA presentations. I am
sure, that our modeling event in Seville was beneficial to all MOS-AK
Workshop attendees.

Please note that as a result of post workshop discussion, the Dolphin
Verilog-A Compact Model Coding Whitepaper is available for direct
download:
http://www.dolphin-integration.com/medal/smash/notes/Verilog_A_Compact_Model_Coding_Whitepaper.pdf

Organization of our modeling event would not be possible without our
generous sponsors: Cascade Microtech and X-FAB Semiconductor Foundries
as well as the IEEE EDS, technical co-sponsor. I also would like to
personally acknowledge local ESSDERC/ESSCIRC organizers, in
particular, Professors Manuel Delgado Restituto, Andrés Godoy, the
ESSDERC/ESSCIRC Tutorials & Workshops Chairs for their dedication,
commitment. My very special 'thank you' goes also to Susana Eiroa for
her assistance and providing smooth workshop logistics.

I hope, we would have a next chance to meet us with your academic and
industrial partners at future MOS-AK/GSA modeling events (check the
list below).

- with regards - WG (for the MOS-AK/GSA Committee)
––––––––––––––––––––––––––––––––––
MOS-AK/Seville on-line publications <http://mos-ak.org/seville>
MOS-AK/California (Dec.2010; IEDM time frame)
IWCM at ASP-DAC in Yokohama Jan.2011 (with MOS-AK Support)
MOS-AK/Paris at LIP6 (March/April 2011)
MIXDES in Gliwice June 16-18, 2011 (with MOS-AK Session)
MOS-AK/Helsinki Sept.16, 2011 (ESSDERC time frame)
––––––––––––––––––––––––––––––––––

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CEA-Leti Makes a R&D 20nm Fully Depleted SOI Process available through CMP

Grenoble, FRANCE, and Tokyo, JAPAN, October 1st , 2010, CEA-Leti and CMP (Circuits Multi Projets®) announced during the FDSOI Workshop at Tokyo University the launch of an Exploratory MPW (Multi Project Wafers) initiative based on FDSOI (Fully Depleted SOI) 20nm process, opening the access of its 300mm infrastructure to the design community. This MPW offer is partly supported by EUROSOI+ network that gathers the main European academic partners on SOI.

The basis of the Fully Depleted SOI 20nm technology offer will be the following:

• CMOS transistors with an undoped channel and a silicon film thickness of 6nm
• High-k / Metal Gate stack
• Single threshold voltage (Vth) n- and p-MOSFET with balanced Vth of ±0.4V
• Associated Design Kit, including SPICE model (Verilog-A language), model cards extracted from silicon data, p-cells, DRC, LVS, schematic, parasitics
• Design Kit documentation

CMP Press Contacts:

Bernard Courtois +33 4 76 57 46 15

Kholdoun Torki +33 4 76 57 47 63

Shipments of silicon for semiconductor manufacturing raise more than 23%

I copy part of a post from EDN:

Shipments of silicon for semiconductor manufacturing in 2010 will grow by 23.6% year-over-year, reaching 8.9 billion total square inches, according to iSuppli estimates.

Global silicon shipments in terms of square inches are bouncing back in 2010, after suffering like most segments did in the 2008/2009 economy.

That's according to a report from iSuppli Corp, which estimated shipments will rise to record levels in 2010.

Shipments of silicon for semiconductor manufacturing in 2010 will grow by 23.6% year-over-year, reaching 8.9 billion total square inches, up from 7.2 billion square inches in 2009, iSuppli forecast. Growth is expected to continue and iSuppli projected that by 2014 12.4 billion total square inches of silicon will be shipped.

read more here....

Ten Years of Scaling

[source http://dger.at/2XTq]

Nano antenna concentrates light

Condensed matter physicist Doug Natelson and graduate student Dan Ward have found a way to make an optical antenna from two gold tips separated by a nanoscale gap that gathers light from a laser. The tips "grab the light and concentrate it down into a tiny space," Natelson said, leading to a thousand-fold increase in light intensity in the gap. [more]

What's the "AMS" in VHDL-AMS?

from Mentor.com :: Blog Posts by Mike Jensen

read also related post "What's in a SPICE Model?"

The pocket beamer is a reality!

Maher Kayal, professor at EPFL's Institute of Electrical Engineering presents the beamer of the future: 1 cm3 of technology that can be integrated into a portable computer or mobile telephone. Nicolas Abélé, technical director of Lemoptix, explains the future developments of this new device.

TSMC, Taiwan universities partner to cultivate semiconductor talent

TSMC, Taiwan universities partner to cultivate semiconductor talent: "TaiwanSemiconductor Manufacturing Co (TSMC), Taiwan's National Cheng ..."

Arana Behavioral Modeling Platform (as of Sept. 2010)

I copy part of the press release (by the way, the link in their home page doesn't work...):

Arana platform automates the process of behavioral model creation, generation, optimization, and validation for analog, custom digital, memory and mixed-signal integrated circuits. It features Arana Top-Down Designer, Arana Bottom-Up Designer, Arana Model Optimizer, and Arana Model Validator.

Arana Top-Down Designer supports behavioral model creation from specification or from templates, as well as automated calibration of model parameters against the transistor response and/or measurement data. Arana Bottom-Up Designer allows a circuit designer to automatically generate silicon-faithful parametric behavioral models—accounting for process, voltage, temperature, and loading variations—for functional verification.

Both Arana Bottom-Up Designer and Top-Down Designer support hierarchical modeling and automated generation of formal analog assertions and model test benches. Arana Model Optimizer and Model Validator optimize and validate behavioral models against transistor level responses and characterization and/or measurement data.

 read more...

Paper in IEE Electronics Letters (September 2010)

Analytical modelling of gate tunnelling current of MOSFETs based on quantum tunnelling

5567057abstract

Kazerouni, I.A.;   Hosseini, S.E.;   Parashkoh, M.K.;  
Engineering Department, Tarbiat Moallem University of Sabzevar, Sabzevar, Iran 
This paper appears in: Electronics Letters
Issue Date: September 2010
Volume: 46 Issue:18
On page(s): 1277 - 1279
ISSN: 0013-5194
Digital Object Identifier: 10.1049/el.2010.1339 
Date of Current Version: 09 September 2010
Sponsored by: Institution of Engineering and Technology 

Abstract

The gate tunnelling current of MOSFETs is an important factor in modelling ultra-small devices. In this reported work, the gate tunnelling current in present-generation MOSFETs is studied. Presented is a model for the gate tunnelling current in MOSFETs having ultra-thin gate oxides. In the proposed model, the electron wavefunction at the semiconductor-oxide interface is calculated and inversion charge by assuming the inversion layer as a potential well, including some simplifying assumptions. Then the gate tunnelling current is calculated using the calculated wavefunction. The proposed model results have excellent agreement with experimental results in the literature.

IEEE SCV EDS: LDMOS reminder & upcoming

Sept. 14th
LDMOS - Technology and Applications
Shekar Mallikarjunaswamy, Alpha Omega Semiconductor

Sept. 28th
The Makers of the Microchip: Creating the Planar Integrated Circuit, Establishing Silicon Valley
David Brock, Cristophe Lecuyer

Oct. 12th
Is it the End of the Road for Silicon in Power Management?
Dr. Alex Lidow, CEO Efficient Power Conversion Corporation

Details on IEEE SCV EDS website: http://www.ewh.ieee.org/r6/scv/eds

OLED simulation software

I'm copying here the press release (it must be takes as such, cum grano salis)

sim4tec announces the release of new version 3.0 of its OLED simulation software SimOLED.
New features include:

• Enhanced powerful graphical representation of results - line and contour plots
• Electronic, excitonic and optic module seamlessly combined
• Faster calculation speed
• Additional results for current, power, quantum efficiencies, CIE diagram and many more
• Updated graphical user interface

A special highlight is the combination of our well-proven and reliable electronic module with the excitonic and optic modules. This allows users to simulate voltage-dependent optical quantities like the colour maintenance of white OLEDs.
The software is ideally suited for conducting basic research, arbitrary OLED stack design, material parameter extraction and process window identification. Included in the software is an in-depth tutorial containing more than 20 examples, ranging from simple single layer devices up to white hybrid OLEDs.

IDESA Training Courses Calendar

Implementation of widespread IC DEsign Skills in advanced deep submicron technologies at European Academia.

Advanced Analog Implementation flow	Analog circuit design simulation and layout for 90nm and below.
Advanced Digital Physical Implementation flow	Power Aware physical design techniques, timing and power closure.
Advanced RF Implementation flow	RF Implementation Flow in deep sub-micron CMOS technology.
Design for Manufacturing flow	DFM issues are becoming increasingly important for 90nm and below.

The IDESA Course Booking System is managed and maintained by STFC Rutherford Appleton Laboratory, UK. If you have a booking enquiry, please email: idesa@stfc.ac.uk

	Jan	Feb	Mar	Apr	May	Jun	Jul	Aug	Sep	Oct	Nov	Dec
IDESA Course Calendar 2010
Advanced Analog Implementation flow									RAL
Advanced Digital Physical Implementation flow									AGH			LUND
Advanced RF Implementation flow											IMEC	PPAZ
Design for Manufacturing flow											ERLN
IDESA Course Calendar 2011
Advanced Digital Physical Implementation flow		ERLN
Design for Manufacturing flow		TUL				MONS

Course Location key:
AGH	AGH University of Science and Technology, Poland	CIME	CIME, France
ERLN	Fraunhofer IIS, Erlangen, Germany	IMEC	Interuniversitair Micro-Electronica Centrum, Belgium
LUND	University of Lund, Sweden	MONS	Université de Mons, Belgium
MONT	University Montpellier 2, France	NAP	Università degli Studi di Napoli Federico II
PPAZ	Péter Pázmány Catholic University, Hungary	RAL	Rutherford Appleton Laboratory, UK
STU	Slovak University of Technology in Bratislava, Slovakia	TUL	Technical University of Lodz, Poland

Where to study nanotech?

Marie Curie Fellows - Centro de Química da Madeira, Funchal, Madeira Island, Portugal.

Job Reference: CQM-WIIP-2010

Where to study nanotech in India?

Nanotechnology in USA

Visit also Nanotechnology - TINC

Accelicon announces Context Dependent Modeling Platform

I copy a part of the original post:

Accelicon Technologies, Inc. announces the market’s first commercially available Context Dependent Modeling Platform based on Accelicon’s flagship device modeling solution MBP. The performance of FETs can vary significantly, at advanced process nodes, due to layout dependent proximity effects. Sources of LDEs include Well Proximity Effect (WPE), lithography distortions, un-intentional stress sources such as Shallow Trench Isolation (LOD Effect) and intentional stressors which are used to enhance the performance of the device. These enhancement techniques include dual-stress liners, embedded SiGe and stress memorization techniques. At advanced process nodes engineers must analyze LDEs to minimize undesirable proximity effects and lithography distortions, and effectively utilize stress enhancement techniques. This analysis can only be conducted after layout extraction, SPICE modeling alone is not sufficient. 

Read more at the original post in LinkedIn:

Accelicon announces Context Dependent Modeling Platform

Simulating the Memristor with spice (as of September 2010)

Here you have a list of papers where people model a memristor:


- H.H. Li and M. Hu, "Compact Model of Memristors and Its Application in Computing Systems," DATE, 2010.

- Á. Rak and G. Cserey, "Macromodeling of the Memristor in SPICE," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, 2010, pp. 632-636.

- D. Batas and H. Fiedler, "A Memristor Spice Implementation and a New Approach for Magnetic Flux Controlled Memristor Modeling," IEEE Transactions on Nanotechnology, 2010, pp. 1-1.

- "Modeling the HP memristor with SPICE," http://www.neurdon.com/2010/07/23/modeling-the-hp-memristor-with-spice/, 2010.

- Valsa, J., Biolek, D. and Biolek, Z. , "An analogue model of the memristor". International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, n/a. doi: 10.1002/jnm.786

Lot of work, isn't it?

www.SoCconference.com

8th International System-on-Chip (SoC) Conference, Exhibit & Workshops

Date: Nov. 3-4, 2010
Venue: Hilton Irvine/Orange County Airport
Agenda & Schedule

Early Bird Registration Is Now Open!

Three distinguished keynote speakers:

1. Dr. Ivo Bolsens, Senior Vice President and CCEO, Xilinx Inc.

2. Dr. J. Antonio Carballo, WW Manager, IBM Microelectronics Services, Semiconductor Partner, IBM VC Group, IBM.

3. Raouf Y. Halim, CEO, Mindspeed Technologies, Inc.

New record set for ferroelectric data storage

Scanning Nonlinear Dielectric Microscope: inset left: Shows topography and electric dipole-moment; inset right: Example of a ferroelectric information storage; [Read more...]

HP and Hynix - Bringing the memristor to market in next-generation memory

Today, HP announced a joint development agreement with Hynix Semiconductor Inc., to develop a new kind of computer memory – one that will employ memristor technology pioneered by researchers at HP Labs.

LDMOS - Technology and Applications

Speaker: Shekar Mallikarjunaswamy, Alpha Omega Semiconductor
Date: Sept 14th, 2010
Location: National Semiconductor, Building E1, Conference Center, 2900 Semiconductor Drive, Santa Clara , CA 95051 .

Abstract: A key device that is used in most high voltage (20 to 120V) power integrated circuits for power management applications is the Lateral Diffused MOS (LDMOS) transistor. Recent interest in ‘green” products have further increased the demand for integrated HV LDMOS devices in CMOS and BCD technologies to build higher efficiency dc-dc converters for consumer and LED markets. This presentation will journey through the structural innovations from “planar” to “trench” and to state-of-the-art “RESURF” LDMOS devices in both junction and dielectric isolation technologies for the past two decades. The physics of operation, figure of merits used for device comparison, layout techniques including integration of LDMOS into modern CMOS/BCD technologies will be discussed. Device and process simulations to optimize device parameters including SPICE macro circuits to model “quasi-saturation” and “Cgd” capacitance will be described. Methods to improve hot carrier reliability and ESD robustness of LDMOS devices will be highlighted. Finally, LDMOS circuit topologies and their applications in consumer, computer and telecommunication products will be presented to let the audience comprehend and appreciate the significance of LDMOS devices to modern power management products.

Web link: http://www.ewh.ieee.org/r6/scv/eds/

Modeling Memristor with SPICE

In 1971, Professor Chua proposed [1] that by necessity of symmetry reasons, besides the resistor, the capacitor, and the inductor; a fourth circuit element has to exist. In 2008, members of an HP Lab published [2] that they successfully realized a nano-scale electronic component. Spice macromodel [3-6] could be a powerful tool for electrical engineers to design and experiment new circuits with memristors.

REFERENCES
[1] L. Chua, “Memristor: The missing circuit element,” IEEE Trans. Circuit Theory, vol. 18, no. 5, pp. 507–519, Sep. 1971.
[2] D. B. Strukov, G. S. Snider, D. R. Stewart, and S. R. Williams, “The missing memristor found,” Nature, vol. 453, no. 7191, pp. 80–83, May 2008.
[3] H.H. Li and M. Hu, "Compact Model of Memristors and Its Application in Computing Systems," DATE, 2010.
[4] Á. Rak and G. Cserey, "Macromodeling of the Memristor in SPICE," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, 2010, pp. 632-636.
[5] D. Batas and H. Fiedler, "A Memristor Spice Implementation and a New Approach for Magnetic Flux Controlled Memristor Modeling," IEEE Transactions on Nanotechnology, 2010, pp. 1-1.
[6] "Modeling the HP memristor with SPICE," http://www.neurdon.com/2010/07/23/modeling-the-hp-memristor-with-spice/, 2010.

How To Make a P-N-P-N Semiconductor Device

50 years ago this year, in its 'Patent Pointers' section, the Electronics Weekly edition of September 14th 1980 carried the following snippet.

'An ingenious way of making a P-N-P-N or an N-P-N-P semiconductor device which avoids the difficulty of the heat treatment of the second junction adversely affecting the first formed junction is described in Patent No. 844970, filed by British Thomson-Houston Co.'

The note continues:
'What is done is to form a first P-N junction by alloying semiconductor germanium of N type with semiconductor silicon of P type, the second junction being subsequently made by fusing indium to the germanium.'

The note ends:
'The second junction is made at a lower temperature than the first so that the first junction is unharmed.'

Posted by David Manners on August 17, 2010; TrackBack URL for this entry:
http://www.electronicsweekly.com/cgi-bin/mt/mt-tb.cgi/162252

DATE 2011 - Final Call for Papers

DATE 2011 - Conference and Exhibition
March 14-18, 2011; Grenoble, France

Submission Deadlines:

• Sept. 5, 2010: Papers, Special Sessions, Tutorials, Workshops
• Oct. 10, 2010: Exhibition Theatre
• Nov. 12, 2010: PhD Forum
• Jan. 14, 2011: University Booth

More Information:
Download/View the CfP as PDF
Complete DATE 2011 information is available

Postdoctoral Marie Curie Fellowship on Compact Modeling

The European (7th Framework Programme) Call for Postdoctoral Individual Marie Curie Fellowships is open until August 17 2010.

I am looking for one or two candidates to work in my research group at the Universitat Rovira i Virgili (Tarragona, Spain) in the field of compact modeling of advanced semiconductor devices. Therefore, I would like to receive CVs from potential applicants. Once I have selected the candidates, we will make the application.The candidates must have a Ph D in Electrical Engineering, Electronic Engineering, Physics or Telecommunication Engineering.

There are two open Calls: the one forIntra-European Fellowships and the one for International Incoming Fellowships. Therefore, candidates from European countries can apply for an Intra European Fellowship and candidates from outside Europe can apply for an International Incoming Fellowship.These felowships can be for one or two years. Salaries are extremely good and the prestige of having this type of fellowship is very high. For this reason, there is a tough competition to get these fellowships.I am looking for candidates for these Marie Curie Grants, both from Europe and outside Europe. Candidates must have a good CV (preferably with more than 4 publications in international journals, in order to have chances).

In order to fit the Marie Curie requirements, their age should be below 35.

If successful, the postdoctoral researchers will work on the characterization of compact modeling of any of the advanced semiconductor devices targeted by our research European projects: nanoscale MOSFETs, SOI and Multi-Gate MOSFETs, strained-Si/SiGe MOSFETs, Schottky-Barrier MOSFETs, nanowire FETs, III-V HEMTs and organic TFTs.The specific device/s in which the postdoctoral researcher will work will depend on his/her preference and background.

Candidates must send me by e-mail (to benjamin.iniguez@gmail.com) a CV or resume by AUGUST 14. Successful applicants will be informed by August 15, and then we will start to make the application. The successful candidates will be informed on the steps to do.

Tarragona is a small city (110000 inhabitants) on the Mediterranean coast, about 100 Km south from Barcelona, and very well connected to Barcelona and the main Spanish cities by rail and highway. Tarragona is a very old city, very important during the Roman Empire, and with a lot of historical landmarks.The quality of life in Tarragona is excellent. Mediterranean and mild climate the whole year. Wonderful beaches around the city (even at the city). Mountains close to the city (even the Pyrenees are not far). Besides, the city is very quiet, but with an intense nightlife.

My research group in the Department of Electronic Engineering, Universitat Rovira i Virgili (URV) is one of the strongest groups in compact modeling in Europe. We are leading one European project on compact modeling (in which a total of 15 European universities and companies participate). We also participate on two other European projects (one about nanoscale MOSFETs and another one about organic Thin Film Transistors). I am looking forward to receiving excellent applications!
Benjamin Iñiguez
Department of Electronic EngineeringTarragona,
SPAIN
Universitat Rovira i Virgili (URV)
E-mail: benjamin.iniguez@gmail.com

[mos-ak] Final Program MOS-AK/GSA Workshop in Seville

Please visit the MOS-AK/GSA/ESSDERC/ESSCIRC Seville web site with the
final workshop program:
http://www.mos-ak.org/seville and
http://www.mos-ak.org/seville/posters.php

* Venue and Recommended Hotels:
Sept.17, 2010 Barceló Renacimiento Hotel Seville
http://www.barcelorenacimiento.com/

* Free On-line Registration Form:
http://www.essderc2010.org/registration.html
or send an email directly to <seville@mos-ak.org>

Your might also note that, it will have a series of important compact
modeling (CM) events is Spain:

• Sept. 9-10: CMC Q3 Meeting with the COMON project presentation
• Sept. 13: ESSDERC CM tutorial
• Sept. 16: ESSDERC CM session with the regular conference papers
• Sept. 16: COMON CM Project Meeting
• Sept. 17: MOS-AK/GSA CM Workshop

--

For more options, visit www.mos-ak.org or its email group at:

http://groups.google.com/group/mos-ak?hl=en.

Open Ph D scholarship in semiconductor device modeling

We offer one scholarship for a Ph D student position in the Department of Electronic Engineering in the Universitat Rovira i Virgili (URV), in Tarragona, Spain.

The duration of the grant will be for four years. The monthly salary will be about 1000 Euro/month. The position will start in January 2011.

The candidate should have a Bachelor or Master degree in Electrical Engineering, Electronic Engineering, Telecommunication Engineering or Physics. A good background in Semiconductor Physics, Semiconductor Devices, or Integrated Circuit Design will be highly appreciated.

The work to be done by the candidate will be focused on the development of new techniques of characterization and modeling of novel advanced semiconductor devices, in particular nanoscale MOSFETs or III-V devices. It will be related to several European projects in which the hosting group participates, in particular the COmpact MOdelling Netwok (COMON), that is led by the hosting group (the so-called NEPHOS group)

The NEPHOS group at URV is one of the most powerful teams in Europe in the area of compact modeling of semiconductor devices.

Required documents for applicants


Applicants are required to send to the address specified below the following documents (in English or Spanish):

1) a full Curriculum Vitae (as complete as possible) with passport number

2) Copy of their diploma

3) copy of their passport

4) Academic certificate including their marks (it is important that the number of hours or credits of each subject appears). It is also very important that the document specifies what is the minimum mark for passing a given subject and what is the maximum mark that can be awarded.

Candidates are requested to send their documents by e-mail to:

Prof. Benjamin Iñiguez
Department of Electronic, Electrical and Automatic Control Engineering

Universitat Rovira i Virgili (URV)

Avinguda Països Catalans, 26
43007 Tarragona (Spain)
Email: benjamin.iniguez@gmail.com
Tel: +34977558521 Fax:+34977559610

Deadline: August 21 2011

You can contact Prof. Benjamin Iñiguez (Benjamin.Iniguez@gmail.com) for more information

Tarragona is a medium city (100000 inhabitants) with a Mediterranean climate and many recreation opportunities (nice beaches, theme parks, nature preserves, mountain hiking, touristic resorts and facilities). It is located 100 km Southwest of Barcelona, and it is very well connected by train, bus, highways and even low cost flights from its own airport. Additional information about the University and the department can be found at: www.urv.cat and sauron.etse.urv.es

IEEE SCV EDS: upcoming talks

Aug 10th
3-D ICs: Motivation, Performance Analysis, Technology and Applications
Dr. Krishna Saraswat, IEEE Fellow

Sept 14th
LDMOS - Technology and Applications
Shekar Mallikarjunaswamy, Alpha Omega Semiconductor

Oct 12th
Is it the End of the Road for Silicon in Power Management?
Dr. Alex Lidow, CEO Efficient Power Conversion Corporation

For details visit http://www.ewh.ieee.org/r6/scv/eds/

30 free programming eBooks [UPDATED]

Software engineering is an important element of the compact/spice modeling. Learning a new programming language always is fun and there are many great books legally available for free online. Here’s a selection of 30 of them:

Lisp/Scheme:
How to Desing Programs
Let Over Lambda
On Lisp
Practical Common Lisp
Programming in Emacs Lisp
Programming Languages. Application and Interpretation (suggested by Alex Ott)
Structure and Interpretation of Computer Programs
Teach Yourself Scheme in Fixnum Days
Visual LISP Developer’s Bible (suggested by skatterbrainz)

Ruby:
Data Structures and Algorithms with Object-Oriented Design Patterns in Ruby
Learn to Program
MacRuby: The Definitive Guide
Mr. Neighborly’s Humble Little Ruby Book (suggested by @tundal45)
Programming Ruby
Ruby Best Practices
Ruby on Rails Tutorial Book (suggested by @tundal45)

Javascript:
Building iPhone Apps with HTML, CSS, and JavaScript
Eloquent Javascript
jQuery Fundamentals

Haskell:
Learn You a Haskell for Great Good
Real World Haskell

Erlang:
Concurrent Programming in Erlang
Learn You Some Erlang for Great Good

Python:
Dive into Python
How to Think Like a Computer Scientist – Learning with Python

Smalltalk:
Dynamic Web Development with Seaside
Pharo by Example (based on the next book in this list, suggested by Anonymous)
Squeak by Example

Misc:
Algorithms
The Art of Assembly Language
Beginning Perl
Building Accessible Websites (suggested by Joe Clark)
The C Book
Compiler Construction
Dive Into HTML 5 (suggested by @til)
Learn Prolog Now!
Objective-C 2.0 Essentials
Programming Scala

Of course there are many more free programming eBooks, but this list consists of the ones I read or want(ed) to read. This is far from comprehensive and languages that are completely missing are mostly left out on purpose (e.g. PHP, C++, Java). I’m sure somebody else made a list for them somewhere.

[Source]