[Deadline] extended to Oct.15 2026

10th IEEE Electron Devices Technology and Manufacturing

(EDTM 2026) Conference

https://ieee-edtm.org/

March 1-4, 2026 Penang, Malaysia 

EDTM2026 paper submission date has been extended to 15th October 2025

Submit your papers today in any of the 13 tracks and see you in Penang, Malaysia from 1st - 4th March 2026.

• Contributed papers will be judged for the best paper award for each technical track
• Each track will have Invited Speakers. Meet prominent Plenary and Keynote Speakers from Industry and academia for research, networking, innovation and commercialization purposes
• Exhibition and sponsorship opportunities to showcase breakthrough technology
• Extended versions of accepted papers to be published in 
• EEE Transactions on Materials for Electron Devices (T-MAT) and 
• Journal of IEEE Electron Devices Society (JEDS)

[C4P] EDTM 2025 in Hong Kong, China

The 9th IEEE Electron Devices Technology and Manufacturing Hong Kong, China, March 9th – 12th, 2025 Theme: Shaping the Future with Innovations in Devices and Manufacturing Call for Papers Three-page camera-ready paper submission starts: August 15, 2024 Paper submission deadline: October 15 October 31, 2025 Notification for Acceptance: December 15, 2024 https://edtm2025.com/ Technical Areas EDTM 2025 solicits papers in all areas of electronic devices, including materials, processes, modeling, device/circuit/system design, reliability, packaging, manufacturing, testing, and yield. EDTM 2025 will include parallel technical sessions of oral and poster presentations. Publication Opportunities The accepted and presented papers will be published in the EDTM 2025 Proceedings, included in IEEE Xplore. The authors of a selected number of high-impact papers will be invited to submit extended versions for publication in the special issue of IEEE Journal of Electron Devices Society (J-EDS) or IEEE Transactions on Electron Devices, subjected to J-EDS and TED policy. Short Courses and Tutorials EDTM 2025 will start with a set of short courses and tutorials on March 9, 2025. Tutorials will cover selected topics from the basics to the state-of-the-art. The Short Courses will discuss the latest research and challenges on emerging and advanced topics. Exhibition EDTM 2025 offers vendors to showcase their newest products and technologies, allowing attendees to learn about new tools and techniques. Award Opportunities EDTM 2025 offers one Best Paper Award in each sub-technical area.

General Chair： Yang Chai (HK PolyU) General Co-Chair： Tim Cheng (HKUST) TPC Chair： Mansun Chan (HKUST) TPC Co-Chair： Yansong Yang (HKUST) Steering Committee: Shuji Ikeda (TEI Solutions) – Chair Bin Zhao (CTI) Arokia Nathan (Cambridge U.) Ravi Todi (Synopsys) Murty Polavarapu (BAE) Roger Booth (Qualcomm) Samar Saha (Prospicient Devices) Albert Wang (UC Riverside) Kazunari Ishimaru (Rapidus) Yogesh Chauhan (IIT Kanpur) Executive Committee: Yang Chai (HK PolyU) Roger Booth (Qualcomm) Mansun Chan (HKUST) Yansong Yang (HKUST) Ru Huang (Southeast) Qiming Shao (HKUST) Merlyne De Souza (U Sheffield) Pei-Wen Li (NCTU) Can Li (HKU) Masumi Saito (Kioxia) Zhongrui Wang (HKU) Meiki Ieong (Simbury) Carmen Fung (HKSTP) Man Hoi Wong (HKUST) Roger Booth (Qualcomm) Huaqiang Wu (Tsinghua) Rino Choi (Inha U.) Bernard Lim (Appscard) Shinichi Yoshida (SONY) Bill Nehrer (Atomera) Bich-Yen Nguyen (SOITEC) Benjamin Iniguez (URV) Edmundo Gutierrez (INAOE) Ming Yang (HK PolyU)

[IEEE SSCS] “PICO” Open-Source Chipathon

IEEE SSCS “PICO” Open-Source Chipathon

Automating Analog Layout

https://sscs.ieee.org/about/tc-ose/sscs-pico-design-contest

– Sign-Up Deadline: May 10, 2024 –

The IEEE Solid-State Circuits Society is pleased to announce its fourth open-source integrated circuit (IC) design contest under the umbrella of its PICO Program (Platform for IC Design Outreach). While this contest is open to anyone (no restrictions), we encourage the participation of pre-college students, undergraduates, and geographical regions that are underrepresented within the IC design community. 

The goal of this year’s event is to advance the automatic generation and open sharing of analog circuit layout cells to increase our community’s design productivity and to catch up with other fields where sharing and automation is a key enabler of progress (e.g., in machine learning).

Die photo in background courtesy of IBM

Contest Outline

1. Interested individuals sign up using this form by May 10, 2024.
2. Phase 1 (~June): Through a series of weekly meet-ups and training sessions, the participants learn to create basic one- or two-transistor layout generators using Python and open-source CMOS PDKs. Using Jupyter Notebooks hosted on Google Colab allows anyone with an internet connection to participate - no downloads or installations required! Relevant circuit examples can be found in [1], [2]. We will leverage code modules available with the OpenFASoC [3] environment.
3. Phase 2 (~July): Interested participants define larger layout building blocks that they wish to automate (examples: comparator, bandgap, phase interpolator, OTA). Teaming among participants is encouraged to maximize collaboration and learning).
4. Phase 3 (~August-September): Participants implement their generators and submit sample layouts and test structures for potential tape-out to an open-source MPW (tentatively SKY130).
5. Phase 4 (~October-November): A jury evaluates the created generators/layouts and selects the test structures that will be taped out. The teams work together to assemble a shared database with all the designs and to complete the tapeout. Ideally, this phase will involve automated verification through CACE [4] or a similar tool.
6. Phase 5 (TBD): The designs will be tested using lab measurements by a subset of participants and SSCS volunteers with access to lab facilities. Some of the test setups may be available for remote characterization. The obtained measurement data will be added to the repositories containing the layout generators.

 References

[1] H. Pretl, “Fifty Nifty Variations of Two-Transistor Circuits,” MOS-AK Workshop Spring 2022, URL: https://www.mos-ak.org/spring_2022/presentations/Pretl_Spring_MOS-AK_2022.pdf.
[2] H. Pretl and M. Eberlein, "Fifty Nifty Variations of Two-Transistor Circuits: A tribute to the versatility of MOSFETs," in IEEE Solid-State Circuits Magazine, vol. 13, no. 3, pp. 38-46, Summer 2021, URL: https://ieeexplore.ieee.org/document/9523464.
[3] OpenFASoC: Fully Open-Source Autonomous SoC Synthesis using Customizable Cell-Based Synthesizable Analog Circuits, https://github.com/idea-fasoc/OpenFASOC/.
[4] Circuit Automatic Characterization Engine, URL: https://github.com/efabless/cace.

GDR SOC2 IEEE CASS

GDR SOC2 - IEEE CASS

“Tour de France” - Grenoble - 19 April 2024

Open Hardware: the new road?

INP; 46 Av Felix Viallet 38000 Grenoble – Amphi Gosse

8:30  Prof. Boris Murmann (U. of Hawaii) 

Re-Energizing Analog Design using the Open-Source Ecosystem. 

9:30  Aurélien Nicolet (CIME-P)

The French platform supporting open hardware

10:00 Krzysztof Herman (IHP)

 IHP Open Source PDK -  sharing experience after one year of development.

11:00 75th anniversary of CAS Society Keynote by Prof. Ricardo Reis.

12:00 Lunch & Cocktail

14:00 Prof. Ricardo Reis (UFRGS)

 Why joining IEEE CAS Society?

14:30 Jean-Paul Chaput (LIP6 – Sorbonne University)

 Coriolis, The European Open Hardware Project 

15:30 Dr. Leonardo Gomes (TIMA - UGA)

 The first 60 GHz circuit designed with open hardware platform

16:00 Deni Alves (UFSC)

 ACM, a design-oriented model for open tools

Inscription Gratuite: à laurence.ben-tito@univ-grenoble-alpes.fr  

IEEE 5NANO2024 Conference 25-26th April, 2024

IEEE 5NANO2024

2024 IEEE International Conference on Nanoelectronics, Nanophotonics,
Nanomaterials, Nanobioscience & Nanotechnology

25th & 26th April 2024

VISAT Engineering College

Elanji, Ernakulam, Kerala, India - 686 665.

The IEEE 5NANO2024 International Conference is going to be dynamic and informative as it provides the premier interdisciplinary forum for researchers, practitioners and educators to present and discuss the most recent innovations, trends, practical challenges encountered, and the solutions adopted in the field of Nanotechnology. The theme of the conference is: “Future Challenges and Advanced Innovations in Nanotechnology”

Contact 5NANO2024:

Dr. T.D.Subash, Conference Organizing Chair - 5NANO2024,
VISAT Engineering College,
Elanji, Ernakulam, Kerala, India - 686 665

Tel: +91 9447691397, +91 9486881397.
E-mail: deanresearch@visat.ac.in, tdsubash2007@gmail.com, 5nano2k24@gmail.com

Website: https://www.5nano2024.com

[Open PDK] IEEE EDS DL at IISc Banglare

IEEE EDS/SSCS Bangalore Chapter Presents DL Series

FOSS TCAD/EDA Tools SPICE and Verilog-A

Modeling Flow Technology - Devices - Applications

W.Grabinski, MOS-AK (EU)

DATE AND TIME	LOCATION	HOSTS
Date: 07 Mar 2024 Time: 04:00 PM to 05:00 PM All times are (UTC+05:30) Chennai Add Event to Calendar iCal Google Calendar	Auditorium, Dept. of ESE, IISc Bangalore Karnataka India 560012	Bangalore Section Jt. Chapter ED15/SSC37

[EDTM] Inauguration Session

8th IEEE EDTM

March 3-6, 2024

Strengthening Globalization in Semiconductors

The 8th Electron Devices Technology and Manufacturing Conference (IEEE EDTM 2024) will be held for the first time in India at Bangalore; the Silicon Valley of India and the hub of semiconductor companies. IEEE EDTM 2024 will be a full four-day conference to be held during March 3-6, 2024. IEEE EDTM 2024 aims to be a premier global forum for researchers and engineers from around the world coming to share new discoveries and discuss any device/manufacturing-related topics, including but not limited to, materials, processes, devices, packaging, modeling, reliability, manufacturing and yield, tools, testing, and any emerging device technologies, as well as workforce training. 

Plenary Talk by Prof. Chenming Hu "Semiconductor – the Next 75 Years?"

[webinar] IEEE SCV-EDS: Investigating quantum speed limits with superconducting qubits

The Electron Devices Society Santa Clara Valley/San Francisco joint Chapter is hosting Prof. Meenakshi Singh. The title of the lecture is ‘Investigating quantum speed limits with superconducting qubits’

When: Friday, Oct. 20, 2023 – 9am to 10am (PDT)
Where: This is an online event and attendees can participate via Zoom.

Registration or Send an email to hiuyung.wong at ieee.org to get the zoom link indicating if you are IEEE member, IEEE EDS member, IEEE Student member

Abstract: The speed at which quantum entanglement between qubits with short range interactions can be generated is limited by the Lieb-Robinson bound. Introducing longer range interactions relaxes this bound and entanglement can be generated at a faster rate. The speed limit for this has been analytically found only for a two-qubit system under the assumption of negligible single qubit gate time. We seek to demonstrate this speed limit experimentally using two superconducting transmon qubits. Moreover, we aim to measure the increase in this speed limit induced by introducing additional qubits (coupled with the first two). Since the speed up grows with additional entangled qubits, it is expected to increase as the system size increases. This has important implications for large-scale quantum computing.

Speaker Bio: Dr. Singh is an experimental physicist with research focused on quantum thermal effects and quantum computing. She graduated from the Indian Institute of Technology with an M. S. in Physics in 2006 and received a Ph. D. in Physics from the Pennsylvania State University in 2012. Her Ph. D. thesis was focused on quantum transport in nanowires. She went on to work at Sandia National Laboratories on Quantum Computing as a post-doctoral scholar. She is currently an Associate Professor in the Department of Physics at the Colorado School of Mines. At Mines, her research projects include measurements of spin-orbit coupling in novel materials and thermal effects in superconducting hybrids. She recently received the NSF CAREER award to pursue research in phonon interactions with spin qubits in silicon quantum dots.

[C4P] LASCAS 2024

 

LASCAS 2024

An IEEE CASS Flagship Conference

15th IEEE LATIN AMERICAN SYMPOSIUM ON CIRCUITS AND SYSTEMS

February 27 - March 01, 2024

ieee-lascas.org

PUNTA DEL ESTE - URUGUAY

Since its first edition in 2010, LASCAS provides a high-quality exchange and networking forum for researchers, professionals, and students, gathering an international audience with experts from all over the world. This event is a space where the CAS community can present new concepts and innovative approaches, learn about new trends and solutions, and receive feedback from specialists in diverse fields.

The 15th edition will take place in Punta del Este, Uruguay. With its lush landscapes, pristine beaches, and sophisticated amenities, it has established itself as a premier tourist destination in South America. It offers an unparalleled experience, where visitors can immerse themselves in a rich blend of natural beauty and modern luxury. The city is easily accessible by air, with regular flights from major cities in South America, and just 90 minute from Montevideo and its international airport. Punta del Este is ready to receive you. The symposium will cover technical novelties and tutorial overviews on circuits and systems topics including but not limited to:

● Analog and Digital Signal Processing

● Biomedical Circuits and Systems

● Intelligent Sensor Systems and Internet of Things

● Artificial Intelligence and Smart Systems

● Nanoelectronics and Gigascale Systems

● Electronic Design Automation

● Circuits and Systems for Communications

● RF Circuits and Systems

● Smart Systems and Smart Manufacturing

● Power Systems and Power Electronic Circuits

● Multimedia Systems and Applications

● Life Science Systems and Applications

● Electronic Testing

● Fault Tolerant Circuits

● Nonlinear Circuits and Systems

● Cognitive Computing and Deep Learning

● Computing and Big Data Applications

Accepted papers will be submitted for inclusion into IEEE Xplore subject to meeting IEEE Xplore’s scope and quality requirements. Best papers will be invited to a special edition of the IEEE Transactions on Circuits and Systems I (TCAS-I) and IEEE Transactions on Circuits and Systems II (TCAS-II). A social program will be offered, including special events and tours to selected attractions for the attendees and their guests.

General Chairs:

Dr. Matías Miguez – UCU, Uruguay. 

Dr. Pablo Pérez-Nicoli – Udelar, Uruguay. 

Program Chairs:

Dr. Maysam Ghovanloo –Silicon Creations, USA

Dr. José Lipovetzky – IB-CNA, Argentina

[C4P] EDTM Conference 2024, Bangalore

8th IEEE Electron Devices Technology and Manufacturing

EDTM Conference 2024

Theme: Strengthening Globalization in Semiconductors

Hilton Bangalore, India, March 3rd- 6th, 2024

https://ewh.ieee.org/conf/edtm/2024/

Call for Paper: We cordially invite you to submit ORIGINAL 3-page Camera-Ready papers to the 2024 IEEE Electron Devices Technology and Manufacturing (IEEE EDTM 2024) Conference for possible presentations. Original papers are sought on any topic within the scope of IEEE EDTM 2024. There are 14 R&D Tracks for IEEE EDTM 2024, among them:

TRACK 9. Modeling and Simulation (MS)

Advances in modeling/simulation of devices, packages and processes; Technology CAD and benchmarking; Atomistic process and device simulation; Compact models for DTCO and STCO; AI/ML-augmented modelling; Material and interconnect modeling; Models for photonic devices.

Important Dates for Authors

• Three-page camera-ready paper submission starts: August 1,2023
• Paper submission deadline: October 15, 2023 October 30, 2023 
• Notification for Acceptance: December 15, 2023

Accepted IEEE EDTM 2024 papers will be considered for competition for the Best Paper Award, Best Student Paper Awards and Best Poster Awards.

More details on paper submission can be found at the Paper Submission webpage.

[EDS MQ/DL] The Transistor Turns 75

The Transistor Turns 75

A Forward Look to Challenges and Opportunities

A series of IEEE EDS Distinguished Lecturer talks on topics in current transistor and electron device research, reflecting on the challenges ahead and the rewards inherrent in overcomming them.

DATE AND TIME	LOCATION	HOSTS	REGISTRATION
Date: 02 Jun 2023 Time: 08:30 AM to 05:30 PM All times are (UTC+00:00) Edinburgh	Moller Institute Cambridge, England UK CB3 ODE Click here for Map	UK and Ireland Section Chapter, ED15 Contact Host	Starts 19 April 2023 06:00 AM Ends 30 May 2023 06:30 PM All times are (UTC+00:00) Edinburgh No Admission Charge Register Now

EDS DL SPEAKERS

• Benjamin Iniguez: Modeling 2D Semiconductor Devices
• Lluis Marsal: Organic Photovoltaics: Opportunities and Challenges
• Arokia Nathan: 
• Fernando Guarin: 75th Anniversary of the Transistor Semiconductor Industry Perspective
• Edmundo A. Gutierrez-D.: DC and RF reliability of advanced bulk and SOI CMOS technologies
• Merlyne De Souza: Challenges to Edge computing: an era beyond silicon CMOS
• Samar Saha: 
• MK Radhakrishnan: Birth and Evolution of Transistor and Its Impact on Humanity
• Xiaojun Guo: Transistor Technologies for Hybrid Integration at Micro- and Macro-scales
• Hiroshi Iwai: Present status and future of the nanoelectronics technology

Commemorative and Networking Event: 75th anniversary of the transistor

IEEE Switzerland Solid State Circuits Chapter

invites you to join the networking event to celebrate

the 75th anniversary of the transistor

Three IEEE Distinguished Lecturers will talk about the transistor history and its properties. It will be followed by short presentations about semiconductor industry activities in Switzerland, with the following networking apéro.

Attendance is free and open to all: mention it and forward to your friends and colleagues.

Please register for logistics reasons. 

Date and Time	Location
Date: 30 Mar 2023 Time: 01:00 PM to 07:30 PM All times are (UTC+01:00) Bern Add Event to Calendar iCal Google Calendar	EPFL Microcity Rue de la Maladière 71C CH-2020 Neuchâtel Room Number: MC A1 272 Click here for Map

Agenda

13:00 – 13:30 Welcome Coffee 

13:30 – 14:15 Tom Lee: From Rocks to Chips: Stories of the Transistor

14:15 – 15:15 Chris Mangelsdorf: Don't try this with CMOS

15:15 – 15:45 Coffee break 

15:45 – 16:30 Christian Enz: The Design of Low-power Analog CMOS Circuits Using the Inversion Coefficient

16:30 – 17:30 Semiconductor industry in Switzerland, sharing experiences 
                        (W.Grabinski, Panel Moderator):

• Bipolar transistor manufacturing in Switzerland – Hugo Wyss
• Integrated Circuits – Eric Vittoz
• Semiconductor design in the 21st century – Alain-Serge Poret
• Micro-electronics for Swiss made products – Evert Dijkstra
• Semiconductor manufacturing equipment – André Gerde

17:30 – 19:00 Apéro riche

Hosts

Switzerland Section Chapter, SSC37 : https://sscs.ieee.ch
Switzerland Section : https://ieee.ch/

[Hisayo Momose] My Journey as a Researcher in the Semiconductor Field

 

Hisayo Mosmose's Story 

Read Hisayo Momose's article from the IEEE EDS January Newsletter, "My Journey as a Researcher in the Semiconductor Field."

Dr. Momose has more than 30 years of experience in research and development at Toshiba Corporation, Japan. She is a recipient of several awards and honors, and has authored or co-authored nearly 200 papers published in technical journals and conference proceedings [read more...]

#IEEE #EDS #ElectronDevices #WiEDS #womeinengineering #semiconductors
 

 

 

[C4P] IEEE LAEDC 2023

On behalf of the Organizing Committee of  IEEE 2023 Latin American Electron Devices Conference (LAEDC) we want to invite you to the next edition of our conference. It will take place in Puebla, Mexico from July 3-5, 2023.

The conference is growing rapidly with worldwide participation and will cover key topics in the field of electronic devices. The main objective of LAEDC is to bring together specialists from all fields related to electronic devices, it will also be aimed at students and young researchers. This event is financially sponsored by IEEE Electron Devices Society (EDS). We are sure that thanks to your significant achievements and contributions, your attendance will significantly increase the value of our conference and motivate research groups and young generations in the field of electronic devices. Please note that discounted registration will be available until June 17, 2023.

Please consider submitting a full paper to our conference proceedings no later than March 31th and engage with our audience and participants while visiting one of the most lively and historic cities in Mexico. For more information, please visit our web site and do not hesitate to contact us 

Sincerely

IEEE EDS MQ at NIT Silchar Silchar, Assam (IN)

IEEE EDS Mini-Colloquium 

on Micro/Nanoelectronics, Devices, Circuits and Systems, 

29-31 Jan 2023 (Hybrid Mode)

DATES	LOCATION	HOST	REGISTER
Date: 29 Jan 2023 Time:10:00AM to 06:00PM  (UTC+05:30)  Add Event to Calendar  iCal  Google Calendar	National Institute of Technology Silchar Dept of ECE, NIT Silchar Silchar, Assam India 788010 Building: ECE/CSE Building	National Inst of Technology - Silchar, ED15 Kolkata Section Chapter NANO42 Co-sponsored by Dr. Trupti R. Lenka	Starts Dec.1, 2022 Ends Jan.28,2023 No Admission Charge Register NOW

Agenda with following contribution Distinguished Lecturers: 

• Anil Kottantharayil (anilkg@ieee.org)
• Gananath Dash (gndash@ieee.org)
• Ajit Kumar Panda (akpanda62@hotmail.com)
• Manoj Saxena (msaxena@ieee.org)
• Brajesh Kumar Kaushik (bkkaushik23@gmail.com)
• Samar Saha (samar@ieee.org)
• Hiroshi Iwai (h.iwai@ieee.org)
• Taiichi Otsuji (taiichi.otsuji.e8@tohoku.ac.jp)
• Pei-Wen Li (pwli@nycu.edu.tw)
• Zhou Xing (EXZHOU@ntu.edu.sg)
• Albert Chin (albert_achin@hotmail.com)
• Mansun Chan (mchan@ust.hk)
• Chao-Sung LAI (cslai@mail.cgu.edu.tw)
• Wladek Grabinski, MOS-AK, EU (wladek@grabinski.ch)

Register NOW

[Program] MINI-COLLOQUIUM ON CAD/EDA MODELING

MINI-COLLOQUIUM ON CAD/EDA MODELING

Sala de Graus, Campus ETSE/ETSEQ

Department of Electronic, Electrical and Automatic Control Engineering, 

University Rovira i Virgili Tarragona, Catalonia, Spain

Chairperson: 

Benjamin Iñiguez, EDS BoG Member and Chair of the ED Spain Chapter

Tuesday, June 28 2022

8:20-8:30 Overview, B. Iñiguez
8:30-9:30 “Characterization and TCAD modeling based design assessment of ultra-high voltage SiC devices,” Muhammad Nawaz (Hitachi Energy, Sweden)
9:30-10:30 “Nanoscale InGaAs FinFETs: Band-to-Band Tunneling and Ballistic Transport,” Jesús del Alamo (MIT, USA)

10:30-11:00 Coffee break

11:00-12:00 “Physics-Based Parameter Extraction for Thin Film Transistors,” Arokia Nathan (Darwin College, University of Cambridge, UK)
12:00-13:00; “Characterization and modeling of organic solar cells,” Lluís F. Marsal (University Rovira I Virgili, Tarragona, Spain)

13:00-15:00 Lunch

15:00-19:00 Meeting of the EDS SRC Region 8 Executive Committee

Wednesday, June 29 2022

11:00-12:00 “Trends and challenges in Nanoelectronics for the next decade,” Elena Gnani (University of Bologna, Italy)
12:00-13:00,“SPICE and Verilog-A Modelling Using FOSS TCAD/EDA Tools: Technology - Devices – Applications” (virtual), Wladek Grabinski (GMC, Switzerland)

13:00-14:20 Lunch

Joint Session 

• MQ on CAD Modeling
• Graduate Student Meeting on Electronic Engineering

14:20-14:30 Overview, B. Iñiguez and J. Ferré-Borrull
14:30-15:30 “Compact modeling of memristive devices for neuromorphic computing,” (virtual) Enrique Miranda (Autonomous University of Barcelona, Spain)
15:30-16:30 Physical Principles to Formulate Thin Film Transistor Models for Circuit Design (virtual), Samar Saha (Prospicient Devices, USA)

16:30-16:35 Closing remarks, B. Iñiguez

IEEE SSCS PICO Contestants Cross the Finish Line

by Boris Murmann

DOI:10.1109/MSSC.2021.3135176

Date of current version: 24 January 2022

Last summer 2021, the IEEE Solid-State Circuits Society (SSCS) launched its first open source chip design contest under the umbrella of its Platform for Integrated Circuit Design Outreach program (PICO). Beginning with 61 submissions, a volunteer jury selected 18 teams from nine countries to embark on a journey toward tapeout. Anyone interested in supporting future activities is encouraged to sign up at the Society’s volunteer web portal. Stay tuned for the 2022 edition of the SSCS PICO contest!

FIG: Layout views of the chips submitted for tape out

      TABLE: A Summary Oof Designs Submitted for TapeOut

	Function	Team	Chip URL
1	5G bidirectional amplifier	Pakistan 3 (National University of Computer and Emerging Sciences)	https://efabless.com/projects/560
2	Wireless power transfer unit	Pakistan 2 (National University of Computer and Emerging Sciences)
3	Variable precision fused multiply–add unit	Pakistan 1 (National University of Computer and Emerging Sciences)
4	Oscillator-based LVDT readout	India 2 (Anna University)	https://efabless.com/projects/474
5	Temperature sensor	India 1 (Anna University)
6	GPS baseband engine	India 3 (Anna University)
7	Ultralow-power analog front end for bio signals	Brazil 2 (Universidade Federal de Santa Catarina)	https://efabless.com/projects/476
8	TIA for quantum photonics interface	USA 4 (University of Virginia)	https://efabless.com/projects/470
9	Bandgap reference	Egypt (Cairo University)	https://efabless.com/projects/473
10	Neural network for sleep apnea detection	USA 2 (University of Missouri)
11	Sonar processing unit	Chile (University of the Bío-Bío)	https://efabless.com/projects/54

[webinar] "More Moore Roadmap" by IRDS and SINANO

IEEE EDS France, IRDS and the SINANO Institute will organize a Webinar 

"More Moore Roadmap"

by Mustafa Badaroglu 

IRDS-IFT More Moore Leader

The webinar will be held on 8th April 2021 at 16:00 Paris time. Interest participants please register via IEEE vTools by the following link: https://events.vtools.ieee.org/event/register/267103

Other Webinars of the IRDS Chapters will be announced in the EDS Newsletters

[C4P] IEEE-NANO 2021 (Virtual) Montreal, Canada

IEEE-NANO 2021 Nanotechnology Flagship Conference July 28-30, 2021 | Virtual from Montreal, Canada Abstract Submission Deadline Extended: March 15, 2021  Website: https://2021.ieeenano.org CALL for PAPERS (download PDF) Nanotechnology researchers will gather to exchange information across disciplines at the 21st IEEE International Conference in Nanotechnology, the flagship conference of the IEEE Nanotechnology Council. We hope you will join us at IEEE-NANO 2021, to be held virtually July 28th–30th, 2021 from Montreal. The IEEE-NANO 2021 is now calling for abstract submission. View Technical Interests Here and access the Submission System Here We are delighted to share with you our confirmed distinguished plenary speakers: John Polanyi, Nobel Laureate (University of Toronto) Yury Gogotsi (Drexel University) Luisa De Cola (University of Strasbourg) Shelley Minteer (University of Utah) Following the tradition of the NANO conferences, participants have the opportunity to publish their research in IEEE Xplore® and IEEE Transactions in Nanotechnology. Important Dates: Abstract Submission: March 15, 2021 Notice of acceptance: March 31, 2021 Submission of full paper for proceedings: May 1, 2021 Short notice proceedings for exceptional findings: June 1, 2021 Notification of short notice proceedings acceptance-revision-rejection: June 15, 2021