[paper] TCAD for Circuits and Systems

Z. Stanojevic, X. Klemenschits, G. Rzepa, F. Mitterbauer, C. Schleich,

F. Schanovsky, O. Baumgartner, and M. Karner

TCAD for Circuits and Systems: Process Emulation, Parasitics Extraction, Self-Heating

2024 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium

BCICTS, Fort Lauderdale, FL, USA, 2024, pp. 294-297

doi: 10.1109/BCICTS59662.2024.10745677

1 Global TCAD Solutions GmbH., Boesendorferstraße 1/12, 1010 Vienna, Austria

Abstract: We present TCAD-based methodologies that go beyond process and device simulations of single transistors. We show that TCAD solvers can be used as effective tools to resolve the intricacies of current and future technology nodes that are otherwise difficult to access using EDA-level methods alone.

Fig: Single NMOS/PMOS FinFET with the local contacts and their parasitic R/C-components; fitting results for NMOS and PMOS FinFET: gate capacitance, transfer characteristics, output characteristics

[book] Microelectronic Circuits

Sedra, Adel S., Smith, Kenneth Carless, Carusone, 

Tony Chan, Gaudet, Vincent. 

Microelectronic Circuits. 

United Kingdom: Oxford University Press, 2020

Circuits by Sedra and Smith has served generations of electrical and computer engineering students as the best and most widely-used text for this required course. Respected equally as a textbook and reference, "Sedra/Smith" combines a thorough presentation of fundamentals with an introduction to present-day IC technology. It remains the best text for helping students progress from circuit analysis to circuit design, developing design skills and insights that are essential to successful practice in the field. Significantly revised with the input of two new coauthors, slimmed down, and updated with the latest innovations, Microelectronic Circuits, Eighth Edition, remains the gold standard in providing the most comprehensive, flexible, accurate, and design-oriented treatment of electronic circuits available today.

Appendix

• B. SPICE Device Models and Design with Simulation Examples

Model files for representative CMOS technologies are provided below:

• 0.8 um CMOS
• 0.35 um CMOS
• 0.18 um CMOS
• 45 nm CMOS
• 7nm FinFET

 

[C4P] LASCAS 2024

 

LASCAS 2024

An IEEE CASS Flagship Conference

15th IEEE LATIN AMERICAN SYMPOSIUM ON CIRCUITS AND SYSTEMS

February 27 - March 01, 2024

ieee-lascas.org

PUNTA DEL ESTE - URUGUAY

Since its first edition in 2010, LASCAS provides a high-quality exchange and networking forum for researchers, professionals, and students, gathering an international audience with experts from all over the world. This event is a space where the CAS community can present new concepts and innovative approaches, learn about new trends and solutions, and receive feedback from specialists in diverse fields.

The 15th edition will take place in Punta del Este, Uruguay. With its lush landscapes, pristine beaches, and sophisticated amenities, it has established itself as a premier tourist destination in South America. It offers an unparalleled experience, where visitors can immerse themselves in a rich blend of natural beauty and modern luxury. The city is easily accessible by air, with regular flights from major cities in South America, and just 90 minute from Montevideo and its international airport. Punta del Este is ready to receive you. The symposium will cover technical novelties and tutorial overviews on circuits and systems topics including but not limited to:

● Analog and Digital Signal Processing

● Biomedical Circuits and Systems

● Intelligent Sensor Systems and Internet of Things

● Artificial Intelligence and Smart Systems

● Nanoelectronics and Gigascale Systems

● Electronic Design Automation

● Circuits and Systems for Communications

● RF Circuits and Systems

● Smart Systems and Smart Manufacturing

● Power Systems and Power Electronic Circuits

● Multimedia Systems and Applications

● Life Science Systems and Applications

● Electronic Testing

● Fault Tolerant Circuits

● Nonlinear Circuits and Systems

● Cognitive Computing and Deep Learning

● Computing and Big Data Applications

Accepted papers will be submitted for inclusion into IEEE Xplore subject to meeting IEEE Xplore’s scope and quality requirements. Best papers will be invited to a special edition of the IEEE Transactions on Circuits and Systems I (TCAS-I) and IEEE Transactions on Circuits and Systems II (TCAS-II). A social program will be offered, including special events and tours to selected attractions for the attendees and their guests.

General Chairs:

Dr. Matías Miguez – UCU, Uruguay. 

Dr. Pablo Pérez-Nicoli – Udelar, Uruguay. 

Program Chairs:

Dr. Maysam Ghovanloo –Silicon Creations, USA

Dr. José Lipovetzky – IB-CNA, Argentina

IEEE EDS MQ at NIT Silchar Silchar, Assam (IN)

IEEE EDS Mini-Colloquium 

on Micro/Nanoelectronics, Devices, Circuits and Systems, 

29-31 Jan 2023 (Hybrid Mode)

DATES	LOCATION	HOST	REGISTER
Date: 29 Jan 2023 Time:10:00AM to 06:00PM  (UTC+05:30)  Add Event to Calendar  iCal  Google Calendar	National Institute of Technology Silchar Dept of ECE, NIT Silchar Silchar, Assam India 788010 Building: ECE/CSE Building	National Inst of Technology - Silchar, ED15 Kolkata Section Chapter NANO42 Co-sponsored by Dr. Trupti R. Lenka	Starts Dec.1, 2022 Ends Jan.28,2023 No Admission Charge Register NOW

Agenda with following contribution Distinguished Lecturers: 

• Anil Kottantharayil (anilkg@ieee.org)
• Gananath Dash (gndash@ieee.org)
• Ajit Kumar Panda (akpanda62@hotmail.com)
• Manoj Saxena (msaxena@ieee.org)
• Brajesh Kumar Kaushik (bkkaushik23@gmail.com)
• Samar Saha (samar@ieee.org)
• Hiroshi Iwai (h.iwai@ieee.org)
• Taiichi Otsuji (taiichi.otsuji.e8@tohoku.ac.jp)
• Pei-Wen Li (pwli@nycu.edu.tw)
• Zhou Xing (EXZHOU@ntu.edu.sg)
• Albert Chin (albert_achin@hotmail.com)
• Mansun Chan (mchan@ust.hk)
• Chao-Sung LAI (cslai@mail.cgu.edu.tw)
• Wladek Grabinski, MOS-AK, EU (wladek@grabinski.ch)

Register NOW

[paper] SPICE Modeling and Circuit Demonstration of a SiC Power IC Technology

Tianshi Liu¹, Hua Zhang¹, Sundar Babu Isukapati², Emran Ashik³, Adam J. Morgan², Bongmook Lee³, Woongje Sung², Ayman Fayed¹, Marvin H. White¹, and Anant K. Agarwal¹

SPICE Modeling and Circuit Demonstration of a SiC Power IC Technology

IEEE Journal of the Electron Devices Society, vol. 10, pp. 129-138, 2022, 

DOI: 10.1109/JEDS.2022.315036

   
1 Department of Electrical & Computer Engineering, The Ohio State University, Columbus, OH 43210, USA
2 College of Nanoscale Science and Engineering, State University of New York Polytechnic Institute, Albany, NY 12309, USA
3 Department of Electrical & Computer Engineering, North Carolina State University, Raleigh, NC 27695, USA

Abstract: Silicon carbide (SiC) power integrated circuit (IC) technology allows monolithic integration of 600 V lateral SiC power MOSFETs and low-voltage SiC CMOS devices. It enables application-specific SiC ICs with high power output and work under harsh (high-temperature and radioactive) environments compared to Si power ICs. This work presents the device characteristics, SPICE modeling, and SiC CMOS circuit demonstrations of the first two lots of the proposed SiC power IC technology. Level 3 SPICE models are created for the high-voltage lateral power MOSFETs and low-voltage CMOS devices. SiC ICs, such as the SiC CMOS inverter and ring oscillator, have been designed, packaged, and characterized. Proper operations of the circuits are demonstrated. The effects of the trapped interface charges on the characteristics of SiC MOSFETs and SiC ICs are also discussed.

FIG: Cross-sectional view of the SiC MOSFETs (lot2)

Acknowledgment The authors would like to thank the team at Analog Devices (ADI), Hillview facility for the fabrication of devices and Advanced Research Projects Agency-Energy (ARPA-E). The authors also thank D. Xing for providing the customized gate driver for the dynamic characterizations of the circuits

[paper] Bridging the gap between design and simulation of low voltage CMOS circuits

C. M. Adornes, D. G. Alves Neto, M. C. Schneider and C. Galup-Montoro

Bridging the gap between design and simulation of low voltage CMOS circuits

2021 IEEE Nordic Circuits and Systems Conference (NorCAS), 2021, pp. 1-5,

DOI: 10.1109/NorCAS53631.2021.9599867

Abstract: This work proposes a simplified MOSFET model based on the Advanced Compact MOSFET (ACM) model, which contains only four parameters to assist the designer in understanding how the main MOSFET parameters affect the design. The 4-parameter model was implemented in Verilog-A to simulate different circuits designed with the ACM model. A CMOS inverter and a ring oscillator were designed and simulated, either using the 4-parameter ACM model or the BSIM model. The simulation results demonstrate that the 4-parameter model is very suitable for ultra-low-voltage (ULV) modeling. In the ultra-low-voltage domain, some of the secondary effects of the MOSFET are not relevant and thus not included in the 4-parameter model. A simplified MOSFET model for the ULV domain is of great importance to applications such as energy harvesting, sensor nodes for the Internet of Things, and always-on circuits.

C. M. Adornes Video Presentation NorCAS 2021

Acknowledgment: The authors would like to thank the Brazilian agencies CAPES, finance code 001, and CNPq for supporting this work.

REF:

[1] A. I. A. Cunha, M. C. Schneider and C. Galup-Montoro, "An MOS Transistor Model for Analog Circuit Design", IEEE J. Solid-State Circuits, vol. 33, no. 10, pp. 1510-1519, October 1998

[2] C. Galup-Montoro and M. C. Schneider, "The compact all-region MOSFET model: theory and applications", IEEE 16th International New Circuits and Systems Conference (NEWCAS), pp. 166-169, June 2018

[3] M. C. Schneider and C. Galup-Montoro, CMOS Analog Design Using All-Region MOSFET Modeling, Cambridge University Press, 2010

[4] C. Galup-Montoro and M. C. Schneider, MOSFET modeling for circuit analysis and design, World Scientific, 2007

[5] Verilog-A Reference Manual, Agilent Technologies, 2004

[6] 0. F. Siebel, "Um modelo eficiente do transistor MOS para o projeto de circuitos VLSI," Universidade Federal de Santa Catarina, Florianopolis, 2007

[7] F. N. Fritsch, R. E. Shafer and W. P. Crowley, "Algorithm 443: Solution of the transcendental equation wew=x," Commun. ACM, vol. 16, no. 2, pp. 123-124, 1973

[8] O. F. Siebel, M. C. Schneider and C. Galup-Montoro, "MOSFET threshold voltage definition, extraction and some applications," Microelectronics Journal, vol. 43, no. 5, pp. 329-336, May 2012

[9] G. Hiblot. DIBL-Compensated Extraction of the Channel Length Modulation Coefficient in MOSFETS. IEEE Transactions on Electron Devices, vol. 65, no. 9, pp. 4015-4018, 2018

[10] BSIM4v4.5.0 Technical Manual, Department of Electrical Engineering and Computer Science, UC Berkeley, Berkeley, CA, USA. 2004

[11] Y. Tsividis and C. McAndrew, Operation and Modeling of the MOS Transistor, Oxford Univ. Press, 2011

[12] J. V. T. Ferreira, C. Galup-Montoro, "Ultra-low-voltage CMOS ring oscillators. Electronics Letters," IET, v. 55, n. 9, p. 523-525,2019

[13] E. M. Camacho-Galeano, C. Galup-Montoro and M. C. Schneider, "A 2-nW 1.1.-V self biased current reference in CMOS technology," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 52, no. 2, pp. 61-65, 2005

[14] E. Bolzan, E. B. Storck, M. C. Schneider and C. Galup-Montoro, "Design and testing of a CMOS SelfBiased Current Source," 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 382-385, 2019

[paper] SET and CMOS circuits

Tetsufumi Tanamoto¹, and Keiji Ono²

Simulations of hybrid charge-sensing single-electron-transistors and CMOS circuits

Appl. Phys. Lett. 119, 174002 (2021)

DOI: 10.1063/5.0068555

1Department of Information and Electronic Engineering, Teikyo University (J)
2Advanced Device Laboratory, RIKEN (J)

Abstract: Single-electron transistors (SETs) have been extensively used as charge sensors in many areas, such as quantum computations. In general, the signals of SETs are smaller than those of complementary metal–oxide–semiconductor (CMOS) devices, and many amplifying circuits are required to enlarge the SET signals. Instead of amplifying a single small output, we theoretically consider the amplification of pairs of SETs, such that one of the SETs is used as a reference. We simulate the two-stage amplification process of SETs and CMOS devices using a conventional SPICE (Simulation Program with Integrated Circuit Emphasis) circuit simulator. Implementing the pairs of SETs into CMOS circuits makes the integration of SETs more feasible because of direct signal transfer from the SET to the CMOS circuits.

Fig: (a) Six transistor SRAM cells applied in the second-stage amplification 

(b) Time-dependent voltage behaviors of the SRAM setup of L = 90 nm  

(c) Replotting of (b) for L = 65 nm.

[symposium] ISDCS 2021 Hiroshima University

ISDCS 2021

3-5, March 2021

Hiroshima University, Higashi-Hiroshima, Japan

The ISDCS is a premium international forum for scholars, scientists, educators, students and engineers to exchange their latest findings and technological advances in the field of devices, circuits and systems.

Keynote Speakers

• Prof. Parthasarathi Chakrabarti, Director, IIEST Shibpur and Department of Electronics Engineering, IIT(BHU), India
  "Advanced Materials and Methods for Fabrication of Thin-film Transistor (TFT)-based Sensors"
• Prof. Shinji Kaneko, Hiroshima University, Japan
  "SDGs Initiatives at Hiroshima University: Integrating Global Strategy and Regional Vitalization"

Invited Speakers

• Prof. Sanatan Chattopadhyay, University of Calcutta, India
  "Voltage Assisted Quantum Dot Based MOS Devices for Electronic and Optoelectronic Applications"
• Prof. Partha Bhattacharya, IIEST Shibpur, India
  "Performance Improvement of Graphene Derivative based Gas sensors: Role of Functional Group Tuning and Ternary Junction Formation"
• Prof. Hafizur Rahaman, IIEST Shibpur, India
  "Tunnel Field Effect Transistors: Challenges and Opportunities"
• Prof. Nillohit Mukherjee, IIEST Shibpur, India
  "Metal Oxide Semiconductors with Carbon Nanomaterials for Efficient Supercapacitive Type Energy Storage Devices"
• Prof. Shigeyasu Uno, Ritsumeikan University, Japan
  "Electrochemical Impedance Sensor for Non-invasive Living Cell Monitoring toward CMOS Cell Culture Monitoring Platform"
• Mr. Shigeru Shiratake, Corporate Vice President, DRAM, Emerging Memory Process Integration and Device Technology Micron Technology, Inc., USA
  "Challenges for DRAM scaling and performance enhancement"
• Prof. Rihito Kuroda, Tohoku University, Japan
  TBD

Previous Conference:

• ISDCS 2020, Kolkata, India
• ISDCS 2019, Higashi-hiroshima, Japan
• ISDCS 2018, Kolkata, India

[paper] Readout electronics for LGAD sensors

Readout electronics for LGAD sensors

O. Alonso,^a N. Franch,^a J. Canals,^a F. Palacio,^a M. López,^a A. Vilà,^a A. Diéguez,^a
M. Carulla,^b D. Flores,^b S. Hidalgo,^b A. Merlos,^b G. Pellegrini^b and D. Quirion^b
aDepartment of Engineering: Section of Electronics, University of Barcelona,
C/ Martí i Franquès nº1, Barcelona, 08028 Spain
^bInstituto de Microelectrónica de Barcelona — Centro Nacional de Microelectrónica (IMB-CNM),
Campus UAB, Cerdanyola del Vallès, Bellaterra, Barcelona, 08193 Spain
doi:10.1088/1748-0221/12/02/C02069

Abstract: In this paper, an ASIC fabricated in 180 nm CMOS technology from AMS with the very front-end electronics used to readout LGAD sensors is presented as well as its experimental results. The front-end has the typical architecture for Si-strip readout, i.e., preamplification stage with a Charge Sensitive Amplifier (CSA) followed by a CR-RC shaper. Both amplifiers are based on a folded cascode structure with a PMOS input transistor and the shaper only uses passive elements for the feedback stage. The CSA has programmable gain and a configurable input stage in order to adapt to the different input capacitance of the LGAD sensors (pixelated, short and long strips) and to the different input signal (depending on the gain of the LGAD). The fabricated prototype has an area of 0.865mm  0.965mm and includes the biasing circuit for the CSA and the shaper, 4 analog channels (CSA+shaper) and programmable charge injection circuits included for testing purposes. A first approach to find the proper dimensioning of the input transistor has been done using a Matlab script, where the transconductance value has been calculated with the EKV model

Acknowledgments This work has been partially funded by the Spanish national projects FPA2013-48387 and FPA2015-71292. In addition, this work has been done in the framework of RD50 CERN collaboration.

ESSDERC ESSCIRC in Graz (A)

 ESSDERC 2015: 45th European Solid-State Device Conference

 ESSCIRC 2015: 41th European Solid-State Circuits Conference

 September 14-18, 2015 - Graz, Austria

The aim of ESSDERC and ESSCIRC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits. The increasing level of integration for system-on-chip design made available by advances in silicon technology is, more than ever before, calling for a deeper interaction among technologists, device experts, IC designers, and system designers. While keeping separate Technical Program Committees, ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both communities. Attendees registered for either conference are encouraged to attend any of the scheduled parallel sessions, regardless to which conference they belong.

Read more:

• Program at a glance (Sept. 14 to 18, 2015 including Tutorials and Workshops)
• Program folder