2nd Semiconductor Device Frontier Summit

Date: May 18, 2026; Time: 10:00AM ~ 05:00PM

Ewha Womans University Student Culture Center (Small Theater B101)

The Semiconductor Device Research Group of the Society of Semiconductor Engineers has been holding this event since 2025 to strengthen human networks among domestic researchers and share the latest research trends.

This year's summit, now in its second year, invited top-notch speakers from various fields to provide a broad view of the latest technologies in industry and academia. It will be a place for meaningful academic exchanges to grasp the latest semiconductor technology trends as well as to share in-depth opinions on international market trends. This event is co-organized by the Society of Semiconductor Engineers and the IEEE EDS Seoul Section Chapter and aims to become an international event representing the semiconductor device field in Korea in the future. We ask for your interest and participation so that the 'Semiconductor Device Frontier Summit', which will be the core pillar of the Korean researcher network, can become the cornerstone of the development of our semiconductor industry.

Pre-registration deadline: Until May 16, 2026 (Saturday)

Time	Program
Opening Session
10:00 – 10:20	Welcome & Registration
10:20 – 10:30	Opening Remarks (Prof. Sung‑Jae Cho, Ewha Womans University)
Session 1 | Chair: Prof. Sung‑Jae Cho
10:30 – 11:15	Semiconductor Devices for the New Computing Era Prof. Woo‑Young Choi, Seoul National University
11:15 – 12:00	Development Strategy for AI‑Oriented NAND Solutions Prof. Ki‑Hwan Song, Yonsei University
12:00 – 13:30	Lunch
Session 2 | Chair: Prof. Myung‑Gon Kang
13:30 – 14:15	Trends and Outlook of eNVM Technology Visiting Prof. Yong‑Gyu Lee, Seoul National University
14:15 – 15:00	Memcapacitor Technology for Charge‑Domain PIM Implementation Prof. Tae‑Hyun Kim, Seoul National University of Science and Technology
15:00 – 15:10	Coffee Break
Session 3 | Chair: Prof. Il‑Hwan Cho
15:10 – 15:55	Atomically Thin 2D Semiconductor Electronics toward Beyond‑CMOS Technology Prof. Chul‑Ho Lee, Seoul National University
15:55 – 16:40	Orders‑of‑Magnitude Faster TCAD Device Simulation of GAA MOSFETs without Additional Computational Training Cost Prof. Sung‑Min Hong, GIST
16:40 – 17:00	Closing Ceremony | Prof. Il‑Hwan Cho, Myongji University

[paper] Threshold Engineering in 2D FETs

Dipanjan Sen, Harikrishnan Ravichandran, Safdar Imam, Subir Ghosh, Krishnendu Mukhopadhyay, Md Yasir Bashir, Thomas S. Ie, Vlastimil Mazanek, Jan Luxa, Chen Chen, Joan M. Redwing, Zdenek Sofer, Shubham Sahay, Mercouri G. Kanatzidis and Saptarshi Das

van der Waals dielectrics for threshold engineering in two-dimensional field effect transistors

Nature Communications (2026)

DOI: 10.1038/s41467-026-69089-6

1. Engineering Science and Mechanics, Penn State University, University Park, PA 16802, USA
2. Department of Chemistry, Northwestern University, Evanston, IL 60208, USA
3. Electrical Engineering, Indian Institute of Technology, Kanpur, India
4. Department of Inorganic Chemistry, University of Chemistry and Technology Prague, CzechRepublic
5. 2DCC, Penn State University, University Park, PA 16802, USA
6. Materials Science and Engineering, Penn State University, University Park, PA 16802, USA
7. Electrical Engineering, Penn State University, University Park, PA 16802, USA

Abstract: Two-dimensional (2D) semiconductors are promising for next-generation field-effect transistors (FETs), but their integration into complementary-metal-oxide-semiconductors (CMOS) logic is hindered by improper threshold voltages (Vth), leading to excessive power consumption. While past efforts have focused on improving electrostatics and near-ideal subthreshold swing (𝑺𝑺), systematic Vth engineering in 2D FETs remains unexplored. Here, we investigate high-κ van der Waals (vdW) dielectrics including metal oxyhalides such as LaOBr, BiOBr, and BiOCl, and bimetallic thiophosphates such as LiInP2S6 (LIPS), LiInP2Se6 (LIPSe) and CuInP2S6 (CIPS) and demonstrate that bimetallic thiophosphates enable programmable and non-volatile Vth tuning in both n-type monolayer MoS₂ and p-type bilayer WSe2 FETs. Leveraging ion-mediated Vth tuning, we realize 2DCMOS inverters with nearly three orders of magnitude reduction in static power while maintaining high switching speed. Combining experiments with industry-compatible SPICE modeling, we identify an optimal Vth window that minimizes power without significant delay penalty, enabling built-in power gating and improved power–performance–area metrics without additional sleep transistors.

Fig: LiInP2S6 as a top-gate dielectric for 2D field-effect transistors (FETs). a) angled scanning electron microscope (SEM) image of dual-gated 2D FET with LiInP2S6(LIPS) as top-gate dielectric and 25 nm thick Al2O3 as the back-gate dielectric. Dual-sweep top-gate transfer characteristic of a b) WSe2 FET obtained by sweeping the VTG from -8 V to 8 V at a constant 𝑉𝐵𝐺 = -4 V and 𝑉𝐷𝑆 = 1 V, both exhibiting a counterclockwise (CCW) hysteresis.

Acknowledgements: SD acknowledges funding support from the National Science Foundation for NSF Career under grant number ECCS-2042154, NSF Fuse, under grant number ECCS-2328741, ONR under grant number N00014-24-1-2565, and ARO under grant number W911NF-23-1-0279. The MOCVDTMD films were grown in the 2D Crystal Consortium–Materials Innovation Platform (2DCC-MIP) facility which is supported by the National Science Foundation under cooperative agreement DMR-2039351. The work at Northwestern was supported in part by the National Science Foundation under award number DMR-2305731. ZS was supported by ERC-CZ program (project LL2101) from the Ministry of Education Youth and Sports (MEYS) and by the project Advanced Functional Nanorobots (reg. No. CZ.02.1.01/0.0/0.0/15_003/0000444 financed by the EFRR). JL was supported by Czech Science Foundation (GACR No. 24-11465S). VM was supported by project LUAUS23049 from Ministry of Education Youth and Sports (MEYS). SS acknowledges the Ministry of Education’s Scheme for Transformational and Advanced Research in Sciences (STARS) Project under Grant MoE-STARS/STARS-2/2023-0023, DST Indo-Korea Research Grant INT/Korea/P-66 under Grant E-47691 and the University Grant Commission, Government of India, through the Senior Research Fellowship, student ID: 200510263123

2026 Asia-Pacific Workshop on Advanced Semiconductor Devices

2026 Asia-Pacific Workshop on Advanced Semiconductor Devices (AWAD 2026)

July 12-14, 2026

Asti Hotel Busan, Korea

Paper submission deadline: Apr 19, 2026

This annual workshop has been held alternately in Japan and Korea since 1993, and the AWAD 2026 Workshop will be the 33rd in workshop's series. The purposes of this workshop are to bring scientists and engineers together, actively engaged in advanced semiconductor devices and materials, and to discuss the present and future device processing and related technologies. The workshop will cover the entire field of semiconductor devices and materials, from fundamental physics to recent improvements in device performance and processing technology [read more...] 

[For Korean Participants] AWAD 학회는 BK21 Four 규정에 따른 국제학회입니다.

AWAD 2026 Venue Asti Hotel Busan [48733] 7-8, Jungang-daero 214 beon-gil, Dong-gu, Busan, Republic of Korea Important Dates Paper submission deadline: Apr 19, 2026 Acceptance notification: May , 2026 Author registration: June, 2026 Advance registration: June, 2026

Topics of Interest Advanced semiconductor technologies MOS logic and memory devices Characterization and simulation Quantum devices and computing technologies Compound semiconductor materials and devices Optoelectronics, displays, and imagers Nano, 2D materials, and wearable devices Power electronic devices Neuromorphic devices and compute technologies Advanced packaging technologies

Organized by 

• The Institute of Electronics and Information Engineers (IEIE), Korea 
• The Institute of Electronics, Information and Communication Engineers (IEICE-ES), Japan
• IEEE Electron Devices Society (EDS) Seoul Section Chapter

[paper] Gate stack engineering of 2D transistors

Yeon Ho Kim, Donghun Lee, Woong Huh, Jaeho Lee, Donghyun Lee, 

Gunuk Wang, Jaehyun Park, Daewon Ha and Chul-Ho Lee*

Gate stack engineering of two-dimensional transistors.

Nat Electron 8, 770–783 (2025)

DOI: 10.1038/s41928-025-01448-5

* Laboratory of Emerging Electronics & optoElectronics, SNU / julianus95@snu.ac.kr

Abstract: Gate stack engineering has helped enable aggressive device scaling in silicon complementary metal–oxide–semiconductor technology. Two-dimensional (2D) materials are a potential replacement for silicon in next-generation electronics. However, creating gate stacks that are capable of effective and reliable channel control with such materials is inherently challenging owing to the lack of compatible dielectrics and fabrication methods. Here we explore the development of gate stack engineering technologies for two-dimensional transistors. We benchmark key performance metrics for two-dimensional metal–oxide–semiconductor gate stacks against current silicon-based technologies, as well as the targets set by the International Roadmap for Devices and Systems. We also highlight recent advances in ferroelectric-embedded gate stacks, which offer additional functionalities and could be of use in the development of high-speed non-volatile memories and logic-in-memory devices, as well as low-power transistors. Finally, we consider the technical challenges that need to be addressed to develop advanced electronic technologies based on two-dimensional transistors.

FIG: CMOS logic technology roadmap and potential of angstrom-scale 2D transistors

Acknowledgment: This research was supported by the Ministry of Science and ICT under the Next-Generation Intelligent Semiconductor Technology Development Project and the Nano and Material Technology Development Program (Future Technology Labs). The graduate researchers received additional support from BK21 Four and the SNU Graduate School of AI Semiconductor.

[paper] Microchips for Memristive Applications

Kaichen Zhu, Sebastian Pazos, Fernando Aguirre, Yaqing Shen, Yue Yuan, Wenwen Zheng, Osamah Alharbi, Marco A. Villena, Bin Fang, Xinyi Li, Alessandro Milozzi, Matteo Farronato, Miguel Muñoz-Rojo, Tao Wang, Ren Li, Hossein Fariborzi, Juan B. Roldan, Guenther Benstetter, Xixiang Zhang, Husam N. Alshareef, Tibor Grasser, Huaqiang Wu, Daniele Ielmini & Mario Lanza 

Hybrid 2D–CMOS microchips for memristive applications

Nature 618, 57–62 (2023)

DOI: 10.1038/s41586-023-05973-1

Abstract: Exploiting the excellent electronic properties of two-dimensional (2D) materials to fabricate advanced electronic circuits is a major goal for the semiconductor industry1,2. However, most studies in this field have been limited to the fabrication and characterization of isolated large (more than 1 µm2) devices on unfunctional SiO2–Si substrates. Some studies have integrated monolayer graphene on silicon microchips as a large-area (more than 500 µm2) interconnection3 and as a channel of large transistors (roughly 16.5 µm2) (refs. 4,5), but in all cases the integration density was low, no computation was demonstrated and manipulating monolayer 2D materials was challenging because native pinholes and cracks during transfer increase variability and reduce yield. Here, we present the fabrication of high-integration-density 2D–CMOS hybrid microchips for memristive applications—CMOS stands for complementary metal–oxide–semiconductor. We transfer a sheet of multilayer hexagonal boron nitride onto the back-end-of-line interconnections of silicon microchips containing CMOS transistors of the 180 nm node, and finalize the circuits by patterning the top electrodes and interconnections. The CMOS transistors provide outstanding control over the currents across the hexagonal boron nitride memristors, which allows us to achieve endurances of roughly 5 million cycles in memristors as small as 0.053 µm2. We demonstrate in-memory computation by constructing logic gates, and measure spike-timing dependent plasticity signals that are suitable for the implementation of spiking neural networks. The high performance and the relatively-high technology readiness level achieved represent a notable advance towards the integration of 2D materials in microelectronic products and memristive applications.

FIG: Structure of the considered SNN. Each MNIST image is reshaped as a 784x1 column vector, and the intensity of the pixels is encoded in terms of the firing frequency of the input neurons. The only trainable synapses are those connecting the input layer with the excitatory layer, and they are modelled with the STDP characteristic of the CMOS-h-BN based 1T1M cells. The learning is unsupervised, and the neurons are labelled only after the training. These label-neuron assignments are then feed to the decision block altogether with the firing patterns of the neurons, to infer the class of the image presented in the input. 

Acknowledgements: This work has been supported by the Ministry of Science and Technology of China (grant nos. 2019YFE0124200 and 2018YFE0100800), the National Natural Science Foundation of China (grant no. 61874075) and the Baseline funding scheme of the King Abdullah University of Science and Technology.

Compact Modeling of 2D Field-Effect Biosensors

Francisco Pasadas¹, Tarek El Grour², Enrique G. Marin¹, Alberto Medina-Rull¹, Alejandro Toral-Lopez¹, Juan Cuesta-Lopez¹, Francisco G. Ruiz¹, Lassaad El Mir² and Andrés Godoy¹

Compact Modeling of Two-Dimensional Field-Effect Biosensors.

Sensors 2023, 23, 1840.

DOI: 10.3390/s23041840

1 Pervasive Electronics Advanced Research Laboratory (PEARL), Departamento de Electrónica y Tecnología de Computadores, Universidad de Granada,18071 Granada, Spain
2 Laboratory of Physics of Materials and Nanomaterials Applied at Environment (LaPhyMNE) LR05ES14, Faculty of Sciences of Gabes, Gabes University, Erriadh City, Zrig, 6072 Gabes, Tunisia

Abstract: A compact model able to predict the electrical read-out of field-effect biosensors based on two-dimensional (2D) semiconductors is introduced. It comprises the analytical description of the electrostatics including the charge density in the 2D semiconductor, the site-binding modeling of the barrier oxide surface charge, and the Stern layer plus an ion-permeable membrane, all coupled with the carrier transport inside the biosensor and solved by making use of the Donnan potential inside the ion-permeable membrane formed by charged macromolecules. This electrostatics and transport description account for the main surface-related physical and chemical processes that impact the biosensor electrical performance, including the transport along the low-dimensional channel in the diffusive regime, electrolyte screening, and the impact of biological charges. The model is implemented in Verilog-A and can be employed on standard circuit design tools. The theoretical predictions obtained with the model are validated against measurements of a MoS2 field-effect biosensor for streptavidin detection, showing excellent agreement in all operation regimes and leading the way for the circuit-level simulation of biosensors based on 2D semiconductors

FIG: Schematic of a two-dimensional field-effect biosensor. A sketch of the position-dependent potential is also shown, highlighting the surface charge density at the 2D channel (σ2D), at the oxide-electrolyte interface (σ0), and at the membrane-diffuse regions of the electrolyte (σmd). The latter comprises a charge-free layer (Stern layer) and an ion-permeable membrane due to the presence of charged macromolecules, with a diffusion layer located between the barrier oxide surface and the bulk electrolyte. The potential difference from the electrolyte bulk to the barrier oxide surface, ψ0, encompasses two contributions originating from a potential drop (ψ0 − ψm) across the Stern layer extending between the outer Helmholtz plane (OHP) and the barrier oxide surface, and a potential drop across the ion-permeable membrane layer formed by charged macromolecules and the diffuse layer (ψm)

Funding: This work is funded by the Spanish Government MCIN/AEI/10.13039/501100011033 through the projects PID2020-116518GB-I00 and TED2021-129769B-I00 (MCIU/AEI/FEDER-UE); and by FEDER/Junta de Andalucía-Consejería de Transformacion Económica, Industria, Conocimiento y Universidades through the projects P20_00633 and A-TIC-646-UGR20. F. Pasadas acknowledges funding from PAIDI 2020 and the European Social Fund Operational Programme 2014–2020 no. 20804. A. Medina-Rull acknowledges the support of the MCIN/AEI/PTA grant, with reference PTA2020- 018250-I. J. Cuesta-Lopez acknowledges the FPU program FPU019/05132, and A. Toral-Lopez the support of Plan Propio of Universidad de Granada.

Data Availability Statement: The Verilog-A model for 2D EIS BioFETs is available from the corresponding author (fpasadas@ugr.es) upon reasonable request.

[paper] Perspective of Ultra-Scaled CMOS

Ab initio perspective of ultra-scaled CMOS

from 2D-material fundamentals to dynamically doped transistors

Aryan Afzalian 

Open Access; npj 2D Mater Appl 5, 5 (2021) 

DOI: 10.1038/s41699-020-00181-1 

Abstract: Using accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10-nm scaling for high-performance complementary metal oxide semiconductor (CMOS) applications. We show that a combination of good electrostatic control together with high mobility is paramount to meet the stringent roadmap targets. Such requirements typically play against each other at sub-10-nm gate length for MOS transistors made of conventional semiconductor materials like Si, Ge, or III–V and dimensional scaling is expected to end ~12 nm gate-length (pitch of 40 nm). We demonstrate that using alternative 2D channel materials, such as the less-explored HfS2 or ZrS2, high-drive current down to ~6 nm is, however, achievable. We also propose a dynamically doped field-effect transistor concept, that scales better than its MOSFET counterpart. Used in combination with a high-mobility material such as HfS2, it allows for keeping the stringent high-performance CMOS on current and competitive energy-delay performance, when scaling down to virtually 0 nm gate length using a single-gate architecture and an ultra-compact design (pitch of 22 nm). The dynamically doped field-effect transistor further addresses the grand-challenge of doping in ultra-scaled devices and 2D materials in particular.

Fig: Switching energy vs delay (EDP) of high-performance MOSFET and D2-FET inverters. EDP of 1ML-HfS2 high-performance inverter cells, at various VDD (0.4 V to 0.7 V), made of L = 5 nm and L = 3 nm stacked DG MOSFETs (5 ribbons/device) and L = 0 nm and L = nm stacked SG-D2-FETs (nine ribbons/device). The EDP performance of Si HP inverter cells made of L = 12 nm stacked Si-GAA MOSFETs (tS = 5 nm, 8 wires/device) and L = 5 nm stacked Si SG-D2-FETs (tS = 3 nm, 7 ribbons/device) are also shown for comparison. The inverters are loaded with a 50 contacted-gate-pitch-long metal line (https://irds.ieee.org/editions/2018). The extrinsic capacitances of the cell layout are also included in the load capacitance. IOFF = 10 nA/μm. ΔL = 4 nm for the D2-FETs.

Acknowledgements: Part of the computing resources and services used in this work were provided by the VSC (Flemish Supercomputer Center), funded by the Research Foundation–Flanders (FWO) and the Flemish Government. The author acknowledges the support of Dr. G. Gaddemane for the DFTP e-ph coupling calculations.

Open Access: This article is licensed under a Creative Commons Attribution 4.0 International License

[paper] Analysis of 2D Transistors

Guoli Li, Zizheng Fan, Nicolas André, Member, IEEE, Yongye Xu, Ying Xia, Benjamín Iñíguez, Fellow, IEEE, Lei Liao, Senior Member, IEEE, and Denis Flandre, Senior Member, IEEE

Non-Linear Output-Conductance Function for Robust Analysis of Two-Dimensional Transistors

IEEE Electron Device Letters, 42(1), pp.94-97

DOI: 10.1109/LED.2020.3042212

Abstract: In this work, we explore the outputconductance function (G-function) to interpret the device characteristics of two-dimensional (2D) semiconductor transistors. Based on analysis of the device output conductance, the carrier mobility, and the channel as well as contact resistance are extracted. Thereafter the currentvoltage (IV) characteristics of black phosphorous (BP) and MoS2 transistors from room to low temperature are modeled and compared to experiments. The G-function model proves its reliability and accuracy in parameter extraction and IV modeling of 2D transistors, regardless of the n- or p- type, the short- or long-channel and the Schottky or Ohmic contact. Moreover, this works shows its high potential in the device modeling and further circuit design of the 2D transistors, requiring only few parameters and simulating precise IV characteristics.

G-Function Model (for Linear and Non-Linear Cases), the Rch and Rc can be calculated for both the Ohmic and Schottky contacts in the 2D transistors: 

Aknowlegement: This work was supported in part by the National Key Research and Development Program of China under Grant 2018YFA0703700; in part by the National Natural Science Foundation of China under Grant 61925403, Grant 61851403, and Grant 62004065; in part by the Hunan Natural Science Foundation under Grant 2020JJ5087; and in part by the Technology Program (Major Project) of Changsha under Grant kq1902042.

[paper] 2D Charge Density Wave Phases

Machine-Intelligence-Driven High-Throughput Prediction of 2D Charge Density Wave Phases

Arnab Kabiraj and Santanu Mahapatra*

J. Phys. Chem. Lett. 2020, 11, 15, 6291–6298

Publication Date:July 22, 2020

DOI: 10.1021/acs.jpclett.0c01846

*Nano-Scale Device Research Laboratory, IISc Bangalore, India

Abstract: Charge density wave (CDW) materials are an important subclass of two-dimensional materials exhibiting significant resistivity switching with the application of external energy. However, the scarcity of such materials impedes their practical applications in nanoelectronics. Here we combine a first-principles-based structure-searching technique and unsupervised machine learning to develop a fully automated high-throughput computational framework, which identifies CDW phases from a unit cell with inherited Kohn anomaly. The proposed methodology not only rediscovers the known CDW phases but also predicts a host of easily exfoliable CDW materials (30 materials and 114 phases) along with associated electronic structures. Among many promising candidates, we pay special attention to ZrTiSe4 and conduct a comprehensive analysis to gain insight into the Fermi surface nesting, which causes significant semiconducting gap opening in its CDW phase. Our findings could provide useful guidelines for experimentalists.

Fig: Top view of TaSe₂-H 3×3_ɸ-1.

[paper] Analogue 2D Semiconductor Electronics

Analogue two-dimensional semiconductor electronics

Dmitry K. Polyushkin¹, Stefan Wachter¹, Lukas Mennel¹, Matthias Paur¹, Maksym Paliy², Giuseppe Iannaccone², Gianluca Fiori², Daniel Neumaier^3,4, Barbara Canto^3,4

and Thomas Mueller¹ 

Nat Electron 3, 486–491 (2020)

DOI: 10.1038/s41928-020-0460-6

¹Vienna University of Technology, Institute of Photonics, Vienna, Austria. 
²Dipartimento di Ingegneria dell’Informazione, Università di Pisa, Pisa, Italy.
³AMO GmbH, Aachen, Germany. 

⁴Bergische Universität Wuppertal, Wuppertal, Germany

Abstract: Digital electronics are ubiquitous in the modern world, but analogue electronics also play a crucial role in many devices and applications. Analogue circuits are typically manufactured using silicon as the active material. However, the desire for improved performance, new devices and flexible integration has—as for their digital counterparts—led to research into alternative materials, including the use of two-dimensional (2D) materials. Here, we show that operational amplifiers—a basic building block of analogue electronics—can be created using the 2D semiconductor molybdenum disulfide (MoS2) as the active material. The device is capable of stable operation with good performance, and we demonstrate its use in feedback circuits including inverting amplifiers, integrators, log amplifiers and transimpedance amplifiers. We also show that our 2D platform can be used to monolithically integrate an analogue signal preconditioning circuit with a MoS2 photodetector.

Fig: a) Schematic of the back-gated transistor architecture; 

b) Transfer characteristics of a typical transistor on the chip (W/L = 4); 

c) View of a single OPA showing the pinout and transistor labelling

Circuit design and modelling: Because a complete model of back-gated 2D semiconductor FETs is still not readily available, we fitted the experimental results with an Enz–Krummenacher– Vittoz (EKV) model in both, the subthreshold and inversion, regimes. All the transistors operate in the inversion regime, we used the inversion model to simulate the OPA, obtaining a nominal low-frequency Atot gain value.

Acknowledgements: We thank A.J. Molina-Mendoza for technical assistance and N. Schaefer and J.A. Garrido for providing a polyimide substrate. We acknowledge financial support by the European Union (grant agreements 785219 Graphene Flagship, 796388 ECOMAT and 828901 ORIGENAL), the Austrian Science Fund FWF (START Y 539-N16) and the Italian MIUR (FIVE 2D).

TSMC: All the Processes, All the Fabs

TSMC Technology Symposium: All the Processes, All the Fabs

by Paul McLellan at breakfast-bytes

27 Aug 2020

TSMC has new transistor structure (nanosheet) and new materials such as high mobility channel, 2D, carbon nanotube (CNT). TSMC has already demonstrated at 32Mb nanosheet SRAM fully-functional at 0.46V. It has also identified promising 2D materials such as MoS₂ (molybdenum disulfide). At IEDM last year, they disclosed the first BEOL CNT power-gating device integrated with silicon-based CMOS.

Scaling continues with EUV advances with the current generation of scanners. They are also working with ASML (the only supplier of EUV equipment) on High-NA EUV [read more...]

[paper] Native High-k Oxides for 2D Transistors

Yury Yu. Illarionov^1,2, Theresia Knobloch¹ and Tibor Grasser¹

Native high-k oxides for 2D transistors

Nature Electronics vol. 3, pp 442–443 (2020)

Published online: 05 August 2020

DOI: 10.1038/s41928-020-0464-2

¹Institute for Microelectronics, TU Wien, Vienna, Austria
²Ioffe Physical-Technical Institute, St Petersburg, Russia

Abstract: The two-dimensional semiconductor Bi₂O₂Se can be oxidized to create an atomically thin layer of Bi₂SeO₅ that can be used as the insulator in scaled field-effect transistors.

Fig.: Development of FETs with Bi₂O₂Se channels and native Bi₂SeO₅ insulators. a.) Step-by-step oxidation of multilayer Bi₂O₂Se towards Bi₂SeO₅ and the crystal structure of the two materials. b.) Cross-sectional scanning transmission electron microscopy image confirming the atomically sharp interface. c.) Schematic of the top-gated devices fabricated with a native gate oxide. d.) Gate transfer characteristics of the devices with a 4.6-nm-thick Bi₂SeO₅ layer (EOT below 1 nm)

[paper] An ambipolar homojunction with options

Yanqing Wu

An ambipolar homojunction with options

Nat Electron (2020)

Published 13 July 2020

DOI: 10.1038/s41928-020-0447-3

Circuits capable of reconfigurable logic and neuromorphic functions can be created by exploiting the electronic tunability of two-dimensional tungsten diselenide homojunctions.

Fig: Reconfigurable ambipolar WSe2 homojunction devices and circuits. a, Schematic of a WSe2 homojunction device that consists of two polarity-control embedded gates. b, Using two of these devices, a reconfigurable circuit cell can be created (top) that has a multifunctionality controlled through combinations of gate voltage and drain voltage. The circuit has three input terminals, two of which connect to the polarity gate of one of the devices and the drain of the other device. Using different combinations of the three inputs, seven different Boolean functions can be achieved, including pass, inverter, two-input OR, AND, and borrow-out, as listed in the truth table (bottom). Vds, drain–source voltage; VgA and VgB, gate bias for partial gates A and B, respectively; Vin1, Vin2 and Vin3, input voltages for input terminals 1, 2 and 3, respectively; M1 and M2, homojunction devices 1 and 2, respectively; Vout, output voltage; A, B and C represent logic states of either ‘0’ or ‘1’.

MicroTec: Semiconductor Process and Device Simulator

Software Package for 2D Process and Device Simulation

Version 4.0 for Windows

User’s Manual

Publisher: Siborg Systems Inc

Editor: Michael S. Obrecht

MicroTec allows 2D silicon process modeling including implantation, diffusion and oxidation and 2D steady-state semiconductor device simulation like MOSFET, DMOS, JFET, BJT, IGBT, Schottky, photosensitive devices etc. Although MicroTec is significantly simplified compared to widely available commercial simulators, it nevertheless is a very powerful modeling tool for industrial semiconductor process/device design. In many instances MicroTec outperforms existing commercial tools and it is remarkably robust and easy-to-use.

FIG: MicroTec SibGraf GUI windows

Mini-Colloquium (MQ) on Nanoelectronics

AGENDA
DATE: Saturday Aug. 26, 2016

VENUE: IIT Kanpur L16

This Mini-Colloquium (MQ) on Nanoelectronics is being hosted by the IEEE Electron Device Society UP Chapter in collaboration with the Department of Electrical Engineering at IIT Kanpur. Distinguished speakers from renowned universities will be presenting on wide range of topics in Nanoelectronics. The MQ will be organized into 1 hour talks by the speakers. The agenda would be as follows:

Time	Topic	Speaker
9:00 - 9:15	Inauguration
9:15 - 9:30	High Tea
9:30 - 10:30	Nanotransistors with 2D materials: Opportunities and Challenges	Prof. Navkanta Bhat IISc
10:30 - 11:30	Revisiting gate C-V characterization for high mobility semiconductor MOS devices	Prof. Anisul Haque East West Univ.
11:30 - 11:45	Tea
11:45 - 12:45		Prof. V. Ramgopal Rao IIT Delhi
12:45 - 14:15	Lunch
14:15 - 15:15	ASM-HEMT - First Industry Standard Compact Model for GaN HEMTs	Prof. Yogesh Singh Chauhan IIT Kanpur
15:15 - 16:15	Spintronics - Perspectives and Challenges	Prof. Brajesh Kumar Kaushik IIT Roorkee
16:15 - 16:30	Tea
16:30 - 17:30	Advanced Hetero structure based Nano Scale MOSFETs	Prof. Chandan Kumar Sarkar Jadavpur Univ.

Coordinator: Dr. Yogesh S.Chauhan IIT Kanpur, India
Website: http://www.iitk.ac.in/nanolab/MQ/index.html

INFOS 2017 in Potsdam, Germany

20th Conference on “Insulating Films on Semiconductors” 

INFOS 2017

June 27th – 30th, 2017 in Potsdam, Germany

The INFOS conference is a prestigious biennial event which brings together electrical engineers, technologists, materials scientists, device physics and chemists from Europe and around the world to debate the latest development in thin insulating film technology and identify as well as address challenges ahead in this highly diversifying field [read more...]

Conference Topics:

• High-k dielectrics, metal gate materials and SiO2 for future scaling
• Gate stack materials for high mobility substrates (Ge, SiGe, GaN, III-V)
• Stacked dielectrics for non-volatile memory (flash, nc-Si)
• Dielectrics for resistive switching memories and spin memories
• Dielectrics for DRAM and MIM
• Low-k dielectrics
• Semiconductors on insulators
• Dielectrics for 2D materials, nanowires, 2D devices and carbon-based devices
• Surface cleaning technologies
• Physics and chemistry of dielectrics and defects
• Characterization techniques for dielectrics and interfaces
• Electrical reliability, leakage and modelling
• Modelling of atomic structure of dielectrics, interfaces and thin films
• Topological insulators
• Ferroelectrics and functional oxides
• Dielectrics and thin films for TFT, amorphous or organic devices and photovoltaics
• Dielectrics for photonics and sensing

LibreCAD: Call for Your POTM Vote

The vote for April 2016 Community Choice SourceForge Project of the Month is now available, and will run until March 15, 2016 12:00 UTC. Here is one of the candidates:

LibreCAD is a fully comprehensive 2D CAD application that you can download and install for free. LibreCAD is an Open Source community-driven project: development is open to new talent and new ideas, and our software is tested and used daily by a large and devoted user community; you, too, can get involved and influence its future development. LibreCAD has GPLv2 public license – you can use it, customize it, hack it and copy it with free user support and developer support from our active worldwide community and our experienced developer team. There is a large base of satisfied LibreCAD users worldwide, and it is available in more than 20 languages and for all major operating systems, including Microsoft Windows, Mac OS X and Linux, including Debian, Ubuntu, Fedora, Mandriva, Suse, etc. 

Download LibreCAD now.