[paper] Low-Frequency Noise in Single-Layer Graphene FETs

An extended low-frequency noise compact model for single-layer graphene FETs 

including correlated mobility fluctuations effect

Nikolaos Mavredakis, Anibal Pacheco-Sanchez, and David Jiménez

https://arxiv.org/pdf/2512.08388

Departament d’Enginyeria Electrònica, Escola d’Enginyeria, Universitat Autònoma de Barcelona, Bellaterra 08193 (SP)
Departamento de Electrónica y Tecnología de Computadores, Universidad de Granada, 18011 Granada (SP)

Abstract: Correlated mobility fluctuations are considered in the physics-based carrier number fluctuation (ΔΝ) low-frequency noise (LFN) compact model of single-layer graphene field effect transistors (GFET) in the present study. Trapped charge density and Coulomb scattering coefficient ΔΝ LFN parameters are obtained after applying a parameter extraction methodology, adapted from conventional silicon technologies,to the linear ambipolar regions of GFETs. Appropriate adjustments are considered in the method according to GFETs’physical characteristics. Afterwards, Hooge mobility as well asseries resistance fluctuations LFN parameters can be extracted.The updated LFN model is validated with experimental data from various long and short-channel GFETs at an extendedrange of gate and drain bias conditions.

Fig: SID2/ID2 vs. VGS at 1 Hz for B (a) and A (b) -type RF GFETs with W=12μm and L=100nm

at VDS=60 mV. Markers: measurements, solid lines:model, dashed lines in (b): 

θint=0 V-1. Different colors represent different LFN contributions.

Acknowledgments: This work has received funding from the European Union’s Horizon2020 research and innovation programme under grant agreements NoGrapheneCore3 881603, from Ministerio de Ciencia, Innovación y Universidades under grant agreements RTI2018-097876-B-C21(MCIU/ AEI/ FEDER, UE), PID2021-127840NB-I00(MCIN/AEI/FEDER, UE), and CNS2023-143727 RECAMBIO (MCIN/AEI/ 10.13039 /501100011033). 

This work is also supported by the European Union Next Generation EU/PRTR research project.

[paper] Benchmarks for SPICE AI/ML Modeling

Colin C. McAndrew, Andries J. Scholten, Kiran K. Gullapalli, Yogesh Chauhan, and Kejun Xia

Benchmarks for SPICE Modeling and Parameter Extraction Based on AI/ML

IEEE Transactions on Electron Devices (2025)

DOI: 10.1109/TED.2025.3537952

1 Computer Engineering, Iowa State University, (USA)
2 NXP Semiconductors N.V., Eindhoven (NL)
3 NXP Semiconductors N.V., Austin (USA)
4 IIT Kanpur, (IN)
5 TSMC, Hsinchu (TW)

Abstract: Over the past decades, the number of submitted articles that use numerical approaches for SPICE models or for characterization (extraction) of parameters of existing SPICE models has grown significantly. Many of those articles rely on synthetic data, generated either from technology computer-aided design (TCAD) or from physical SPICE model simulations; most do not model/fit measured data. Furthermore, those articles do not evaluate the physical correctness, smoothness/monotonicity, or asymptotic correctness of the approach they propose. That is sufficient for initial evaluation of proposed techniques. However, it does not prove that they are “industrial strength.” This article presents benchmarks/guidelines for the proposed artificial intelligence (AI)/machine learning (ML) SPICE modeling and characterization techniques to try to help them become practical and useful.

TAB: CHECKLIST FOR MODELS

Capability	Existing State-of-the-Art	Proposed AI/ML Approach	Best Prior AI/ML Approach
obeys the laws of thermodynamics	✓	?	?
accurate DC modeling for all terminal currents, on relevant log/linear scale	✓	?	?
accurate capacitance/charge modeling	✓	?	?
models DC and capacitance interaction where relevant	✓	?	?
accurate modeling of high-frequency/non-quasi-static effects where relevant	✓	?	?
works for large-signal transient simulation, including delay effects	✓	?	?
accurate noise modeling	✓	?	?
has full geometry dependence	✓	?	?
has complete temperature dependence	✓	?	?
models all necessary LDEs	✓	?	?
behaves “well” for unreasonable geometry or temperature or bias	✓	?	?
exhibits physical monotonicity over bias, geometry, and temperature	✓	?	?
is smooth (ideally C∞-continuous)	✓	?	?
exhibits relevant physical symmetries (currents, charges, their derivatives)	✓	?	?
exhibits asymptotic correctness over geometry, temperature, and bias	✓	?	?
includes modeling of electrothermal effects (with frequency dependence)	✓	?	?
includes, or enables, modeling of global and local statistical variation	✓	?	?
includes, or enables, modeling of aging	✓	?	?
enables modeling of parasitics for different layouts	✓	?	?
is verified to converge reliably in at least one circuit simulator	✓	?	?

[paper] Rapid MOSFET Threshold Voltage Testing

Michael H. Herman; Trenton T. Nguyen; Ken Wong; Jeff Johnson; Ben Morris

Rapid MOSFET Threshold Voltage Testing

for High Throughput Semiconductor Process Monitoring

2024 IEEE 36th International Conference on Microelectronic Test Structures (ICMTS)

Edinburgh, United Kingdom, 2024, pp. 1-6

doi : 10.1109/ICMTS59902.2024.10520252

* Parametric Test Group, Advantest America, San Jose, CA 95134 United States

Abstract : We describe a method for rapid MOSFET threshold voltage (Vt) measurement. Multiple spot Ids measurements are compared to stored reference data. Each spot measurement yields an independent Vt estimate, and these enable quality metric calculation. A Vt and quality metric can be measured within 7 msec, using two spot measurements. The method permits parallel MOS testing.

FIG : Reference Ids-Vgs Curve with Gm curveB2Q8 device 2N7002 NMOS Transistor
at Vds = 0.05 Gm(max) 0.02272 at Vgs 2.25V; Extrap tangent line at 1.8665V

[paper] Sub-THz HICUM for SiGe HBTs

Soumya Ranjan Panda, Thomas Zimmer, Anjan Chakravorty, Nicolas Derrier

and Sebastien Fregonese

Exploring Compact Modeling of SiGe HBTs in Sub-THz Range With HICUM

in IEEE TED, DOI: 10.1109/TED.2023.3321017.

IMS laboratory, CNRS, University of Bordeaux (F)
Department of Electrical Engineering, IIT Madras (IN)
STMicroelectronics, 38920 Crolles (F)

Abstract : This study delves deeper into the high frequency (HF) behavior of state-of-the-art sub-THz silicon germanium heterojunction bipolar transistors (SiGe HBTs) fabricated with 55 nm BiCMOS process technology from STM. Using measurement data, calibrated TCAD simulations, and compact model simulations, we present a comprehensive methodology for extracting several HF parameters (related to parasitic capacitance partitioning and nonquasi-static effects) of the industry standard model, HICUM. The parameter extraction strategies involve thorough physics-based investigation and sensitivity analysis. The latter allowed us to precisely evaluate the effects of parameter variations on frequency dependent characteristics. The accuracy of the finally deployed model is tested by comparing the model simulation with measured small-signal two-port parameters of SiGe HBTs up to 330 GHz.

FIG: a.)  TEM image of the SiGe HBT device; b.) 2D TCAD structure simulation; c.) Large signal equivalent circuit of HICUM L2 compact model; d.) and e.) adjunct networks for vertical NQS effects

Acknowledgment: The authors would like to acknowledge Dider Celi, STM, for valuable discussion about the compact modeling of heterojunction bipolar transistors (HBTs), and they also like to thank STM for providing the silicon wafers. This work was supported by NANO2022 Important Project of Common European Interest Project (IPCEI), and SHIFT Grant ID 101096256.

[paper] Automatic Parameter Extraction of MOSFET Compact Models

Gazmend Alia^1,2, Andi Buzo¹, Hannes Maier-Flaig¹, Klaus-Willi Pieper¹, 

Linus Maurer²  and Georg Pelz¹

Automatic Parameter Extraction of MOSFET Compact Models using Differential Evolution with Population Prediction (DEpred)

6th EDTM; March 6 to 9, 2022 

   
1 Infineon Technologies AG, Munich (D)
2 Bundeswehr University Munich (D)

Abstract: Parameter extraction of MOSFET compact models with hundreds of parameters is not a trivial task. Differential evolution (DE) has proven to be very effective in such highly dimensional parameter spaces. However, DE needs a large number of iterations to converge. This paper proposes a novel method to accelerate the convergence of DE by predicting tens of iterations ahead where the population will be, based on the knowledge from the already finished iterations. The method is validated with BSIM4 and HiSIM-HV compact models, where up to 50% of the iterations are saved.

Fig: DE vs DEpred cost function for BSIM4 and HiSIM-HV models.
DEpred reaches the target 50% faster.

[paper] Automated Compact Model Parameter Extraction

Marc Huppmann∗, Klaus-Willi Pieper†, Andi Buzo†, Linus Maurer∗ and Georg Pelz†

Utilizing Differential Evolution for an Automated Compact Model Parameter Extraction

In 2021 International Semiconductor Conference (CAS), pp. 231-234. IEEE, 2021.

   
∗ Universitat der Bundeswehr Munchen, Neubiberg, Germany
† Infineon Technologies AG, Neubiberg, Germany

Abstract: Parameter extraction is a challenging task, as it searches for a solution inside a high dimensional plus non- convex space. To be able to apply well known gradient based optimizers, the problem is dissected into multiple simpler yet intertwined tasks, which yields a complex and manual labour intensive procedure. On the contrary to gradient based methods, genetic algorithms perform excellent on global search problems, which eliminates the need for such a sophisticated workflow. In this paper, a highly automated methodology is presented that is capable of replacing the standard manual extraction sequence for the BSIM MOSFET compact model. Due to its superior extreme finding behaviour, the Differential Evolution algorithm is applied in combination with a special error metric to ensure a high fitting quality, in all regions of the output and transfer curves. Repeatably good results for 20k measurement points are obtained, with a reduction of factor 10 in total fitting duration, while coincidentally consuming mostly computation instead of manual labour time.

Fig: With every iteration, the errors approach each other till

they meet in roughly one point and σi terminates the fitting.

[paper] Parameter Extraction Approaches for Memristor Models

Dmitry Alexeevich Zhevnenko^1,2, Fedor Pavlovich Meshchaninov^1,2, Vladislav Sergeevich Kozhevnikov^1,2, Evgeniy Sergeevich Shamin^1,2, Oleg Alexandrovich Telminov^1,2, and Evgeniy Sergeevich Gornev^1,2

Research and Development of Parameter Extraction Approaches for Memristor Models

Micromachines 2021, 12, 1220. 

DOI: 10.3390/mi12101220

   
1 Moscow Institute of Physics and Technology, Moscow, Russia;
2 JSС MERI, Zelenograd, Russia

Abstract: Memristors are among the most promising devices for building neural processors and non-volatile memory. One circuit design stage involves modeling, which includes the option of memristor models. The most common approach is the use of compact models, the accuracy of which is often determined by the accuracy of their parameter extraction from experiment results. In this paper, a review of existing extraction methods was performed and new parameter extraction algorithms for an adaptive compact model were proposed. The effectiveness of the developed methods was confirmed for the volt-ampere characteristic of a memristor with a vertical structure: TiN/HfxAl1-xOy/HfO2/TiN.

Fig: Model VACs with different numbers of inhomogeneities: 

(a) four inhomogeneities; (b) no inhomogeneities.

Acknowledgments: This research was funded by the Ministry of Science and Higher Education of the Russian  Federation, grant number 075-15-2020-791. Authors thank the Institute of Microelectronics Technology and High-Purity Materials RAS for access to experimental data on the study of graphene oxide memristor switching cycles.

[paper] Parameter Extraction of Power MOSFET Models

Michihiro Shintani, Aoi Ueda and Takashi Sato

Accelerating Parameter Extraction of Power MOSFET Models Using Automatic Differentiation

IEEE Transactions on Power Electronics (2021)

DOI:  10.1109/TPEL.2021.3118057

 
Graduate School of Science and Technology, Nara Institute of Science and Technology, Ikoma (J)

Graduate School of Informatics, Kyoto University (J)
 

Abstract: The extraction of the model parameters is as im- portant as the development of compact model itself because simulation accuracy is fully determined by the accuracy of the pa- rameters used. This study proposes an efficient model-parameter extraction method for compact models of power MOSFETs. The proposed method employs automatic differentiation (AD), which is extensively used for training artificial neural networks. In the proposed AD-based parameter extraction, gradient of all the model parameters is analytically calculated by forming a graph that facilitates the backward propagation of errors. Based on the calculated gradient, computationally intensive numerical differentiation is eliminated and the model parameters are efficiently optimized. Experiments are conducted to fit current and capacitance characteristics of commercially available silicon carbide MOSFET using power MOSFET models having 13 model parameters. Results demonstrated that the proposed method could successfully derive the model parameters 3.50× faster than a conventional numerical-differentiation method while achieving the equal accuracy.

Fig: Backward propagation mode. The dashed arrows indicate the path from E to SCALE.

The propagated values on the path in the backward propagation are highlighted

Acknowledgment: This work was partially supported by JST-OPERA Program Grant Number JPMJOP1841, Japan. The part of this work is also supported by JSPS KAKENHI Grant 20H04156 and 20K21793.

[Photos] MOS-AK LADEC Mexico April 18, 2021

Arbeitskreis Modellierung von Systemen und Parameterextraktion

Modeling of Systems and Parameter Extraction Working Group

MOS-AK LAEDC Workshop

(virtual/online) April 18, 2021

Together with local Host and LAEDC Organizers as well as all the Extended MOS-AK TPC Committee, we have organized the 3rd subsequent MOS-AK/LAEDC workshop which was the Virtual/Online event. There are a couple of the event photos:

MOS-AK Session 1 (APR.18) begun: 8:00am Mexico time zone (GMT-5)

T_1 FOSSEE eSIM: An open source CAD software for circuit simulation

Kannan Moudgalya

IIT Bombay (IN)

T_2 Memristor modeling

Arturo Sarmiento

INAOE (MX)

T_3 Modeling Issues for CMOS RF ICs

Roberto Murphy, Jose Valdes and Reydezel Torres

INAOE (MX)

T_4 Improving Time-Dependent Gate Breakdown of GaN HEMTs with p-type Gate

E. Sangiorgi, A. Tallarico, N. Posthuma, S. Decoutere, C. Fiegna

Universita di Bologna

MOS-AK Session 2 (APR.18) begun: 1:00pm Mexico time zone (GMT-5)

T_5 Compact Models of SiC and GaN Power Devices

Alan Mantooth, Arman Ur Rashid, Md Maksudul Hossain

University of Arkansas (US)

T_6 New analytical model for AOSTFTs

Antonio Cerdeira

CINVESTAV-IPN, Mexico City (MX)

T_7 On the Parameter Extraction of Thin-Film Transistors in Weak-Conduction

Adelmo Ortiz-Conde

Solid State Electronics Laboratory, Simon Bolivar University, Caracas (VE)

End of MOS-AK Workshop
Group Photo

[paper] Modeling Power GaN-HEMTs in SPICE

Utkarsh Jadli, Faisal Mohd-Yasin, Hamid Amini Moghadam, Peyush Pande*, Mayank Chaturvedi and Sima Dimitrijev

Modeling Power GaN-HEMTs Using Standard MOSFET Equations and Parameters in SPICE

Electronics 2021, 10, 130

DOI: 10.3390/electronics10020130

Queensland Micro- and Nanotechnology Centre, Griffith University, Brisbane, QLD 4111, Australia;

*Electronics Department, Graphic Era (Deemed to Be University), Dehradun, Uttarakhand 248002, India;

Abstract: The device library in the standard circuit simulator (SPICE) lacks a gallium nitride based high-electron-mobility-transistor (GaN-HEMT) model, required for the design and verification of power-electronic circuits. This paper shows that GaN-HEMTs can be modeled by selected equations from the standard MOSFET LEVEL3 model in SPICE. A method is proposed for the extraction of SPICE parameters in these equations. The selected equations and the proposed parameter-extraction method are verified with measured static and dynamic characteristics of commercial GaN-HEMTs. Furthermore, a double pulse test is performed in LTSpice and compared to its manufacturer model to demonstrate the effectiveness of the MOSFET LEVEL3 model. The advantage of the proposed approach to use the MOSFET LEVEL3 model, in comparison to the alternative behavioral-based model provided by some manufacturers, is that users can apply the proposed method to adjust the parameters of the MOSFET LEVEL3 model for the case of manufacturers who do not provide SPICE models for their HEMTs.

Fig: Internal cross-sectional structure of GaN-HEMT

Acknowledgments: The authors would like to acknowledge the Innovative Manufacturing Co- operative Research Centre (IMCRC) for providing a PhD scholarship to the first author. We also acknowledge the School of Engineering and Built Environments (EBE) of Griffith University for funding this project. This work was performed in part at the Queensland node of the Australian National Fabrication Facility, a company established under the National Collaborative Research Infrastructure Strategy to provide nano- and micro-fabrication facilities for Australia’s researchers.

[paper] Compact Modeling of Carbon Nanotube FETs

A Compact and Robust Technique for the Modeling and Parameter Extraction 

of Carbon Nanotube Field Effect Transistors

Laura Falaschetti¹, Davide Mencarelli¹, Nicola Pelagalli¹, Paolo Crippa¹, Giorgio Biagetti¹,

Claudio Turchetti¹,George Deligeorgis², and Luca Pierantoni¹

Electronics 2020, 9(12), 2199; 

DOI: 10.3390/electronics9122199

1 Department of Information Engineering, Marche Polytechnic University, 60131 Ancona, Italy
2 Microelectronics Research Group (MRG/IESL), FORTH, Greece

Abstract: Carbon nanotubes field-effect transistors (CNTFETs) have been recently studied with great interest due to the intriguing properties of the material that, in turn, lead to remarkable properties of the charge transport of the device channel. Downstream of the full-wave simulations, the construction of equivalent device models becomes the basic step for the advanced design of high-performance CNTFET-based nanoelectronics circuits and systems. In this contribution, we introduce a strategy for deriving a compact model for a CNTFET that is based on the full-wave simulation of the 3D geometry by using the finite element method, followed by the derivation of a compact circuit model and extraction of equivalent parameters. We show examples of CNTFET simulations and extract from them the fitting parameters of the model. The aim is to achieve a fully functional description in Verilog-A language and create a model library for the SPICE-like simulator environment, in order to be used by IC designers.

Figure 2. 3D structure of CNTFET. Reprinted, with permission, from [I and II]

Aknowlwgement: This research was supported by the European Project “NANO components for electronic SMART wireless circuits and systems (NANOSMART)”, H2020—ICT-07-2018-RIA, n. 825430.

References:

[I] Deng, J.; Wong, H.P. A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including non-idealities and Its Application—Part I: Model of the Intrinsic Channel Region. IEEE Trans. Electron Devices 2007, 54, 3186–3194

[II] Deng, J.; Wong, H.P. A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including non-idealities and Its Application—Part II: Full Device Model and Circuit Performance Benchmarking. IEEE Trans. Electron Devices 2007, 54, 3195–3205 

[paper] Local Variability Evaluation on Effective Channel Length

Juan Pablo Martinez Brito, Graduate Student Member, IEEE, 

and Sergio Bampi, Senior Member, IEEE

Local Variability Evaluation on Effective Channel Length

Extracted with Shift-and-Ratio Method

IEEE TED, vol. 67, no. 11, pp. 4662-4666, Nov. 2020

doi: 10.1109/TED.2020.3017178

Abstract: In this study, the local variation of the effective channel reduction parameter (ΔL=Lm−Leff) of a MOSFET is extracted by means of the traditional shift-and-ratio (SAR) method. ΔL is then correlated with the threshold voltage difference (ΔVTH) between the device under test (DUT) and the reference device. It is demonstrated that there exists an optimal VG range for extracting reliable values of L through the SAR method. Statistical data analysis shows that for R≈ (Llong/Lshort)≈25, better results are achieved since the value of σ(ΔL) varies typically as the reciprocal 1/√ W. The test structure used in this work is a Kelvin-based 2-D addressable MOSFET matrix implemented in 180-nm bulk CMOS technology. The sample space is of 2304 devices divided into nine subgroups of 256 same size closely placed nMOSFETs.

Fig: (a) Full circuit micrograph (b) MOSFET Matrix structure (c) Zoomed-in view at DUTs 

Acknowledgment: The authors would like to thank and acknowledge the Brazilian public company CEITEC S.A. Semiconductors for the measurement infrastructure, the CAD Support Center (NSCAD) at Federal University of Rio Grande do Sul (UFRGS) for electronic design automation (EDA) support, and Silterra Inc. for the silicon prototyping services.

[paper] Parameter Extraction Technique for IGBT Compact Model

N.V. Bharadwaj¹, Dr. P. Chandrasekhar² and Dr. M. Sivakumar³

A Consecutive Parameter Extraction Technique for IGBT Compact Model

ICMM-2019; AIP Conf. Proc. 2269, 030031-1–030031-5;

DOI: 10.1063/5.0019484

¹Geethanjali College of Enegineering and Technology, Hyderabad, 501301, India 

²MGIT, Hyerabad, 500075, India 

³Gudlavalleru Engineering College, Gudlavalleru , 521356, India

Abstract: A consecutive parameter extraction technique describes the fitting target related parameters for Insulated-gate bipolar transistor (IGBT) model. The IGBT model has been represented by a couple of simplified equivalent circuits. Using simulated data for a trench-type IGBT as reference the performance of compact model IGBT is compared to an IGBT macro model. Due to physics based modeling, parameter extraction with the compact model is fast. With very less extraction effort, the compact model fits the dc current and capacitance characteristics accurately.

FIG: The IGBT cell structure with cell pitch = 4μm and trench gate depth = 3μm

[paper] GCC Method for Determining MOSFET VTH

Matthias Bucher¹, Nikolaos Makris¹, Loukas Chevas¹

Generalized Constant Current Method for Determining MOSFET Threshold Voltage

arXiv:2008.00576v1 (2 Aug 202) 

has been submitted to the IEEE for possible publication

¹ School of Electrical and Computer Engineering, Technical University of Crete

Abstract: A novel method for extracting threshold voltage (VTH) and substrate effect parameters of MOSFETs with constant current bias at all levels of inversion is presented. This generalized constant-current (GCC) method exploits the charge-based model of MOSFETs to extract threshold voltage and other substrate-effect related parameters. The method is applicable over a wide range of current throughout weak and moderate inversion and to some extent in strong inversion. This method is particularly useful when applied for MOSFETs presenting edge conduction effect (subthreshold hump) in CMOS processes using Shallow Trench Isolation (STI).

Fig:  Application of the GCC method in presence of edge conduction phenomenon in STI MOSFETs. A constant current is applied to determine pinchoff voltage for the center transistor in moderate inversion at IC=2. To characterize the edge transistor, imposing a current criterion IC=1E−4 corresponds to ICe≈0.02. Pinchoff voltage (VP) and slope factor n characteristics illustrate the determination of parameters for center and edge transistors.

Acknowledgment: This work was partly supported under Project INNOVATION-EL-Crete

(MIS 5002772).

Conference Paper Reached 500 Reads

Wladek 

Wladek Grabinski, Daniel Tomaszewski, Farzan Jazaeri, Anurag Mangla, Jean-Michel Sallese, Maria-Anna Chalkiadaki, Antonios Bazigos, and Matthias Bucher

FOSS EKV 2.6 Parameter Extractor

22nd International MIXDES Conference, pp. 181-186 (2015)

Abstract: The design of advanced integrated circuits (IC) in particular for low power analog and radio-frequency (RF) application becomes more complex as the device level modeling confronting challenges in micro- and nano-meter CMOS processes. As present CMOS technologies continue geometry scaling the designers can benefit using dedicated SPICE MOSFET models and apply specific analog design methodologies. The EKV was developed especially to meet altogether the analog/RF design requirements. This paper describes a basic set of the DC parameter extraction steps for the EKV 2.6 model. The free open source software (FOSS) Profile2D tool was used to illustrate an accurate EKV 2.6 DC extraction strategy. 

conference FOSS paper reached 300 reads

D. Tomaszewski, G. Głuszko, M. Brinson, V. Kuznetsov and W. Grabinski, "FOSS as an efficient tool for extraction of MOSFET compact model parameters," 2016 MIXDES - 23rd International Conference Mixed Design of Integrated Circuits and Systems, Lodz, 2016, pp. 68-73.

Abstract - A GNU Octave - based application for device-level compact model evaluation and parameter extraction has been developed. The applications main features are as follows: experimental I–V data importing, generating input data for different circuit simulation programs, running the simulation program to calculate I–V characteristics of the specified models, calculating model misfit and its sensitivity to selected parameter variation, and the comparison of experimental and simulated characteristics. Measured I–V data stored by different measurement systems are accepted. Circuit simulations may be done with Ngspice, Qucs and LTSpiceIV © . Selected aspects of the application are presented and discussed.

conference paper reached 700 reads

M. Bucher, A. Bazigos and W. Grabinski, "Determining MOSFET Parameters in Moderate Inversion," 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems, Krakow, 2007, pp. 1-4.

Abstract: Deep submicron CMOS technology scaling leads to reduced strong inversion voltage range due to non-scalability of threshold voltage, while supply voltage is reduced. Moderate inversion operation therefore becomes increasingly important. In this paper, a new method of determining MOSFET parameters in moderate inversion is presented. Model parameters are determined using a constant current bias technique, where the biasing current is estimated from the transconductance-to-current ratio. This technique is largely insensitive to mobility effects and series resistance. Statistical data measured on 40 dies a 0.25 um standard CMOS technology are used for the illustration of this method.

BSIM3v3 to EKV2.6 Model Parameter Extraction

BSIM3v3 to EKV2.6 Model Parameter Extraction and Optimisation

using LM Algorithm on 0.18um Technology node

Kirmender Singh and Piyush Jain

Int. Journal of Electronics and Telecommunications 2018 Vol.64 No.1 pp.5-11

Abstract: The industry standard BSIM3v3 and BSIM4.0 have been replaced by BSIM6.0 compact MOSFET model for deep submicron technology node. The BSIM6.0 is next generation, defacto industry standard model for bulk MOSFET. This model is charge based which is continuous from weak to strong inversion of operation. The core of analytical and physical BSIM6 model[3] is charge, with drain current equation expressed in form of source (qs) and drain charge (qd). This model has all its governing equations continuous and can be used to develop design methodology using IC based approach. But its method of computing qs and qd is complicated which is different from Vittoz traditional charge calculation method. The continuous interpolation equation of drain current as adopted by EKV2.6 although is empirical but its compact expression is preferred by analog designer to get intuitive design guidance. BSIM6 is a combined effort by BSIM and EKV modeling groups based on charge based continuous equations. Although EKV2.6 model is not valid for deep submicron process as it only includes submicron short channel effects like velocity saturation (VS), vertical field mobility reduction (VFMR), Drain induced barrier lowering (DIBL), channel length modulation (CLM) etc. But it still offers some benefits to have first cut design methodology because of its much simplified analytical equations. The inversion coefficient (IC) has found extensive acceptance in designer community as it offers enhanced design elegance in EKV then more complicated BSIM model. This paper discuses first step in analog design process by extracted core EKV2.6 intrinsic model parameters from industry standard BSIM3v3 model on 0.18µ technology node. The 0.18µ technology is chosen as it is still more common technology node in analog circuit design. The model parameters are extracted for different bins and optimisation is done using nonlinear optimisation LM algorithm. The optimised EKV2.6 parameters are validated with currentvoltage(I-V), intrinsic voltage gain (Avi) and Early voltage circuit parameter (VA) with BSIM3v3 model [read more...]

Flow-chart of BSIM to EKV conversion steps
(source:
D. Stefanovic and M. Kayal “Structured Analog CMOS Design" Springer Publications, 2008)

[paper] Accurate diode behavioral model with reverse recovery

Stanislav Banáš^a,b, Jan Divína^b, Josef Dobeš^b, Václav Paňko^a

^aON Semiconductor, SCG Czech Design Center, Department of Design System Technology, 1. maje 2594, 756 61 Roznov pod Radhostem, Czech Republic

^bCzech Technical University in Prague, Faculty of Electrical Engineering, Department of Radioelectronics, Technicka 2, 166 27 Prague 6, Czech Republic

Solid-State Electronics

Volume 139, January 2018, Pages 31–38

https://doi.org/10.1016/j.sse.2017.10.034

Highlights:

• The complex robust time and area scalable Verilog-A model of diode containing reverse recovery effect has been developed.
• Due to implemented reverse recovery effect the model is useful especially for high-speed or high-voltage power devices.
• The model can be used as stand-alone 2-terminal diode or as a parasitic p-n junction of more complex lumped macro-model.
• Two methods of model parameter extraction or model validation have been demonstrated.

ABSTRACT: This paper deals with the comprehensive behavioral model of p-n junction diode containing reverse recovery effect, applicable to all standard SPICE simulators supporting Verilog-A language. The model has been successfully used in several production designs, which require its full complexity, robustness and set of tuning parameters comparable with standard compact SPICE diode model. The model is like standard compact model scalable with area and temperature and can be used as a stand-alone diode or as a part of more complex device macro-model, e.g. LDMOS, JFET, bipolar transistor. The paper briefly presents the state of the art followed by the chapter describing the model development and achieved solutions. During precise model verification some of them were found non-robust or poorly converging and replaced by more robust solutions, demonstrated in the paper. The measurement results of different technologies and different devices compared with a simulation using the new behavioral model are presented as the model validation. The comparison of model validation in time and frequency domains demonstrates that the implemented reverse recovery effect with correctly extracted parameters improves the model simulation results not only in switching from ON to OFF state, which is often published, but also its impedance/admittance frequency dependency in GHz range. Finally the model parameter extraction and the comparison with SPICE compact models containing reverse recovery effect is presented [read more...]

FIG: Solving the recursive calculation of reverse recovery charge

levmar : Levenberg-Marquardt nonlinear least squares algorithms in C/C++

Introduction page: <http://users.ics.forth.gr/~lourakis/levmar/> 

The site provides GPL native ANSI C implementations of the Levenberg-Marquardt optimization algorithm, usable also from C++, Matlab, Perl, Python, Haskell and Tcl and explains their use. Both unconstrained and constrained (under linear equations, inequality and box constraints) Levenberg-Marquardt variants are included. The Levenberg-Marquardt (LM) algorithm is an iterative technique that finds a local minimum of a function that is expressed as the sum of squares of nonlinear functions. It has become a standard technique for nonlinear least-squares problems and can be thought of as a combination of steepest descent and the Gauss-Newton method. When the current solution is far from the correct one, the algorithm behaves like a steepest descent method: slow, but guaranteed to converge. When the current solution is close to the correct solution, it becomes a Gauss-Newton method.

Interfaces for using levmar from high-level programming environments & languages such as Matlab, Perl Python, Haskell and Tcl are also available; please refer to the FAQ for more details.