[paper] ACM3 Compact MOSFET Model

Deni Germano Alves Neto; Márcio Cherem Schneider; Manuel J. Barragan; 

Sylvain Bourdel; Carlos Galup-Montoro,

ACM3 - An Advanced Compact MOSFET Model for Analog IC Design and Simulation

in IEEE Access, DOI: 10.1109/ACCESS.2026.3742180

1.) Federal University of Santa Catarina, 88040-900 Florianópolis (BR)

2.) Univ. Grenoble Alpes, CNRS, Grenoble INP, TIMA F-38000 Grenoble (F)

Abstract: This paper presents ACM3, an advanced compact MOSFET model that extends the designoriented ACM2 formulation by introducing gate-voltage dependencies for the slope factor n, the draininduced barrier lowering (DIBL) coefficient σ, and inversion charge dependence for the specific current IS. ACM3 preserves a single-piece, charge-based description of the drain current, valid from weak to strong inversion and from the linear to the saturation regions, while relying on an efficient analytical approximation of the Lambert W -function suitable for Verilog-A implementation. A robust yet straightforward parameterextraction flow is proposed, in which all eight DC parameters (VT 0, IS0, Φ, γ, θ, σWI , σSI and ζ) are obtained directly from ID–VGB and ID–VDS curves through a differential evolution (DE) algorithm that minimizes the root-mean-square percentage error between the reference and the modeled drain current. A distinctive feature of this flow is that the reference curves may originate either from silicon measurements or from another compact model, making the extraction equally applicable to measured and simulated data. At the device level, the parameters are extracted from silicon measurements of an open-source 130 nm BiCMOS technology, yielding agreement with the measured data for both short- and long-channel transistors across all regions of operation. At the circuit level, ACM3 is validated through simulations of a common-source amplifier, a self-biased current source, and a CMOS latch in a 180 nm CMOS technology, where the ACM3 parameters are extracted from BSIM4-generated characteristics and the results are compared against the foundry BSIM4 model. Representative process, voltage, and temperature (PVT) robustness is also evaluated against BSIM4. The ACM3 model has been implemented in Verilog-A and integrated into open-source circuit simulators, via OpenVAF, enabling accurate and intuitive analog IC design within fully open design flows.

TAB: Comparison of ACM3 with representative industrial 

and design-oriented compact MOSFET models

Aknowlegements: This study was financed in part by the Coordenação de Aperfeiçoamento de Pessoal de Nível Superior, (BRAZIL), Conselho Nacional de Desenvolvimento Científico e Tecnológico, (BRAZIL), and TIMA laboratory, Grenoble (FRANCE).

[paper] Scalable Open-Source Multi-Project SoC Architecture

Uriel Jaramillo-Toral, Susana Ortega-Cisneros, Héctor Emmanuel Muñoz-Zapata, 

Iraam Antonio López-Salas 

Silicluster v2: A Scalable Open-Source Multi-Project SoC Architecture 

in Sky130 CMOS Enabling High-Density Modular Integration

in IEEE Access, vol. 14, pp. 82876-82889, 2026

doi: 10.1109/ACCESS.2026.3698053. 

* CINVESTAV, Guadalajara, Jalisco, Mexico

* Tecnológico Nacional de México, ITA, Aguascalientes, Mexico

Abstract: The increasing availability of open-source electronic design automation (EDA) tools and publicly accessible process design kits (PDKs) has expanded access to integrated circuit (IC) development; however, scalable system-level integration frameworks capable of supporting heterogeneous digital, analog, and mixed-signal systems remain limited. This paper presents Silicluster Version 2 (Silicluster v2), a hierarchical and scalable multi-project system-on-chip (SoC) architecture implemented in 130 nm complementary metal-oxide-semiconductor (CMOS) technology using a fully open-source register-transfer-level (RTL) to Graphic Data System II (GDSII) layout design flow. The proposed architecture enables the structured integration of up to 256 independent digital, analog, and mixed-signal modules within a single chip while preserving modular isolation, reusability, and routing efficiency. In contrast to its previous digital-focused implementation, Silicluster v2 incorporates infrastructure supporting transistor-level analog layout, parasitic-aware mixed-domain co-simulation using Simulation Program with Integrated Circuit Emphasis (SPICE), and integration of synthesized standard-cell netlists alongside custom transistor-level blocks. A hierarchical multiplexed interconnection scheme and centralized clock-distribution strategy mitigate fanout, congestion, and timing-closure challenges inherent to high-density modular integration. The complete system is validated through design rule checking (DRC), layout-versus-schematic (LVS) verification, parasitic extraction, and static timing analysis (STA) at 10 MHz, targeting 1.8 V digital operation and 3.3 V analog operation. The results demonstrate the feasibility of constructing complex heterogeneous integrated circuits using exclusively open-source methodologies, establishing Silicluster v2 as a validated reference architecture for collaborative silicon integration and scalable multi-project chip development.

Fig: Graphical representation of the Silicluster v2 integration process within Caravel. The original user area is replaced by the Silicluster v2 wrapper, enabling high-density modular integration and resulting in a complete MPW-ready SoC while preserving the RISC-V subsystem and padframe infrastructure.

Acknowledgment: The authors gratefully recognize ChipFoundry for enabling the fabrication of Silicluster v2 through the MPW Program. Their support made the physical realization of the proposed architecture possible. They also acknowledge Toyohashi University of Technology (TUT) for its early-stage mentorship in analog design methodologies and the Centro de Investigación y de Estudios Avanzados del IPN, Unidad Guadalajara (CINVESTAV), for providing the academic environment and institutional framework that supported the development of this project.