[paper] ACM3 Compact MOSFET Model

Deni Germano Alves Neto; Márcio Cherem Schneider; Manuel J. Barragan; 

Sylvain Bourdel; Carlos Galup-Montoro,

ACM3 - An Advanced Compact MOSFET Model for Analog IC Design and Simulation

in IEEE Access, DOI: 10.1109/ACCESS.2026.3742180

1.) Federal University of Santa Catarina, 88040-900 Florianópolis (BR)

2.) Univ. Grenoble Alpes, CNRS, Grenoble INP, TIMA F-38000 Grenoble (F)

Abstract: This paper presents ACM3, an advanced compact MOSFET model that extends the designoriented ACM2 formulation by introducing gate-voltage dependencies for the slope factor n, the draininduced barrier lowering (DIBL) coefficient σ, and inversion charge dependence for the specific current IS. ACM3 preserves a single-piece, charge-based description of the drain current, valid from weak to strong inversion and from the linear to the saturation regions, while relying on an efficient analytical approximation of the Lambert W -function suitable for Verilog-A implementation. A robust yet straightforward parameterextraction flow is proposed, in which all eight DC parameters (VT 0, IS0, Φ, γ, θ, σWI , σSI and ζ) are obtained directly from ID–VGB and ID–VDS curves through a differential evolution (DE) algorithm that minimizes the root-mean-square percentage error between the reference and the modeled drain current. A distinctive feature of this flow is that the reference curves may originate either from silicon measurements or from another compact model, making the extraction equally applicable to measured and simulated data. At the device level, the parameters are extracted from silicon measurements of an open-source 130 nm BiCMOS technology, yielding agreement with the measured data for both short- and long-channel transistors across all regions of operation. At the circuit level, ACM3 is validated through simulations of a common-source amplifier, a self-biased current source, and a CMOS latch in a 180 nm CMOS technology, where the ACM3 parameters are extracted from BSIM4-generated characteristics and the results are compared against the foundry BSIM4 model. Representative process, voltage, and temperature (PVT) robustness is also evaluated against BSIM4. The ACM3 model has been implemented in Verilog-A and integrated into open-source circuit simulators, via OpenVAF, enabling accurate and intuitive analog IC design within fully open design flows.

TAB: Comparison of ACM3 with representative industrial 

and design-oriented compact MOSFET models

Aknowlegements: This study was financed in part by the Coordenação de Aperfeiçoamento de Pessoal de Nível Superior, (BRAZIL), Conselho Nacional de Desenvolvimento Científico e Tecnológico, (BRAZIL), and TIMA laboratory, Grenoble (FRANCE).

[paper] 5-DC-Parameter MOSFET Model

Deni Germano Alves Neto 1,3, Mohamedkhalil Bouchoucha 2,3, Gabriel Maranhão 1, Manuel J. Barragan 3, Márcio Cherem Schneider 1, Andreia Cathelin 2, Sylvain Bourdel 1

and Carlos Galup-Montoro 1

Design-Oriented Single-Piece 5-DC-Parameter MOSFET Model

IEEE Access; vol. 12 (2024)

DOI: 10.1109/ACCESS.2024.3417316

1 Department of Electrical and Electronics Engineering, FUSC, Florianópolis (BR)

2 STMicroelectronics, Crolles (F)

3 Univ. Grenoble Alpes, CNRS, Grenoble INP, TIMA, Grenoble (F)

Abstract: This paper presents a novel charge-based MOSFET model, denoted ACM2, including velocity saturation and drain-induced barrier lowering. Employing the proposed model, all the DC characteristics (currents and charges) and the small-signal equations can be expressed as single-piece expressions valid in all inversion (weak, moderate, and strong) regions. When applied to bulk technology, ACM2 has 5 DC parameters, and an extra parameter is included for SOI technologies to account for back gate bias. Straightforward procedures are provided for extracting the short-channel parameters associated with velocity saturation and back gate bias. Experimental results demonstrate that the DC and small-signal characteristics of the ACM2 model match the silicon measurements in bulk and SOI technologies, with typical errors of less than 20 % in the DC currents and 30 % in the transconductances. The validity of the model is further verified with two design examples. Firstly, simulations of a CMOS inverter in a 130 nm bulk technology show similar results using the PSP or ACM2 models. Then, an RF design example is provided. The ACM2 model is employed to design a 2.4GHzlow-noise-amplifier in a 28nm FD-SOI CMOS technology. Obtained results in terms of S11, S21, NF, and IIP3 are consistent with simulations using the complete UTSOI2 model provided in the technology design kit.

 

Technology	130nm		28nm
Transistor	NMOS	PMOS	NMOS	PMOS
W/L (um/um) VTO (mV)	10/0.12 490	10/0.12 -478	1/0.06 389	1/0.06 -404
Is (uA)	11.78	9.39	3.15	0.76
n	1.41	1.46	1.15	1.01
σ	0.053	0.048	0.018	0.029
ς	0.007	0.031	0.039	0.024
δ	-	-	0.079	-0.076

FIG:  Conceptual structure of the ACM2 Model and its 6-DC parameters.

Acknowledgment: The authors would like to thank the STIC-AmSud multi national cooperative scientific program for supporting this research and STMicroelectonics and the Institute for High-Performance Microelectronics (IHP) for the design kits and silicon measurements. This work was supported in part by the Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (BR); in part by the Conselho Nacional de Desenvolvimento Científico e Tecnológico, (BR); in part by the TIMA Laboratory, Grenoble (F) and in part by STMicroelectronics, Crolles, France.