[paper] Effect of doping on Al2O3/GaN MOS capacitance

B.Rrustemi^ab, C.Piotrowicz^a, M-A.Jaud^a, F.Triozon^a, W.Vandendaele^a, B.Mohamad^a, R.Gwoziecki^a, G.Ghibaudo^b

Effect of doping on Al2O3/GaN MOS capacitance

Solid-State Electronics

Vol. 194, Aug. 2022, 108356

DOI: 10.1016/j.sse.2022.108356

   
a CEA, LETI, Grenoble (Fermi)
b IMEP-LAHC Minatec, Grenoble(FR)

Abstract: This paper investigates the turning-on-voltage (VFB/VTH) of Al2O3/GaN MOS stacks with n-doped GaN, p-doped GaN and not intentionally doped (NID) GaN by exploiting capacitance measurements on large gate area test structures with systematic variation of Al2O3 thickness (tox). Measurements are compared with 1D Schrödinger-Poisson simulations including incomplete ionization model. The necessity of using a quantum description of electron density is demonstrated especially for thinner gate oxides. We found that, contrary to what is expected, p-doping below the channel barely increases the VTH and the VTH is independent of tox, even if the density of activated acceptors is demonstrated to be sufficiently high. Our results highly suggest that the negative charge induced by p-doping is compensated at the oxide level.

Fig: Al2O3/GaN MOS stacks with n-doped GaN, p-doped GaN and its CV plots

[paper] Organic Semiconductor Devices

D. Oussalah^1,2, R. Clerc², J. Baylet¹, R. Paquet¹, C. Sésé¹, C. Laugier¹, B. Racine¹

and J. Vaillant¹

On the minimum thickness of doped electron/hole transport layers 

in organic semiconductor devices 

Journal of Applied Physics 130, 125502 (2021);

DOI: 10.1063/5.0060429

  
1Université Grenoble Alpes, CEA, Leti, Grenoble 38000, France
2Université de Lyon, UJM-Saint-Etienne, CNRS, IOGS, Lab. Hubert Curien, UMR5516 St-Etienne, France

  

Abstract: Doped hole (respectively electron) transport layers [HTLs (respectively ETLs)] are commonly used in evaporated organic devices to achieve high work function hole contact (respectively low work function electron contact) in organic LEDs to inject large current, in solar cells to increase the open circuit voltage, and in photodetectors to minimize the dark current. However, optimization of the HTL thickness results from a delicate trade-off. Indeed, on the one hand, to minimize the impact of HTLs on light propagation and series resistance effects, it is commonly admitted that HTLs must be kept as thin as possible. In this work, a model, validated by drift and diffusion simulations, has shown that, depending of the doping level, a minimum thickness between 10 and 20 nm was needed to prevent the transport layer work function from degradation due to field effects. Experiments have been performed on template p-only devices featuring a single HTL of various thicknesses and doping, confirming the validity of the model. Finally, simulations have been performed on a p-i-n device featuring both HTL and ETL. These results constitute precious indications for the design of efficient evaporated organic LEDs, solar cells, or photodetectors.

Fig: Image of a top view of the 200 mm silicon wafer processed to realize TiN/STTB:F4TCNQ/ZnPc:C60/Ag devices.

[paper] A Compact Model for the Statistics of the Low-Frequency Noise of MOSFETs With Laterally Uniform Doping

M. Banaszeski da Silva, H. P. Tuinhout, A. Zegers-van Duijnhoven, G. I. Wirth and A. J. Scholten

"A Compact Model for the Statistics of the Low-Frequency Noise of MOSFETs With Laterally Uniform Doping" 

in IEEE TED, vol. 64, no. 8, pp. 3331-3336, Aug. 2017.
doi: 10.1109/TED.2017.2713301

Abstract: In this paper, we develop a compact physics-based statistical model for random telegraph noise-related low-frequency noise in bulk MOSFETS with laterally uniform doping. The proposed model is suited for modern compact device models, such as PSP, BSIM, and EKV. With our proposed model, one can calculate the expected value and the variability of the noise as a function of bias and device parameters. We validate the model through numerous experimental results from different CMOS nodes, down to 40 nm [read more...]

[paper] A Compact Model for the Statistics of the Low-Frequency Noise of MOSFETs With Laterally Uniform Doping

A Compact Model for the Statistics of the Low-Frequency Noise of MOSFETs With Laterally Uniform Doping

M. Banaszeski da Silva; H. P. Tuinhout; A. Zegers-van Duijnhoven; G. I. Wirth; A. J. Scholten;

in IEEE Transactions on Electron Devices, vol.PP, no.99, pp.1-6
doi: 10.1109/TED.2017.2713301

Abstract: In this paper, we develop a compact physics-based statistical model for random telegraph noise-related low-frequency noise in bulk MOSFETS with laterally uniform doping. The proposed model is suited for modern compact device models, such as PSP, BSIM, and EKV. With our proposed model, one can calculate the expected value and the variability of the noise as a function of bias and device parameters. We validate the model through numerous experimental results from different CMOS nodes, down to 40 nm. [read more...]

[paper] RESURF Model and Electrical Characteristics of Finger-Type STI Drain Extended MOS Transistors

RESURF Model and Electrical Characteristics of Finger-Type STI Drain Extended MOS Transistors
H. C. Tsai, R. H. Liou and C. Lien
IEEE Transactions on Electron Devices
vol. 63, no. 12, pp. 4603-4609, Dec. 2016

Abstract: Finger-type shallow trench isolation (finger STI) drain extended MOS transistors are fabricated and its electrical characteristics is studied. Polyplate on a finger STI served as a reduced surface field is adopted to enhance breakdown voltage (BV) by reducing the effective doping concentration of the drain extension (DE) finger. The conformal mapping method, which relates the reduction of the doping concentration to the width (z_o) of the DE finger, the gap (z_d) between the polyplate and the DE finger, and the STI depth (y_s), is used to estimate the reduction of the doping concentration theoretically. Based on this reduced doping concentration, a BV model is derived. The predictions of this model agree very well with the experimental data.

Keywords: Conformal mapping, Doping, Electric breakdown, MOS devices, Semiconductor process modeling, Silicon, Transistors, Drain extended MOS (DEMOS), Lateral double Diffused MOS (LDMOS), poly field plate, reduced surface field (RESURF)

doi: 10.1109/TED.2016.2605504
[read more...]