[ICTA2026 ] Special OpenPDK Session

IEEE International Conference on Integrated Circuits, Technologies & Applications

ICTA 2026 Special Session “OpenPDK - Global FOSS Scholar Platform"

21st - 24th (Wed - Sat) October 2026

Grand Copthorne Waterfront Hotel, Singapore

The OpenPDK initiative delivers a global FOSS Scholar Platform supporting analog/RF, mixed‑signal, and digital IC design. Central to this effort are accurate SPICE models for low‑power sensing MOSFETs, RF HBTs, and emerging RRAM devices, validated across cryogenic temperatures for space and quantum‑computing applications. The initiative also advances Verilog‑A compact‑model standardization, ensuring result reproducibility and seamless integration into open‑source design flows. Supported by the EU Chips JU, OpenPDK fosters collaboration among academia, startups, and industry, while providing FOSS IC‑design tools covering schematic capture, simulation, layout, and verification up to tape‑out. Similar to the EU Chips JU program, Zhejiang CoreXin in China offers an open‑source PDK together with tape‑out services for its 55nm CMOS process. To accelerate the semiconductor‑industry development across the Asia‑Pacific and Southeast‑Asia regions, semiconductor model development and parameter extraction techniques should be pursued in a more focused manner. This special session brings together experts to present and discuss advances in device characterization, compact modeling, simulation methodologies, and validation techniques for a broad range of solid‑state devices, including Si, III/V semiconductors, power devices, nanoscale structures, and emerging 2.5D/3D advanced packaging technologies [ read more...]

ICTA 2026 Special OpenPDK Session Presenters

• SPICE/Verilog-A standard models and OpenPDK practice
  Wladek Grabinski, GMC Consulting, Switzerland
• Open-Source Ecosystem Updates and Semiconductor Design Development Programs in Japan
  Jun-ichi Okamura, AIST Solutions, OpenSUSI, Japan
• Open-Source EDA Meets Industrial IC Design
  Ehrenfried Seebacher, ams-OSRAM AG, Austria
• Building an Open-Source Process Platform, Empowering VLSI Innovation and Development
  Da Zhang, Zhejiang University/CTO, Zhejiang Chuangxin Integrated Process Platform, China
• From Silicon to Design: Intelligent Measurement and Modeling for DTCO
  Yutao Ma, VP of R&D, Primarius Technologies. Ltd. China
• Beyond Moore, Application-Driven IC Innovation International Cooperation Opportunities at NICE
  Alex Gu, National Innovation Center Par Excellence (NICE), China
• 2.5D/3D IC: AI+EDA Reshaping the System-Design-Technology Co0ptimization (STCO) Paradigm for Advanced Packaging
  Alex Zhao, Founder/CEO Zhuhai SiChip Technology Co., Ltd., China
• Modelling of semiconductor devices: the heart of innovation bridging academia and industrial applications
  Fujiang Lin, University of Science and Technology of China (USTC), China

Special OpenPDK Session progeam include the panel discussion: 

How to have a close loop for PDK, EDA, PDA and ICS simulation?

[ read more...]

[conference] ELECTRONICS 2026 at KTU Kaunas

International Conference ELECTRONICS 2026

From SMT to Advanced Packaging – Manufacturing Meets Microinterconnects

KTU Kaunas, Lithuania

12–13 November 2026

Conference Vision : A joint platform connecting SMT engineers, advanced packaging researchers, reliability specialists, and industry to build a shared technical language, bridge research and manufacturing, and grow German-Baltic collaboration around heterogeneous integration and microinterconnects. Organized by Kaunas University of Technology, the conference serves as a platform for collaboration and discussion among representatives from academy, industry, and business.

Partners:
TUD IAFT (Dresden University of Technology, Institute of Electronic Packaging Technology)
IHP (IHP GmbH, Leibniz Institute for High Performance Microelectronics)
Industry Partners: FINETECH, TELTONIKA, etc.

Conference Program Online <https://eef.ktu.edu/events/electronics2026/>

Conference Organzation Committee:

General Chair

Prof., Dr. Mindaugas ŽILYS, KTU Kaunas

Executive Chair

Dr. Agata ROMANOVA, KTU Kaunas

Co-Chairs

Prof., Dr. Algimantas VALINEVIČIUS, KTU Kaunas

Prof., Dr. Darius ANDRIUKAITIS, KTU Kaunas

Prof., Dr. Dangirutis NAVIKAS, KTU Kaunas

Schematic to Silicon with Mini MOSbius

Zero To ASIC Course and Tiny Tapeout by Matt Venn

Schematic to Silicon with Mini MOSbius 

https://www.youtube.com/watch?v=NM5cLWYWqG0

Take Matt Venn TT course: 

https://www.zerotoasiccourse.com/

Buy a copy of Mini MOSbius, part of the TT IP library, here: 

https://store.tinytapeout.com/products/TTSKY25b-Development-Kit-p849160072

Check the configurator: 

https://github.com/mattvenn/mini-mosbius-configurator

Mini MOSbius is available on these chips

• [OK] TTSKY25a - delivered July 2026 - available in the store
• [OK] TTSKY25b - delivered August 2026 - available in the store
• TTSKY26b - tapeout May 2026
• TTSKY26c - tapeout September 2026
• GF180 - will be taped out December 2026

and finally check out the original MOSBius: https://mosbius.org/ If you are interested to acquire MOSbius kits, review the express license and email Peter Kinget for kit availability before placing an order.

[poster] Active Cantilever with Dual Actuator

Bartosz Pruchnik1, Fabian Dietrich2, Richard Subianto2, Katerina Ivanova2, Athulya K. Muraleedharan Bindu2, Hans-Georg Pietscher2, Javad Basseri2, Muralikrishnan Brajesh Kaimal2, Władysław Kopczyński1, Wojciech Godlewski1, Dominik Badura1, Piotr Putek1, Krzysztof Kwoka1, Piotr Smagowski1, Andrew Yacoot3, Tomasz Piasecki1, Fangzhou Xia4, Ivo W. Rangelow2 

Active Cantilever with Dual Actuator

52nd International Micro and Nano Engineering Conference

Sep. 21-24, 2026 Interlaken (CH)

MEN2026 Poster S05A-T2-P-5

1. Wrocław University of Science and Technology,

2. nano analytik GmbH, 

3. National Physical Laboratory

4. University of Texas at Austin

Abstract: Atomic Force Microscopy (AFM) is often limited by the speed and bandwidth of three main components: the cantilever, the scanner, and the controller. Recent microelectromechanical systems (MEMS) have improved the performance of the cantilever and scanner by combining high-speed active cantilevers with low-latency scanners. In this work, we present a standardized active cantilever design. The system combines a large cantilever that acts as a Z-axis actuator with a smaller active cantilever sensor that provides a bandwidth greater than 400kHz. The smaller cantilever is integrated into the larger structure, creating a compact and highly responsive device. We introduce a new active cantilever architecture that uses two integrated electrothermal actuators. One actuator is used for cantilever operation, while the second provides vertical (Z-axis) movement for surface tracking. This design allows AFM measurements to be performed without the need for an external piezoelectric z-actuator.

Acknowledgements: This work was supported by the European Union's Horizon Europe research and innovation program under the Marie Sklodowska-Curie grant agreement No 101072775, and by the National Science Centre, Poland (grant No. 2021/41/B/ST7/03144).

[paper] Open Source EZ130 8T standard cell library

Oscar Castaneda, Lavinia Recchioni, Tobias Senti, Flurin Cahenzli, Marco Ferroni, Thorben Heekenjann, Robert Kenter, Stefan Odermatt, Daniel Richner, Gabriel Altendorfer, Davide Cannone, Miguel Correa, Ivan Herger, Lars Kroger, Nicolas Nanzer, Darja Nonaca, Christopher Reinwardt, Lukas Winklhofer, Enrico Zelioli, Yiheng Zhang, Yingxue Zhang, Domenic Keller, Seyed Hadi Mirfarshbafan, Zerun Jiang, Beat Muheim, Arianna Rubino, Jeremy Guichemerre, Frank K. Gurkaynak, and Christoph Studer

An Open-Source Standard-Cell Library for IHP 130 nm Developed by Students

arXiv:2609.29965v1 [cs.AR] 24 Sep 2026

1. Department of Information Technology and Electrical Engineering, ETH Zurich, Switzerland

* The open-source EZ130 8T standard-cell library is available at https://ez.ethz.ch

Abstract: Standard-cell libraries form the critical interface between transistor-level circuit design and automated digital design flows, yet their design and characterization are rarely covered in depth in digital VLSI courses. This paper presents VLSI 5, a graduate-level course at ETH Zurich in which students design, lay out, characterize, and integrate their own standard cells using IHP’s open-source 130 nm SG13G2 process design kit. In the first course offering, 19 students developed EZ130 8T, an open-source eight-track standard-cell library comprising 220 cells. We evaluate successive library versions using eight synthesis benchmarks, across which EZ130 8T achieves significant area reduction compared to the SG13G2 library at competitive timing. For a postlayout 8×8 matrix-vector multiplier, EZ130 8T reduces cell area by 35% and energy by 39% while maintaining virtually the same clock period. The library has already been adopted in other ETH Zurich VLSI courses, enabling the creation of chips entirely designed by students down to the transistor level.

FIG: a.) ETH Zurich course series on digital VLSI design. By teaching students to create a standard-cell library, the new VLSI 5 course closes the gap between transistor-level and HDL-level IC design;
b.) and c.) Layout of two example standard cells from the EZ130 8T library.

Aknowlegements: This work has received funding from the Swiss State Secretariat for Education, Research, and Innovation (SERI) under the SwissChips initiative. The authors thank Cadence for their support by providing licenses to design and characterize the EZ library. The authors also thank H. Pretl, T. Benz, and P. Sauter for their feedback on preliminary versions of the EZ library.

[paper] n-MOS pseudo-resistor nA current reference

Bruni, Italo, Mariane Petraglia, and Fabián Olivera

Area-efficient nanoampere current reference employing

a temperature-controlled n-MOS pseudo-resistor

AEU IJ EC (2026): 156642.

DOI: 10.1016/j.aeue.2026.156642

Abstract: This paper presents a CMOS current reference topology that avoids the use of large-area resistors by using a temperature-controlled pseudo-resistor. The proposed technique for achieving a reference current consists of applying proportional to absolute temperature (PTAT) and complementary to absolute temperature (CTAT) voltages to the drain and gate of an n-MOS EKV-based pseudo-resistor, respectively, thereby stabilizing its current against temperature variations. Two current reference design versions, namely D01 and D02, were implemented using a 180 nm technology. Extensive post-layout simulation results for design D01 show a typical reference current of 6.30 nA, an average temperature coefficient (TC) of 414 ppm/C (nominal 219 ppm/C) across a range from −40C to 120C, and a line regulation (LR) of 11.76 %/V. To improve LR, design D02 was developed, achieving a significantly optimized LR of 0.33 %/V while maintaining a typical current of 6.22 nA and an average TC of 401 ppm/C (nominal 191 ppm/C) over the same temperature range. The area-efficient technique enables compact silicon areas of 0.0018 mm2 and 0.0020 mm2 for D01 and D02, respectively.

FIG: Schematics of the CTAT voltage generator topologies: .a) 3T; b.) 6T

and its layout implementation of the current reference designs: c.) D01; d.) D02.

Acknowledgment: This work was supported in part by the Brazilian research funding agencies CNPq, FAPERJ, and Coordenação de Aperfeiçoamento de Pessoal de Nível Superior - Brasil (CAPES) Finance Code 001; by grant 307092/2025-9, funded by CNPq/MCTI/FNDCT N∘18/2024; and by grant E-26/204.222/2025 (SEI-260003/020616/2025), founded by FAPERJ JCNE .

[webinar] Colombia in OpenSilicon Age

IEEE SSCS: Colombia in OpenSilicon Age

• Date: Thursday, October 8, 2026
• Time: 1:00 PM – 2:30 PM (Colombia, GMT-5)
• Platform: Cisco Webex
• Access: Free/Open access

This open online event is the first IEEE SSCS Colombia session. It shares a vision for creating a strong microelectronics ecosystem in Colombia by bringing universities and industry together and helping develop highly skilled engineers. The event will review the current state of microelectronics in Colombia, discuss the future of integrated circuit (IC) design, present recent semiconductor policy initiatives, and explain the goals of the IEEE SSCS Colombia chapter. Speakers from Colombia and abroad will share their experience in IC design, open-source silicon, semiconductor education, and industry development. The session aims to encourage collaboration between academia, industry, and government to support the growth of the semiconductor sector in Colombia.

Featured Panelists and Keynote Speakers

• Made in Colombia: Review of Colombian Microelectronics
  Javier Ardila, Onsilicon, UIS and President, IEEE SSCS
• ColombiaThe Global Map of CI Design: Tools, Foundry and Methodology
  Hugo Hernández, Teradar, Boston, MA
• OpenSilicon Opportunities
  Fernando Guarín IEEE Division 1
• Bill for the promotion of the electronics and semiconductor industry
  Lorena García Founder, Colombian Network of Electronics and Semiconductors

IEEE LA & Caribbean Semi Summit

IEEE Latin America & the Caribbean

Semiconductor Summit

LACSS 2026 will bring together leaders from industry, government, academia, research institutions and the investment community to explore Latin America and the Caribbean’s role in the rapidly evolving global semiconductor ecosystem.

The two-day (Oct. 1-2) program will examine regional capabilities and opportunities across semiconductor design, talent development, advanced manufacturing, packaging and testing, supply chains, investment, public policy, research, critical technologies and international cooperation. The IEEE EDS/CASS MQ Semiconductors in Latin America will follow on the third day (Oct.3)

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DAY 1 — Academia and Industry: Building Talent, Research and Innovation
Thursday, October 1st, 2026

Opening
08:30–09:00	Opening Ceremony Ivan Armuelles, Chair IEEE LACSS 2026 Juan Pimiento, SENACYT, Panama
09:00–09:30	Overview of the Semiconductor Industry Today and Opportunities for Latin America through the IEEE Open Silicon Initiative Fernando Guarin, IEEE Division I, Director - GlobalFoundries (Retired) / IBM (Retired), USA
Building Semiconductor Talent: National Experiences from Latin America Moderator: Fernando Guarín, IEEE
09:30–09:50	Building Panama's National Semiconductor Talent Pipeline Zoila De Castillo, C-TASC, Panama
09:50–10:10	Brazil´s Semiconductor Industry and Design House Ecosystem Jacobus Swart, University of Campinas (UNICAMP) / INCT NAMITEC, Brazil
10:10–10:30	The Kutsari initiative and strategy for the future (virtual) Edmundo Gutierrez, Kutsari (National Center for Semiconductor Design in Mexico), Mexico
10:30–11:00	Networking Coffee Break
Electronic Design Automation Moderator: Ricardo Reis, UFRGS, Brazil
11:00–12:30	Panel: EDA Innovation and Latin America’s Role in the Global Semiconductor Ecosystem Antonio de la Serna, Siemens EDA Victor Grimblatt, Synopsys Marcelo Da Silva, Cadence
12:30–14:00	Lunch
Talent Development and Industrial Capabilities Moderator: Carlos Silva, PUCP, Peru
14:00–14:30	Talent: the keyword for the development of semiconductors Ricardo Reis, Institute of Informatics, Federal University of Rio Grande do Sul (UFRGS), Brazil
14:30–15:45	Panel: Preparing Semiconductor Talent–Industry and University Experiences Rodrigo Jaramillo, Circuify Semiconductors, Mexico Alfredo Arnaud, Universidad Católica del Uruguay, Uruguay Victor Grimblatt, Synopsys, Chile Amílcar Josué Véliz Solares, Universidad Galileo, Guatemala Javier Marte Michelen, Pontificia Universidad Católica Madre y Maestra, Dominican Republic
15:45–16:15	Networking Coffee Break
16:15–16:45	Assembly, Testing and Packaging: Opportunities for Latin America Joel Molina, INAOE, Mexico
Day 1 Wrap-up
16:45–17:00	Day 1 Wrap-Up Ivan Armuelles, Chair IEEE LACSS 2026
18:00–20:00	Welcome Reception (off-site) La Casa - Ciudad del Saber

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DAY 2 — Government and Industry: Policy, Investment and Regional Strategy
Friday, October 2nd, 2026

08:30–08:45	Day 2 Kick-off Start of Day 2: summary of the previous day and agenda of the day
Global Policy, Cooperation and Investment Moderator: Erik Heilman, IEEE-USA
08:45–09:30	Global Policy Perspectives for Semiconductor Development Filipe Silva, Semiconductors Team Lead, OECD (virtual)
09:30–10:00	Pax Silica and the Global Semiconductor Ecosystem: Implications for Latin America and the Caribbean (virtual) Akhil Ramesh, PAC Forum
10:00–10:30	Panama’s Semiconductor Strategy (TBC) Victor Sanchez, C-TASC AIP, Panama
10:30–11:00	Networking Coffee Break
The Semiconductor Policy Playbook: Regulation, IP and Regional Development Moderator: TBC
11:00–12:20	Panel: Policies and Partnerships for Latin American Semiconductor Ecosystems Adão Villaverde, Brazil Mayté Milián, Guatemala Nestor García Romero, Mexico Lorena Garcia, Colombia
12:20–12:30	IEEE Division I–Synopsys MoU Signing Ceremony: Semiconductor Workforce Development Fernando Guarín, IEEE Division I Victor Grimblatt, Synopsys
12:30–14:00	Lunch
Semiconductor Design, Manufacturing and Entrepreneurship Moderator: Lorena Garcia, Alianza E, Colombia
14:00–15:30	Panel: Building Semiconductor and Hardware Businesses in Latin America Rodrigo Jaramillo, Circuify Semiconductors, Mexico Israel Mejia, QSM, Mexico (virtual) Gabriel Ortiz, Pixart, Argentina Alfonso Chacon, Rydev, Costa Rica Javier Ardila, OnSilicon, Colombia (virtual)
15:30–16:00	Networking Coffee Break
Expanding Access to Semiconductor Design, Prototyping and Manufacturing Moderator: Joel Molina, INAOE, Mexico
16:00–17:00	Panel: Expanding Access to Semiconductor Design, Prototyping and Manufacturing Pat Deegan, Tiny Tapeout Mitchell Hsing, InchFab Alfonso Torres, INAOE (virtual)
FET 100 Moderator: Arokia Nathan, IEEE EDS, USA
17:00–17:45	FET100 Speakers: Fernando Guarin, Jacobus Swart.
17:45–18:00	Closing - LACSS 2027 announcement Ivan Armuelles Ricardo Reis
18:00	End of LACSS

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DAY 3 — 2026 IEEE EDS/CASS MQ Semiconductors in Latin America
Saturday, October 3rd, 2026

Universidad De Panama Auditorio (Piso 3), Facultad De Informática, Electrónica Y Comunicación

	IEEE EDS/CASS MQ Session:  Exploring Innovation, Research, and Opportunities for a Semiconductor Future in the Caribbean
8:00–8:15	Opening Ceremony — Registration and Welcome Remarks
8:15–8:45	Low Power Design for Sustainable Manufacturing in Agribusiness Victor Grimblatt
8:45–9:15	Embedded Timing: A New Scaling Layer for Compute at System Scale Rodrigo Calderon
9:15–9:45	Reliability Topics for Advanced Semiconductors Fernando Guarin
9:45–10:15	Physical Design Automation: From Past to Future Ricardo Reis
10:15–10:45	Networking Coffee Break
10:45–11:15	Brazil’s Semiconductor Industry and Design House Ecosystem Jacobus Swart
11:15–11:45	Oxide Electronics Arokia Nathan
11:45–12:15	Dielectrics Materials from Field Effect Transistors to In-Memory Computing Durga Misra
12:15–13:30	Lunch

[EUMW.EU] IHP Open Source Toolchain

Open-source Toolchain in RF and Digital Design

08:30 - 12:50; Monday 5 October 2026

European Microwave Week 

WM02, Room 3, ExCeL, London

The European Chips Act serves as a strategic roadmap to secure technological sovereignty by aiming for a 20% global market share in semiconductors by 2030. The goal is to minimize the geopolitical supply chain risks and foster a self-sufficient ecosystem. Democratization of hardware development through the development of open-source EDA tools is a key pillar in these aspects. This would lower the entry barriers for SMEs and researchers and ultimately accelerate a collaborative and transparent era of European silicon innovation. There are multiple EU funded projects have started from last few years. These projects are set to offer robust process design kits (PDK) for open-source tools. In parallel, existing open-source tools for IC design are being further enhanced to include necessary functionalities for complete design flow for digital, analogue and RF design. Aligning with above mentioned goals, multiple private, academic, and commercial entities have stepped up towards the development. This workshop aims to share a glimpse of activities in open-source EDA tools developments and chip design activities in Europe. It would begin with a talk about current EU projects and the statuses in open-source EDA development. Then there will be two talks about digital and RF design flow using open-source tools. The final talk is about electro-magnetic simulation for RF circuits. Overall, this workshop is targets to publicize the open-source activities towards the building of a collaborative society in chip design domain. 

The event is aimed at IC designers, researchers, PhD candidates and engineers who already have a basic understanding of chip design and EDA workflows. Familiarity with digital, analogue or RF design will help you get the most from the sessions.

This workshop, chaired by the IHP Team: Corrado Carta, Sergei Andreev, and Farabi Ibne Jamal, gives you a practical view on the following Open-Source R&D Topics:

• European Open-Source EDA projects currently stand
• Sergei Andreev, IHP
• How digital design flows can be built with Open-Source tools
• Frank Kagan Gurkaynak, ETH Zürich
• How Open-Source tools are being applied to RF design 
• Harald Pretl, Johannes Kepler Universität Linz
• How Open-Source EM simulation fits into RF circuit development
• Giovanni Di Pietrantonio, IHP and Volker Mühlhaus, MCS, GmbH

Join the IHP OpenPDK Team if you want to understand where open-source chip design is heading, what is already usable today, and how these tools could complement your own work. Register at the EuMW website.

IEEE EDS/SSCS/CAS Mini-Colloquium

Friday 11 September 2026

UIB; Sa Riera Building

C/ de Miquel dels Sants Oliver, 2

07122 Palma

Professors Benjamin Iniguez, URV and Rodrigo Picos, UIB, have organize joint IEEE EDS/SSCS/CAS Mini-Colloquium as an integral part of the recent ESSERC2026 in Palma de Mallorca. All the MQ participants followed the MQ program as follows:

Mini-Colloquium Agenda

9:00 - 09:05 Opening

9:05-9:15 Tribute to Michael S. Shur

9:05-9:15 Tribute to José Epifânio da Franca 

9:15-10:05 Leveraging semiconductor technology for the benefit of society

Fernando Guarin (Director of IEEE Division I)

10:05-10:55 Power efficient WBG devices for the green transition

Mikael Ostling (KTH, SE)

10:55-11:25 Coffee Break

11:25-12:15 Holistic solutions to future computing - not only scaling

Francesca Iacopi (Purdue University, US)

12:15-13:05 Status of the Compact modeling and its Verilog-A standardization

Wladek Grabinski (MOS-AK, CH and IHP OpenPDK, DE)

13:05-14:25 Lunch

14:25-15:15 Graphene thin film technology for neural interfaces

José Antonio Garrido (ICN2, Barcelona, Spain)

15:15-16:05 Energy-Efficient Analog IC Design:

Exploring Solutions at Device, Circuit and System Levels

Antonio López (Public University of Navarra, Spain)

[paper] TCAD Modeling of SB Diode

Pedro Paulo Pessoa Oliveira1,2, Andreas Mai1,3, Norbert Herfurth1, 

and Davies William de Lima Monteiro2

TCAD Modeling of Schottky-Diode in an open-source SiGe BiCMOS technology

In 2026 40th Symposium on Microelectronics Technology and Devices 

SBMicro, pp. 1-4. IEEE, 2026

DOI: 10.1109/SBMicro70495.2026.11684441

1. IHP, Frankfurt (Oder), Germany
2. Department of Electrical Engineering, UFMG - Belo Horizonte-MG, Brazil
3. University of Applied Sciences Wildau, Germany

Abstract: Accurate simulation of Schottky barrier diodes (SBDs) is challenging because standard idealized models fail to capture non-ideal interface physics, such as Fermi-level pinning and image-force lowering. This paper presents an enhanced Technology Computer-Aided Design (TCAD) methodology to model an SBD from the IHP SG13G2 130-nm open-source SiGe BiCMOS technology. To overcome limitations of conventional simulations that often rely on oversimplified assumptions and empirical fitting, this work explicitly incorporates interface en- ergy states into the simulation, specifically modeling the fun- damental pinning mechanisms driven by Metal-Induced Gap States (MIGS). By calibrating the TiSi2/Si interface using the theoretical slope parameter, a value of 0.503 V was determined for the zero-bias barrier height. The resulting physics-based model captures the true rectifying nature of the contact and accurately reproduces the electrical characteristics targeted by the empirical model, achieving a nominal forward voltage drop of 0.39 V and a realistic reverse leakage current of 29.3 nA at -2.5 V. Ultimately, this paper shows the innovation and education gain of open- source foundry data by showcasing an open innovation path for a targeted near-industry device development flow.

FIG: a.) Energy band diagram of the Schottky diode at V=0V. Thecoordinate x = 0 corresponds to the TiSi2/n-Si Schottky interface. The inset displays the 2D device schematic, with the solid black line indicating the multi-segment cut-path used to extract the energy levels across the anode, n-buried layer and n-well RT to cathode contact. b.) Comparison of the simulated DC current-voltage (IV) characteristics between the proposed TCAD model and the standard SPICE macromodel.

Acknowledgment: The authors thank IHP for the open-source PDK and the collaborative research. They also thank Universidade Federal de Minas Gerais (UFMG) and the Brazilian Microelectronics Society (SBMicro) for supporting this work. Finally, gratitude is extended to S. Srivastava and B. Sake for their valuable guidance.

[NanoIC] Workshop

NanoIC Pilot Line Workshop

Next logic, memory, and chiplet technologies to enable future system innovation

October 1, 2026; Sede Turismo Andaluz; 40 Compañía Str. Málaga, Spain

Workshop Agenda

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10:00 - 10:10 Welcome
10:10 - 10:30 Marie Garcia Bardon 

Short Introduction to EU Chips Act NanoIC Pilot Line

10:30 - 11:30 Nicolas Pantano 

Enabling Chiplet Architectures Through Advanced Packaging And High-Density Interconnects

11:30 - 12:00 Coffee break
12:00 - 13:00 Fernando García Redondo 

Opportunities in memory scaling: design-technology co-optimization for SRAM and emerging memories

13:00 - 14:00 Marie Garcia Bardon 

Advanced Logic Scaling: Technologies for the sub-2nm

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Free Registration Online Workshop  

               https://u.uma.es/icc/workshop

[ChipFoundry] December Shuttle: Commitment deadline moved to November 4th

ChipFoundry Team has an important update regarding our upcoming December shuttle. The commitment deadline has been moved to November 4th. We want to remind you that this is not the final design submission date. Here is what you need to know to confirm your space: A 50% payment of your total is required by November 4th to hold your reservation. Your final design files are still due on December 7th. The tapeout submission date has not changed. You only need to provide your user project wrapper, and we will handle the integration through our tapeout flow. Our team is available if you have any questions about the submission process or need help with your invoice. Reserve Now We look forward to confirming your commitment and working with you on your December tapeout!   Best regards,   The ChipFoundry Team ­ ­