Showing posts with label performance. Show all posts
Showing posts with label performance. Show all posts

Oct 13, 2026

[paper] Self-Heating Effects in 55-nm SiGe HBTs

Abdelaaziz Boulgheb1, Billel Smaani2, Taha Housseyn Nouibat1
Physics-Based Electro-Thermal Modeling and Analysis 
of Self-Heating Effects in 55-nm SiGe HBTs
physica status solidi (a), 2026; 223:e70563 
https://doi.org/10.1002/pssa.70563

1. USTHB, Bab Ezzouar, Algeria 
2. University of Mila, Mila, Algeria

Abstract: This work investigates spatially resolved electrothermal behavior in scaled SiGe HBTs under self-heating conditions, emphasizing its impact on temperature distribution and RF performance. Unlike conventional lumped thermal resistance approaches assum- ing uniform temperature rise, the present analysis resolves the internal temperature field to capture nonuniform heat propagation effects. A physics-based electrothermal framework combining drift–diffusion transport, temperature-dependent semiconductor properties, and heat conduction equations is used to study hotspot formation and thermal confinement in a 55 nm SiGe HBT structure. Three operating conditions are considered: nominal operation at 300 K, self-heating at 300 K ambient temperature, and elevated ambient temperature of 320 K. The results reveal localized hotspot formation near the base–collector junction due to current crowding and geometrical confinement, leading to RF performance degradation. The cutoff frequency decreases from 320 to 285 GHz, while the maximum oscillation frequency reduces from 486 to 458.5 GHz. The current gain decreases from 2000 to 1500, and the maximum junction temperature reaches 417 K under the highest thermal stress condition. These findings highlight the importance of spatial thermal effects in governing RF limitations of SiGe HBTs and provide insight into the coupling between heat propagation and electrical performance in BiCMOS technologies.
FIG: Device structure of 55 nm SiGe HBT simulated with multiphysics TCAD: (a) log of electron and hole concentration highlighting emitter/base/SIC pedestal (b) TEM cross section of a fabricated BiCMOS 55nm HBT. Impact of self-heating on high-frequency performance of the 55-nm SiGe HBT under three thermal conditions: (c) parasitic delay parasitic (d) forward transit time τF , (e) cutoff frequency fT, and (f) maximum oscillation frequency fmax.

Jul 21, 2023

[book] Organic and Inorganic Light Emitting Diodes

Organic and Inorganic Light Emitting Diodes
Reliability Issues and Performance Enhancement

Edited By T.D. Subash, J. Ajayan, W. Grabinski

ISBN 9781032375175 1st Edition (C) 2023
198 Pages 106 B/W Illustrations
Published June 19, 2023 by CRC Press

Description
This book covers a comprehensive range of topics on the physical mechanisms of LEDs (light emitting diodes), scattering effects, challenges in fabrication and efficient enhancement techniques in organic and inorganic LEDs. It deals with various reliability issues in organic/inorganic LEDs like trapping and scattering effects, packaging failures, efficiency droops, irradiation effects, thermal degradation mechanisms, and thermal degradation processes.

Chapter 1: Fundamental Physics of Light Emitting Diodes: Organic
and Inorganic Technology; Deboraj Muchahary, Sagar Bhattarai, Arvind Sharma and Ajay Kumar Mahato
Chapter 2: Physical Mechanisms That Limit the Reliability of LEDs; Tulasi Radhika Patnala, N. Hemalatha, Sankararao Majji and M. Sundar Rajan
Chapter 3: Scattering Effects on the Optical Performance of LEDs; Vinodhini Subramaniyam, B. A. Saravanan and Moorthi Pichumani
Chapter 4: Challenges in Fabrication and Packaging of LEDs; Nesa Majidzadeh and Hossein Movla
Chapter 5: Opportunities and Challenges in Flexible and Organic LED; Shalu C.
Chapter 6: Light Extraction Efficiency Improvement Techniques in Light-Emitting Diodes; M. Manikandan, G. Dhivyasri, D. Nirmal, Joseph Anthony Prathap and Binola K. Jebalin I. V.
Chapter 7: Efficiency Enhancement Techniques in Flexible and Organic Light-Emitting Diodes; J. Ajayan and T. D. Subash
Chapter 8: Performance Enhancement of Light Emitting Radiating Dipoles (LERDs) Using Surface Plasmon-Coupled and Photonic Crystal-Coupled Emission Platforms; Seemesh Bhaskar and Sai Sathish Ramamurthy



Jan 12, 2022

[paper] Pseudo-morphic PHEMT: Numerical Simulation Study

Khaouani Mohammed, Hamdoune Abdelkader, Guen Ahlam Bouazza, Kourdi Zakarya, Hichem Bencherif
An Improved Performance of Al0.25Ga0.75N/AlN/GaN/Al0.25Ga0.75N Pseudo-morphic High Electron Mobility Transistor (PHEMT): 
Numerical Simulation Study
IC-AIRES 2021. Lecture Notes in Networks and Systems, vol 361. Springer
DOI: 10.1007/978-3-030-92038-8_80




1. Hassiba Benbouali, Chlef, Algeria
2. University of Abou-Bakr Belkaid, Tlemcen, Algeria
3. Center Exploitation Satellite Communications Agency of Space Oran, Algeria
4. University of Mostefa Benboulaid, Batna, Algeria 

Abstract: In this paper a 9nm T-shaped gate length, Pseudo-morphic High Electron Mobility Transistor (pHEMT AlGaN/AlN/GaN/AlGaN) is studied; we use TCAD software. DC, AC and RF performances assessment allow to exhibit interesting results such as a maximum drain current IDSmax=35mA at VGS=0V, a knee voltage Vknee=0.5V with ON-resistance Ron=0.8Ω-mm, a sub-threshold swing of 75mV/decade, a maximum transconductance value gm=160mS/mm, a DIBL of 36mV/V, a drain lag of 8.5%, a cut-off frequency of 110GHz, a maximum oscillation frequency of 800GHz, and very suitable breakdown voltage VBR of 53.1V. This device can be used in radar, high power and amplifier applications.


Mar 2, 2021

[paper] Predictive Hot-Carrier Aging Compact Model

Y. Xiang1,2, S. Tyaginov1,3,4, M. Vandemaele1,2, Z. Wu1,2, J. Franco1, E. Bury1, B. Truijen1, B.Parvais1,5, D. Linten1, B. Kaczer1
A BSIM-Based Predictive Hot-Carrier Aging Compact Model 
4A.4; IRPS March 21- 24 2021 

1imec, Leuven (B)
2Department of Electrical Engineering (ESAT), KU Leuven, Leuven (B)
3Institute for Microelectronics (IuE), TU Wien, Vienna (A)
4Ioffe Physical-Technical Institute of the Russian Academy of Sciences, Saint Petersburg (RU) 
5Department of Electronics and Informatics (ETRO/VUB), Brussels
 (B)

Abstract: The continued challenge of front-end-of-line transistor reliability has long demanded physics-based SPICE compact models, not only for service lifetime estimation, but also for agingaware device pathfinding with technology scaling and innovation. Here, we present a predictive hot-carrier-degradation (HCD) compact model built upon the industry-standard BSIM model, that conveniently embeds the essential HCD physics within common SPICE simulation flows. We leverage and augment the established, scalable electrostatics and transport in BSIM as the input to an analytical HCD interface states generation formalism, the result of which is in turn injected back into BSIM for a selfconsistent estimation of the threshold voltage (VTH) shift and the mobility degradation. Our approach readily exhibits fundamental, non-empirical predictabilities of the stress timeand the sensing bias- dependency of transistor-level degradation, without having to resort to a priori assumptions. This will further accommodate the irregular, arbitrary voltage waveforms in transient circuit operations, thus enabling efficient evaluation of the power-performance degradation at circuit level. The model ultimately aims to lay the groundwork for a reliability-aware design-technology co-optimization in device pathfinding. 
Fig: Schematic of the Pao-Sah DD current integral method used in commercial CMs [a-e] and the extrapolated piecewise Vch(y) by augmenting the BSIM model. In the Pao-Sah DD formalism, the actual Ids is calculated by the difference of the integral Ξ at the source (channel potential Vch=0) and at the “drift-diffusion limit” (at LDD, where channel potential Vch=VDS,eff), with the latter defined by velocity saturation or pinch-off. The Vch(y) is extrapolated by using the implicit assumptions in BSIM-BULK: the quadratic profile under gradual channel approximation (GCA) and the hyperbolic profile under the drain-side field assumption used in substratecurrent body-effect (SCBE). 

References:
[a] C. K. Dabhi. (2017). BSIM4 4.8.1 MOSFET Model: User’s Manual. [Online]. Available: https://bsim.berkeley.edu/models/bsim4/.
[b] H. Agarwal. (2017). BSIM-BULK106.2.0 MOSFET Compact Model: Technical Manual. [Online]. Available: https://bsim.berkeley.edu/models/bsimbulk/. 
[c] S. Khandelwal. (2015). BSIM-CMG 110.0.0 Multi-Gate MOSFET Compact Model: Technical Manual. [Online]. Available: https://bsim.berkeley.edu/models/bsimcmg/. 
[d] P. Kushwaha. (2017). BSIM-IMG 102.9.1 Independent Multi-Gate MOSFET Compact Model: Technical Manual. [Online]. Available: https://bsim.berkeley.edu/models/bsimimg/. 
[e] W. Grabinski et al., (2019) "FOSS EKV2.6 Verilog-A Compact MOSFET Model," ESSDERC 2019 - 49th European Solid-State Device Research Conference (ESSDERC), Cracow, Poland, 2019, pp. 190-193, doi: 10.1109/ESSDERC.2019.8901822
[Online] Available: https://github.com/ekv26/model