[paper] Cryo 1T1R HfO2-Based RRAM

Emilio Pérez-Bosch Quesada, Alberto Mistroni, Ruolan Jia, Keerthi Dorai Swamy Reddy, Markus Fritscher, Felix Reichmann, Oliver Skibitzki, Juan Bautista Roldán, Helena Castán, Salvador Dueñas, Christian Wenger, Eduardo Pérez

Enabling Quantum-Compatible Nonvolatile Memory: Cryogenic Evaluation 

of 1T1R HfO2-Based RRAM From 300 to 1.5K

Advanced Electronic Materials 12, no. 19 (2026): e00798

DOI: 10.1002/aelm.202500798

ABSTRACT: To enable compact quantum computing systems, cryogenically compatible CMOS-based non-volatile memories are required. In this work, we investigate 1-transistor–1-resistor (1T1R) resistive random-access memory (RRAM) devices over an extended temperature range, including previously unexplored cryogenic regimes. To enhance storage density, we explore a multilevel-cell approach via multilevel programming. As temperature decreases, the low-resistance state (LRS) effective conductance increases, improving state separation but also leading to higher LRS currents and increased reset voltages required for reliable switching to the high-resistance state (HRS), resulting in incomplete filament rupture and a broader HRS distribution. Through independent characterization of the access nMOS transistor, we identify transistor temperature dependence as the dominant factor governing LRS evolution, while extraction of the intrinsic metal–insulator–metal (MIM) behavior reveals an opposite trend, with decreasing conductivity at lower temperatures. Based on these insights, we implement an optimized programming strategy for cryogenic operation by tuning the nMOS gate bias during set, reducing LRS currents, particularly in intermediate and high conductance states, while preserving state separation, narrowing the HRS distribution, and lowering reset voltages. Overall, this work establishes a robust and scalable approach for reliable 1T1R operation at cryogenic temperatures and provides a key step toward nonvolatile memory integration in quantum computing architectures.

FIG: a) Cryogenic setup used to characterize the RRAM devices under study, b) RRAM array containing a total of 32 1T1R devices individually addressable, and c) schematic description of the forming, set, and reset operations carried out during this work.

Acknowledgments: This work was financially supported by the Deutsche Forschungsgemeinschaft (DFG, German Research Foundation) under Project 551916740.

[paper] SPICE Modeling of Cycle-to-Cycle Variability in RRAM Devices

E.Salvador^a, M.B.Gonzalez^b, F.Campabadal^b, J.Martin-Martinez^a, R.Rodriguez^a, E.Miranda^a

SPICE Modeling of Cycle-to-Cycle Variability in RRAM Devices

Solid-State Electronics; In Press, Journal Pre-proof

Available online 29 May 2021, 108040

DOI: 10.1016/j.sse.2021.108040

a) Departament d’Enginyeria Electrònica, Universitat Autònoma de Barcelona, 08193 Cerdanyola del Valles, Spain
b) Institut de Microelectrònica de Barcelona, IMB-CNM, CSIC, 08193 Cerdanyola del Valles, Spain

Abstract: In this work, we investigated how to include uncorrelated cycle-to-cycle (C2C) variability in the LTSpice quasi-static memdiode model for RRAM devices. Variability in the I-V curves is first addressed through an in-depth study of the experimental data using the FITDISTRPLUS package for the R language. This provides a first approximation to the identification of the most suitable model parameter distributions. Next, the selected candidate distributions are incorporated into the model script and used for carrying out Monte Carlo simulations. Finally, the experimental and simulated observables (set and reset currents, transition voltages, etc.) are statistically compared and the model estimands recalculated if it is necessary. Here, we put special emphasis on describing the main difficulties behind this seemingly simple procedure.

Figure 4. Comparison of experimental and simulated parameter distributions: 

a) IHRS, b) VT, c) ILRS, and d) VR.

Acknowledgements: This work was supported by the Spanish Ministry of Science, Innovation and Universities through projects TEC2017-84321-C4-1-R, TEC2017-84321-C4-4-R, and PID2019-103869RB-C32.

[paper] Review of physics-based compact models for emerging nonvolatile memories

Nuo Xu¹, Pai-Yu Chen², Jing Wang¹, Woosung Choi¹, Keun-Ho Lee³, Eun Seung Jung³, Shimeng Yu²

Review of physics-based compact models for emerging nonvolatile memories

¹Device Lab, Samsung Semiconductor Inc., San Jose, CA 95134, USA

²School of ECEE, Arizona State University, Tempe, AZ 85281, USA

³Semiconductor R&D Center, Samsung Electronics, Hwasung-si, Gyeonggi-do, Korea

Journal of Computational Electronics, 2017, pp. 1-13

https://doi.org/10.1007/s10825-017-1098-0

Abstract: A generic compact modeling methodology for emerging nonvolatile memories is proposed by coupling comprehensive physical equations from multiple domains (e.g., electrical, thermal, magnetic, phase transitions). This concept has been applied to three most promising emerging memory candidates: PCM, STT-MRAM, and RRAM to study their device physics as well as to evaluate their circuit-level performance. The models’ good predictability to experiments and their effectiveness in large-scale circuit simulation suggest their unique role in emerging memory research and development [read more...]

https://doi.org/10.1007/s10825-017-1098-0

[paper] Well-Posed Models of Memristive Devices

Well-Posed Models of Memristive Devices

Tianshi Wang, Jaijeet Roychowdhury

(Submitted on 15 May 2016)

Existing compact models for memristive devices (including RRAM and CBRAM) all suffer from issues related to mathematical ill-posedness and/or improper implementation. This limits their value for simulation and design and in some cases, results in qualitatively unphysical predictions. We identify the causes of ill-posedness in these models. We then show how memristive devices in general can be modelled using only continuous/smooth primitives in such a way that they always respect physical bounds for filament length and also feature well-defined and correct DC behaviour. We show how to express these models properly in languages like Verilog-A and ModSpec (MATLAB). We apply these methods to correct previously published RRAM and memristor models and make them well posed. The result is a collection of memristor models that may be dubbed "simulation-ready", i.e., that feature the right physical characteristics and are suitable for robust and consistent simulation in DC, AC, transient, etc., analyses. We provide implementations of these models in both ModSpec/MATLAB and Verilog-A.

Subjects: Emerging Technologies (cs.ET); Computational Engineering, Finance, and Science (cs.CE)
Cite as: arXiv:1605.04897 [cs.ET]
(or arXiv:1605.04897v1 [cs.ET] for this version)