Showing posts with label Europe. Show all posts
Showing posts with label Europe. Show all posts

Apr 1, 2025

[Session] Improving Chip Design Enablement for Universities in Europe

DATE2025 FS06 Focus Session:
Date: Tuesday, 01 April 2025
Time: 11:00 CEST - 12:30 CEST
Location / Room: Rhône 1

Session chair:
Ulf Schlichtmann, TU Munich, DE

Session co-chair:
Holger Blume, Leibniz University Hannover, DE

Organisers:
Norbert Wehn, University of Kaiserslautern-Landau, DE
Lukas Krupp, University of Kaiserslautern-Landau, DE

Time Label Presentation Title
Authors
11:00 CEST FS06.1 PANEL: IMPROVING CHIP DESIGN ENABLEMENT FOR UNIVERSITIES IN EUROPE

Speaker :
Norbert Wehn, RPTU University of Kaiserslautern-Landau, DE

Authors
:
Matthew Venn 1 , Joachim Rodrigues 2 , David Atienza 3 , Ian O'Connor 4 , Andreas Brüning 5  and Patrick Haspel 6
1 Tiny Tapeout, ES;  2 Lund University, SE;  3 EPFL, CH;  4 Lyon Institute of Nanotechnology, FR;  5 FMD, DE;  6 Synopsys, DE

Abstract

The semiconductor industry is central to the European economy, particularly in the industrial and automotive sectors. Semiconductor fabrication and chip design are the two largest segments of the microelectronics value chain. While Europe is strengthening semiconductor fabrication and technology with considerable investments, e.g., in new fabs, chip design capabilities fall far short of the required capacities. The EU MicroElectronics Training, Industry and Skills (METIS) Report 2023 has shown that chip designers are the job profiles identified as the most difficult to find in the European microelectronics industry. European universities face many challenges hindering their ability to produce skilled graduates and contribute to the semiconductor ecosystem. While student interest in, e.g., AI is booming, we observe a decreasing interest in microelectronics. The main reasons for this are the high entry barriers for students, reinforced by the lack of chip design enablement in academia. Hence, there are ongoing initiatives in different European countries, on the EU level, and worldwide to strengthen chip design education and research. This focus session will bring together stakeholders of these initiatives from Europe and the USA to explore the critical challenges, opportunities, and potential strategies facing chip design enablement in European academic institutions. The session will be held in the panel format with active audience participation to guarantee inclusiveness and foster a broad view of the topic.


Jan 24, 2024

[C4P] RISC-V Summit Europe



The RISC-V Summit Europe is the premier event that connects the European movers and shakers - from industry, government, research, academia and ecosystem support - that are building the future of innovation on RISC-V.
RISC-V, the open standard instruction set architecture (ISA), is enabling a range of new applications and research that will define the future of computing in Europe. The region has been central to RISC-V’s success, with one-third of RISC-V’s global community based in Europe. 
RISC-V Summit Europe takes place from Monday 24th to Friday 28th June, 2024. The combination of strong industrial and academic communities is key to the success of RISC-V in Europe, and for this reason the conference is designed to help attendees to explore both commercial and research applications.

Present your work
Presentations on inspirational ideas and technical progress are invited to present 
at RISC-V Summit Europe.

RISC-V Summit Europe brings together developers, architects, technical decision and policy makers from across the European RISC-V ecosystem. Attendees from academia, research, SMEs, industry, and open source communities will come together to exchange knowledge, ideas, technologies, and research, shaping the future of RISC-V computing in Europe.

Taking place from June 24-28, 2024, the event will have a single track of keynotes, invited and selected talks, alongside an exhibition showcasing the latest developments across industry and research, including technology demonstrations and poster sessions. Submissions are invited either for:
🚀  Industry Sessions
Exciting large-scale research efforts, announcement and success-stories.
👩‍🔬  R&D Sessions

Leading edge academic and industry research & development insights.


Important dates
  • Abstract submission deadline: March 15th, 2024, AoE (Anywhere on Earth).
  • Author notification: April 29th, 2024.
  • Final abstract PDF and slides deadline: May 31st, 2024 AoE.
  • Poster PDF deadline: June 14, 2024 AoE.
  • RISC-V Summit Europe: June 24-28, 2024, Munich.
The Steering Committee aims to provide a limited budget for stipends. More information will be available on the conference website before the submission deadline.


Feb 9, 2023

[C4P] RISC-V Summit Europe

RISC-V Summit in Barcelona

On 5-9th June, in Barcelona, RISC-V Summit Europe brings together developers, architects, technical decision and policy makers from across European RISC-V ecosystem. Attendees from academia, research, SMEs, industry and open source communities will gather to exchange knowledge, ideas, technologies, and research shaping the future of RISC-V computing.

The event will include a single track of keynotes, invited and selected talks alongside an exhibition showcasing the latest developments across industry and research including technology demonstrations and poster sessions.

RISC-V Summit Europe is an opportunity not to be missed, come to Barcelona from 5-9th June 2023 to be part of the new wave of European computing innovation!

Call for Submissions

RISC-V Summit Europe brings together developers, architects, technical decision and policy makers from across the European RISC-V ecosystem. Attendees from academia, research, SMEs, industry, and open source communities will come together to exchange knowledge, ideas, technologies, and research shaping the future of RISC-V computing in Europe.

The event will have a single track of keynotes, invited and selected talks alongside an exhibition showcasing the latest developments across industry and research, including technology demonstrations and poster sessions. We invite blind submissions related to RISC-V addressing the following technical topics of interest:

    Automotive
    Cloud computing
    Compilation and code optimization
    Embedded systems, IoT, edge computing
    Hardware/software co-design
    High-performance computing
    Open EDA tools
    Open-source hardware and open silicon
    Operating system and software ecosystem
    RISC-V related educational activities
    RISC-V ISA extensions
    Systems-on-Chip, including processor cores, accelerators, peripherals
    Security and functional safety
    Verification
    Any other topic related to RISC-V and open hardware


We also welcome non-blind submissions related to:

    Commercial applications for real world deployment
    Policies, strategies, business and industry trends
    Publicly funded projects presentations and/or results


Important dates:

    Abstract submissions hard deadline: Monday, March 13th, 2023, AOE.
    Author notifications: Monday, April 24th, 2023, AOE.
    Final abstract version, de-anonymized, deadline: Thursday, Monday May 1st, 2023, AOE.
    Final slides and poster deadline: Thursday, June 1st, 2023, AOE.
    RISC-V Summit Europe: 5-9 June, 2023, Barcelona.