[paper] Bendable non-silicon RISC-V microprocessor

Emre Ozer, Jedrzej Kufel, Shvetank Prakash2, Alireza Raisiardali, Olof Kindgren3, Ronald Wong,
Nelson Ng, Damien Jausseran, Feras Alkhalil, David Kong2, Gage Hills2, Richard Price
and Vijay Janapa Reddi2

Bendable non-silicon RISC-V microprocessor

Nature, vol. 634, pp. 341–346 (2024) 

DOI: 10.1038/s41586-024-07976-y

1 Pragmatic Semiconductor, Cambridge, UK
2 Harvard University, Cambridge, MA, USA

3 Qamcom, Karlstad, Sweden

Abstract: Semiconductors have already had a very profound effect on society, accelerating scientific research and driving greater connectivity. Future semiconductor hardware will open up new possibilities in quantum computing, artificial intelligence and edge computing, for applications such as cybersecurity and personalized healthcare. By nature of its ethos, open hardware provides opportunities for even greater collaboration and innovations across education, academic research and industry. Here we present Flex-RV, a 32-bit microprocessor based on an open RISC-V instruction set fabricated with indium gallium zinc oxide thin-film transistors on a flexible polyimide substrate, enabling an ultralow-cost bendable microprocessor. Flex-RV also integrates a programmable machine learning (ML) hardware accelerator inside the microprocessor and demonstrates new instructions to extend the RISC-V instruction set to run ML workloads. It is implemented, fabricated and demonstrated to operate at 60kHz consuming less than 6mW power. Its functionality when assembled onto a flexible printed circuit board is validated while executing programs under flat and tight bending conditions, achieving no worse than 4.3% performance variation on average. Flex-RV pioneers an era of sub-dollar open standard non-silicon 32-bit microprocessors and will democratize access to computing and unlock emerging applications in wearables, healthcare devices and smart packaging.

FIG a. Layout of the 9×6 mm2 test chip containing two Flex-RV microprocessors

b. The FlexPCB on which the die is assembled.

Data availability
Source data are provided with this paper.

Code availability

Serv is an open-source CPU, which is freely available at GitHub (https://github.com/olofk/serv). The source code of the test benchmarks, the changes made in the Serv CPU Verilog code, and the Verilog code of the ML hardware accelerator are available from the corresponding author upon request.

[paper] Insights from Basilisk

Philippe Sauter∗, Thomas Benz∗, Paul Scheffler∗ , Frank K. Gurkaynak∗ , Luca Benini∗†

Insights from Basilisk:

Are Open-Source EDA Tools Ready for a Multi-Million-Gate, Linux-Booting RV64 SoC Design?

arXiv:2405.04257v2 [cs.AR] 8 May 2024

* Integrated Systems Laboratory, ETH Zurich, Switzerland
† Department of Electrical, Electronic, and Information Engineering, University of Bologna, Italy

Abstract: Designing complex, multi-million-gate application specific integrated circuits requires robust and mature electronic design automation (EDA) tools. We describe our efforts in enhancing the open-source Yosys+Openroad EDA flow to implement Basilisk, a fully open-source, Linux-booting RV64GC system-onchip (SoC) design. We analyze the quality-of-results impact of our enhancements to synthesis tools, interfaces between EDA tools, logic optimization scripts, and a newly open-sourced library of optimized arithmetic macro-operators. We also introduce a streamlined physical design flow with an improved power grid and cell placement integration. Our Basilisk SoC design was taped out in IHP’s open 130 nm technology. It achieves an operating frequency of 77 MHz (51 logic levels) under typical conditions, a 2.3 improvement compared to the baseline open-source EDA flow, while also reducing logic area by 1.6. Furthermore, tool runtime was reduced by 2.5, and peak RAM usage decreased by 2.9. Through collaboration with EDA tool developers and domain experts, Basilisk establishes solid "proof of existence" for a fully open-source EDA flow used in designing a competitive multi-million-gate digital SoC.

FIG: Layout files produced by running the original Iguana flow (a) and of Basilisk (b).

TABLE: KEY METRICS OF BASILISK

Logic area (NAND2)	1.1 MGE
Logic levelsa	51 LL
Technology	130 nm IHP
Operating frequency	77 MHz
SRAM memory	172 KiB (24 macros)
Chip / core area	39 mm / 21 mm
IO count	69

^aNumber of logic gates in the longest path

Acknowledgement: We thank Alan Mishchenko, Masahiro Fujita, Giovanni De Micheli, Andrea Costamagna, Alessandro Tempia Calvino, Osama Hammad Abdel Reheem, Matt Liberty, Martin Poviser, the Yosys team, Beat Muheim, and Zerun Jiang, for their valuable contributions to the research project. We further thank all contributors to the OS EDA tools.

We are deeply grateful to IHP for their generous support and providing us with the opportunity for an open-source tapeout of this scale.
This work was supported in part through the TRISTAN (101095947) project that received funding from the HORIZON KDT-JU programme

[C4P] RISC-V Summit Europe

https://riscv-europe.org/summit/2024/

The RISC-V Summit Europe is the premier event that connects the European movers and shakers - from industry, government, research, academia and ecosystem support - that are building the future of innovation on RISC-V.

RISC-V, the open standard instruction set architecture (ISA), is enabling a range of new applications and research that will define the future of computing in Europe. The region has been central to RISC-V’s success, with one-third of RISC-V’s global community based in Europe. 

RISC-V Summit Europe takes place from Monday 24th to Friday 28th June, 2024. The combination of strong industrial and academic communities is key to the success of RISC-V in Europe, and for this reason the conference is designed to help attendees to explore both commercial and research applications.

Present your work

Presentations on inspirational ideas and technical progress are invited to present 

at RISC-V Summit Europe.

RISC-V Summit Europe brings together developers, architects, technical decision and policy makers from across the European RISC-V ecosystem. Attendees from academia, research, SMEs, industry, and open source communities will come together to exchange knowledge, ideas, technologies, and research, shaping the future of RISC-V computing in Europe.

Taking place from June 24-28, 2024, the event will have a single track of keynotes, invited and selected talks, alongside an exhibition showcasing the latest developments across industry and research, including technology demonstrations and poster sessions. Submissions are invited either for:

🚀  Industry Sessions Exciting large-scale research efforts, announcement and success-stories.

👩‍🔬  R&D Sessions Leading edge academic and industry research & development insights.

Important dates

• Abstract submission deadline: March 15th, 2024, AoE (Anywhere on Earth).
• Author notification: April 29th, 2024.
• Final abstract PDF and slides deadline: May 31st, 2024 AoE.
• Poster PDF deadline: June 14, 2024 AoE.
• RISC-V Summit Europe: June 24-28, 2024, Munich.

The Steering Committee aims to provide a limited budget for stipends. More information will be available on the conference website before the submission deadline.

[paper] ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors

ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation

Alessandro Ottaviano1, Robert Balas1, Giovanni Bambini2, Antonio del Vecchio2, Maicol Ciani2, Davide Rossi2, Luca Benini1,2 and Andrea Bartolini2

DOI: 10.21203/rs.3.rs-2525734/v1

1 Integrated Systems Laboratory, ETH Zurich, Gloriastrasse 35, Zurich, 8092, Switzerland.
2 DEI, University of Bologna, Viale Del Risorgimento 2, Bologna, 40136, Italy

Abstract: High-Performance Computing (HPC) processors are nowadays integrated Cyber-Physical Systems demanding complex and high-bandwidth closed-loop power and thermal control strategies. To efficiently satisfy real-time multi-input multi-output (MIMO) optimal power requirements, high-end processors integrate an on-die power controller system (PCS). While traditional PCSs are based on a simple microcontroller (MCU)-class core, more scalable and flexible PCS architectures are required to support advanced MIMO control algorithms for managing the ever-increasing number of cores, power states, and process, voltage, and temperature variability. This paper presents ControlPULP, an open-source, HW/SW RISC-V parallel PCS platform consisting of a single-core MCU with fast interrupt handling coupled with a scalable multicore programmable cluster accelerator and a specialized DMA engine for the parallel acceleration of real-time power management policies. ControlPULP relies on FreeRTOS to schedule a reactive power control firmware (PCF) application layer. We demonstrate ControlPULP in a power management use-case targeting a next-generation 72-core HPC processor. We first show that the multicore cluster accelerates the PCF, achieving 4.9x speedup compared to single-core execution, enabling more advanced power management algorithms within the control hyper-period at a shallow area overhead, about 0.1% the area of a modern HPC CPU die. We then assess the PCS and PCF by designing an FPGA based, closed-loop emulation framework that leverages the heterogeneous SoCs paradigm, achieving DVFS tracking with a mean deviation within 3% the plant’s thermal design power (TDP) against a software-equivalent model-in-the-loop approach. Finally, we show that the proposed PCF compares favorably with an industry grade control algorithm under computational-intensive workloads.

• https://github.com/Arm-software/SCP-firmware
• https://github.com/open-power
• https://github.com/pulp-platform/control-pulp 
• https://github.com/openhwgroup/cv32e40p
• https://github.com/pulp-platform/clic
• https://github.com/EEESlab/examon
• https://buildroot.org/

FIG: ControlPULP hardware architecture. On the left, the manager domain with the manager core and surrounding peripherals. On the right, the cluster domain accelerator with the eight cores (workers)

 

[C4P] RISC-V Summit Europe

On 5-9th June, in Barcelona, RISC-V Summit Europe brings together developers, architects, technical decision and policy makers from across European RISC-V ecosystem. Attendees from academia, research, SMEs, industry and open source communities will gather to exchange knowledge, ideas, technologies, and research shaping the future of RISC-V computing.

The event will include a single track of keynotes, invited and selected talks alongside an exhibition showcasing the latest developments across industry and research including technology demonstrations and poster sessions.

RISC-V Summit Europe is an opportunity not to be missed, come to Barcelona from 5-9th June 2023 to be part of the new wave of European computing innovation!

Call for Submissions

RISC-V Summit Europe brings together developers, architects, technical decision and policy makers from across the European RISC-V ecosystem. Attendees from academia, research, SMEs, industry, and open source communities will come together to exchange knowledge, ideas, technologies, and research shaping the future of RISC-V computing in Europe.

The event will have a single track of keynotes, invited and selected talks alongside an exhibition showcasing the latest developments across industry and research, including technology demonstrations and poster sessions. We invite blind submissions related to RISC-V addressing the following technical topics of interest:

    Automotive
    Cloud computing
    Compilation and code optimization
    Embedded systems, IoT, edge computing
    Hardware/software co-design
    High-performance computing
    Open EDA tools
    Open-source hardware and open silicon
    Operating system and software ecosystem
    RISC-V related educational activities
    RISC-V ISA extensions
    Systems-on-Chip, including processor cores, accelerators, peripherals
    Security and functional safety
    Verification
    Any other topic related to RISC-V and open hardware

We also welcome non-blind submissions related to:

    Commercial applications for real world deployment
    Policies, strategies, business and industry trends
    Publicly funded projects presentations and/or results

Important dates:

    Abstract submissions hard deadline: Monday, March 13th, 2023, AOE.
    Author notifications: Monday, April 24th, 2023, AOE.
    Final abstract version, de-anonymized, deadline: Thursday, Monday May 1st, 2023, AOE.
    Final slides and poster deadline: Thursday, June 1st, 2023, AOE.
    RISC-V Summit Europe: 5-9 June, 2023, Barcelona.
 

 

 

 

VSD Free Webinar - Mixed-signal RISC-V based SoC on FPGA - 23rd July, 7pm IST

 

This 60-min webinar helps you get started with a basic mixed-signal FPGA flow, which can be extended to any complex SoC.VSD and RedwoodEDA conducts 5-day RISC-V based MYTH (Microprocessors for You in Thirty Hours) workshop using transaction level Verilog on Makerchip platform. For people who have done this workshop can use this webinar as an extension to the 5th Day, where RISC-V pipe-lined CPU coded in TL-Verilog is now converted to Verilog language and is a part of a mixed-signal SoC

If you are from ASIC/Physical design back-ground, this webinar will complement your existing work, and you would really get to know similarities and differences between ASIC and FPGA flow, which one is preferred under what conditions and why is it preferred

This single webinar connects VLSI students, analog designers, FPGA designers and ASIC designers. It is also an attempt to bring everyone on the same platform, and serves as a starting point for design verification

Stay tuned for follow-up series of FPGA webinars and 5-day hands-on high intensity FPGA workshop, which will be built around OpenFPGA framework and Makerchip visualization software, that enables the whole community to learn FPGA fundamentals along with labs, without actually having a physical FPGA board.

Agenda:

1. "FPGA on eSim"
   Guest Speaker - Prof. Kannan M Moudgalya, IIT Bombay
2. "chipIgnite Program"
   Guest Speaker - Mike Wishart, CEO eFabless
3. "Tapeout World Program"
   Guest Speaker - Naveed Sherwani, Chairman, OSFPGA
4. "Mixed-signal RISC-V based SoC on FPGA"
   Webinar Instructor - Shivani Shah

Webinar Curriculum:
1) Introduction
2) RVMYTH RISC-V Core
3) Why FPGAs ?
4) TL - Verilog to RTL verilog using Makerchip
5) Functional Simulation using iverilog
6) FPGA - Steps to create project
7) FPGA - Steps to generate IPs
8) FPGA - RTL simulation
9) FPGA - Synthesis
10) FPGA - Implementation and timing analysis
11) FPGA - Bit-stream generation, FPGA programming and ILA
12) Conclusion

Register here (if you don't see the form, please refresh page):
https://lnkd.in/gByg6fZ