[paper] Cryo FD SOI LNA Design

Giovani Britton, Salvador Mir, Estelle Lauga-Larroze, Benjamin Dormieu, Jose Lugo, Joao Azevedo, Sebastien Sadlo, Quentin Berlingard, Mikael Casse, Philippe Galy

Using DC transistor characterization measurements for LNA design at cryogenic temperatures

(2026) researchsquare.com

DOI: 10.21203/rs.3.rs-7754596/v1

1. STMicroelectronics, Crolles (F)
2. Univ. Grenoble Alpes, CNRS, Grenoble-INP, TIMA, Grenoble (F)
3. Univ. Grenoble Alpes, CEA-Leti, Grenoble (F)
4. Univ. Grenoble Alpes, CNRS, Grenoble-INP, IMEP-LAHC, Grenoble (F)

Abstract: The design of Radio Frequency (RF) cryogenic circuits has attracted much interest in recent years due to applications such as quantum computers. Interface electronics with ultra-low levels of power consumption at temperatures as low as 4 K are required. Silicon technologies are being considered for implementation because of the possibility of large-scale qubit integration with energy-efficient readout and control interfaces. However, the design of RF cryogenic circuits is complicated because of the lack of standard design kits with the corresponding component models for their simulation at these temperatures. Alternative approaches to avoid costly design and fabrication cycles are possible, in particular the use of Look-Up-Table (LUT) based techniques that exploit characterization data of circuit components at cryogenic temperature. In this paper, we make use of this approach for the design of a RF Low Noise Amplifier (LNA) using a 28 nm FD-SOI technology that has been characterized at cryogenic temperatures1using DC measurements. Furthermore, we also experimentally demonstrate that the DC measurements used are valid to extract the transistor noise parameters used in the LUT-based analysis.

Fig: Measurement of: (a) transconductance gm, and (b) threshold voltage Vth 

for the 28nm FD-SOI technology, from 300K down to 4K.

Acknowledgements: This work was supported by the French CIFRE program and the Labex MINOS of French program ANR-10-LABX-55-01.

[paper] Model for Cryo-CMOS Subthreshold Swing

Arnout Beckers, Jakob Michl, Alexander Grill, Member IEEE; Ben Kaczer, Marie Garcia Bardon, Bertrand Parvais, Bogdan Govoreanu, Kristiaan De Greve, Gaspard Hiblot, 

and Geert Hellings, Senior Member IEEE

Physics-Based and Closed-Form Model for Cryo-CMOS Subthreshold Swing

in IEEE Transactions on Nanotechnology, vol. 22, pp. 590-596, 2023,

DOI 10.1109/TNANO.2023.3314811.

IMEC, Leuven (B)

Institute for Microelectronics, TU Vienna (A)

Vrije Universiteit Brussel (B)

KU Leuven (B)

Abstract: Cryogenic semiconductor device models are essential in designing control systems for quantum devices and in benchmarking the benefits of cryogenic cooling for high-performance computing. In particular, the saturation of subthreshold swing due to band tails is an important phenomenon to include in low-temperature analytical MOSFET models, as it predicts theoretical lower bounds on the leakage power and supply voltage in tailored cryogenic CMOS technologies with tuned threshold voltages. Previous physics-based modeling required to evaluate functions with no closed-form solutions, defeating the purpose of fast and efficient model evaluation. Thus far, only the empirically proposed expressions are in closed form. This article bridges this gap by deriving a physics-based and closed-form model for the full saturating trend of the subthreshold swing from room down to low temperature. The proposed model is compared against experimental data taken on some long and short devices from a commercial 28-nm bulk CMOS technology down to 4.2 K.

FIG: (a) TEM picture of a mature imec technology node. (b) Electrostatic potential fluctuations near the channel/oxide interface. (c) Gaussian distributed depths of the potential wells. (d) Including the binding energy in the wells in the quantum picture gives a Laplace distribution of P(Eb). (e-f) Convolution (*) of P(Eb) with the sharp-edged 2-D DOS leads to a logistic/Fermi-like DOS function with an exponential tail.