Showing posts with label
RISC-V
.
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Showing posts with label
RISC-V
.
Show all posts
Nov 20, 2024
[paper] Bendable non-silicon RISC-V microprocessor
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Emre Ozer, Jedrzej Kufel, Shvetank Prakash2, Alireza Raisiardali, Olof Kindgren3, Ronald Wong, Nelson Ng, Damien Jausseran, Feras Alkhalil, ...
May 14, 2024
[paper] Insights from Basilisk
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Philippe Sauter∗, Thomas Benz∗, Paul Scheffler∗ , Frank K. Gurkaynak∗ , Luca Benini∗† Insights from Basilisk: Are Open-Source EDA Tools Read...
Jan 24, 2024
[C4P] RISC-V Summit Europe
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https://riscv-europe.org/summit/2024/ The RISC-V Summit Europe is the premier event that connects the European movers and shakers - f...
Feb 27, 2023
[paper] ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors
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ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal ...
Feb 9, 2023
[C4P] RISC-V Summit Europe
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On 5-9th June, in Barcelona, RISC-V Summit Europe brings together developers, architects, technical decision and policy makers from acr...
Jul 17, 2021
VSD Free Webinar - Mixed-signal RISC-V based SoC on FPGA - 23rd July, 7pm IST
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This 60-min webinar helps you get started with a basic mixed-signal FPGA flow, which can be extended to any complex SoC.VSD and RedwoodEDA...
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