[paper] dual metal InAs-GaSb VTFETs

M. Saravanan, Eswaran Parthasarathy, Shiromani Balmukund Rahi and Ramkumar Natarajan

Impact of drain and source engineering on dual metal InAs-GaSb VTFETs
with high-K gate stack design

Sci Rep 15, 44796 (2025) DOI: 10.1038/s41598-025-28448-x

Department of Electronics and Communication Engineering, Sri Eshwar College of Engineering, Coimbatore, 641202, India
Department of Electronics and Communication Engineering, SRM Institute of Science and Technology, Kattankulathur, 603203, India
University School of Information and Communication Technology, Gautam Buddha University, Greater Noida, 201312, Uttar Pradesh, India
Department of Electronics and Communication Engineering, SR University, Warangal, 506371, Telangana, India

Abstract: The performance of a Dual-Metal-InAs-GaSb Vertical Tunnel Field Effect Transistor (DM-InAs-GaSb VTFET) with an InAs source pocket was investigated in relation to the gate dielectric materials. This research chose gate dielectric materials such as SiO2, Al2O3, HfO2, and ZrO2. The simulation is performed using the Silvaco Technology Computer-Aided Design (TCAD) software. The drain current (ION) of the DM-InAs-GaSb VTFET, which includes an InAs source pocket and an extended drain, is assessed across several dielectric materials; still, ZrO2 (7.92 × 10− 5 A/µm) and HfO2 (8.15 × 10− 5 A/µm) demonstrate enhanced performance. The transconductance (gm) values were 606 µS/µm for HfO2 and 589 µS/µm for ZrO2. A comparison is performed between the Ge-Si VTFET and the suggested configuration. The proposed DM-InAs-GaSb VTFET demonstrates a 1.5-times increase in ON current (ION) and a three-time boost in transconductance (gm). The frequency response of the proposed device was evaluated by employing its SPICE characteristics to construct the common source amplifier in the SPICE circuit simulator. This amplifier comparison reveals that ZrO2 and HfO2 insulators provide significant gain, with HfO2 displaying a cut-off frequency of 1.808 GHz.

FIG: Cross-sectional schematic (a) DM-InAs-GaSb VTFET with split drain (Device-A),
(b) DM-InAs-GaSb VTFET with reduced channel (Device-B),
(c) DM-InAs-GaSb VTFET with drain extension (Device-C).

Acknowledgements: The authors acknowledge the SRM Institute of Science and Technology, Kattankulathur, Chennai, India for providing the support and facility to carry out this research work.

[paper] Vertical III-V Nanowire MOSFETs on Si

Olli-Pekka Kilpi, Markus Hellenbrand, Johannes Svensson, Axel R. Persson, Reine Wallenberg, Erik Lind, Member, IEEE, and Lars-Erik Wernersson

High-Performance Vertical III-V Nanowire MOSFETs on Si With gm > 3 mS/μm

in IEEE EDL vol. 41, no. 8, pp. 1161-1164, Aug. 2020

DOI: 10.1109/LED.2020.3004716

Abstract: Vertical III-V nanowire MOSFETs have demonstrated excellent performance including high transconductance and high Ion. One main bottleneck for the vertical MOSFETs is the large access resistance arising from the contacts and ungated regions. We demonstrate a process to reduce the access resistance by combining a gate-last process with ALD gate-metal deposition. The devices demonstrate fully scalable gm down to Lg = 25 nm. These vertical core/shell InAs/InGaAs MOSFETs demonstrate gm = 3.1 mS/μm and Ron = 190 μm. This is the highest gm demonstrated on Si. Transmission line measurement verifies a low contact resistance with RC = 115 μm, demonstrating that most of the MOSFET access resistance is located in the contact regions.

FIG: (a) of the MOSFET structure demonstrating benefit of the TiN gate metal;

(b )output characteristics of the vertical nanowire MOSFET 

with 90 nanowires, LG = 25 nm and diameter 17 nm.

Acknowledgment: This work was supported in part by the Swedish Research Council, in part by the Knut and Alice Wallenberg Foundation, in part by the Swedish Foundation for Strategic Research, and in part by the European Union H2020 Program INSIGHT under Grant 688784.