[paper] Roadmap for Schottky Barrier Transistors

Eva Bestelink1*, Giulio Galderisi2, Patryk Golec1, Yi Han3, Benjamin Iniguez4, Alexander Kloes5, Joachim Knoch6, Hiroyuki Matsui7, Thomas Mikolajick2,8, Kham M. Niang9, Benjamin Richstein6, Mike Schwarz5, Masiar Sistani10, Radu A. Sporea1, Jens Trommer2, Walter M. Weber10,
Qing-Tai Zhao3 and Laurie E. Calvet11

Roadmap for Schottky Barrier Transistors

IOP Nano Futures in press (2024)

DOI: 10.1088/2399-1984/ad92d1

1 Advanced Technology Institute, University of Surrey, Guildford, UK
2 Namlab gGmbH, Nöthnitzer Str. 64a, 01187 Dresden, Germany
3 Peter Grünberg Institute, Forschungszentrum Jülich, 52428 Jülich, Germany
4 DEEEA, Universitat Rovira I Virgili, Tarragona, Spain,
5 NanoP, THM University of Applied Sciences, 35390 Giessen, Germany,
6 Institute of Semiconductor Electronics, RWTH Aachen University, Germany
7 Research Center for Organic Electronics (ROEL), Yamagata University, Japan
8 Chair for Nanoelectronics, TU Dresden, Germany
9 Electrical Engineering, Cambridge University, UK
10 Institute of Solid State Electronics, TU Wien, Vienna, Austria
11 LPICM, CNRS-Ecole Polytechnique, IPP, 91120 Palaiseau, France

Abstract: In this roadmap we consider the status and challenges of technologies that use the properties of a rectifying metal-semiconductor interface, known as a Schottky barrier, as an asset for device functionality. We discuss source gated transistors, which allow for excellent electronic characteristics for low power, low frequency environmentally friendly circuits. Also considered are reconfigurable field effect transistors, where the presence of two or more independent gate electrodes can be used to program different functionalities at the device level, providing an important option for ultrasecure embedded devices. Both types of transistors can be used for neuromorphic systems, notably by combining them with ferroelectric Schottky barrier transistors, which enable a large number of analog states. At cryogenic temperatures, SB transistors can advantageously serve for the control electronics in quantum computing devices. If the source/drain of the metallic contact becomes superconducting, Josephson junctions with a tunable phase can be realized for scalable quantum computing applications. Developing applications using Schottky barrier devices requires physicsbased and compact models that can be used for circuit simulations, which are also discussed. The roadmap reveals that the main challenges for these technologies are improving processing, access to industrial technologies and modeling tools for circuit simulations.

Fig: Illustration of the different applications of the SB Devices

Aknowleegements: RAS and EB acknowledge support from the Engineering and Physical Sciences Research Council (EPSRC) under Grants EP/V002759/1, EP/R028559/1, and EP/R511791/1, and from the Royal Society of Great Britain under Grants IES\R2\202056, IES\R3\193072, IEC\R3\183042, and IES\R3\170059. JT and GG are supported from the European Union’s Horizon Europe research and innovation programme under grant agreement No 101135316, SENSOTERIC. LEC and BI are supported from the European Union’s Horizon Europe research and innovation program under grant agreement No 101099555, BAYFLEX. Q-T Zhao, Y. Han, B. Richstein and J. Knoch gratefully acknowledge support from Deutsche Forschungsgemeinschaft under grant nos. KN 545/28, KN 545/29, and ZH-639/3. Q-T Zhao acknowledges partially support by the German BMBF project “NeuroTEC” (16ME0398K). KMN acknowledges support from the Engineering and Physical Sciences Research Council (EPSRC) under Grants EP/M013650/1 and EP/W009757/1. LEC acknowledges funding from the ANR under contract ANR-21-FAI1-0006-01.

[paper] Schottky Barrier FET at Deep Cryogenic Temperatures

Christian Roemer^1,2, Nadine Dersch¹, Ghader Darbandy¹, Mike Schwarz¹,

Yi Han³, Qing-Tai Zhao³, Benjamın Iniguez² and Alexander Kloes¹

Compact Modeling of Schottky Barrier Field-Effect Transistors 

at Deep Cryogenic Temperatures

EUROSOI-ULIS 2023

in Tarragona (Catalonia, Spain) on May 10-12 2023

1 NanoP, TH Mittelhessen - University of Applied Sciences, Giessen, Germany
2 DEEEA, Universitat Rovira i Virgili, Tarragona, Spain
3 Peter-Grunberg-Institute (PGI 9), Forschungszentrum Julich, Germany

Abstract: In this paper, a physics-based DC compact model for Schottky barrier field-effect transistors at deep cryogenic temperatures is presented. The model uses simplified tunneling equations at temperatures of ϑ ≈ 0 K in order to calculate the field emission injection current at the device’s Schottky barriers. The compact model is also compared to and verified by measurements of ultra-thin body and buried oxide SOI Schottky barrier field-effect transistors and is able to capture the signature of resonant tunneling effects in the transfer characteristics.

FIG: Band diagram at the source side Schottky junction (left-hand side). The solid blue line is the conduction band of the channel and the blue dashed line shows the metal’s Fermi energy level. The right-hand side subplot shows the tunneling probability, with the exponential part (red line) and the total probability, including the oscillations (green line).

[paper] Three-Gated Reconfigurable FETs

Giulio Galderisi, Christoph Beyer, Thomas Mikolajick, and Jens Trommer 

Insights into the Temperature Dependent Switching Behaviour of Three-Gated Reconfigurable Field Effect Transistors 

physica status solidi (a) DOI: 10.1002/pssa.202300019

NaMLab gGmbH Dresden (D) 

TU Dresden, Chair of Nanoelectronics, Dresden (D) 

Abstract: Three-Gated Reconfigurable Field Effect Transistors are innovative nanoelectronic devices that are rapidly and increasingly attracting substantial interest in several fields of application thanks to their inherent n-type/p-type reconfiguration capabilities. For this reason, it is of significant importance to acquire a deeper knowledge about the temperature ranges in which such devices can be operated and, at the same time, gather a better understanding of the physical mechanisms that are involved in their operation. To achieve this aim, in-depth observations about the functioning of such devices in an ultra-wide temperature range, spanning from 80 K to 475 K, were performed and are presented for their ambipolar and lowVT operation modes. In view of the data exhibited in this work, it is possible to assess the performances of Three-Gated Reconfigurable Field Effect Transistors within a considerable temperature span and finally provide significant insights on the temperature dependent physical mechanisms regulating their functionality.

FIG: a) Typical Three-Gated RFET transfer characteristic, showing both p-/n-type curves for lowVT and highVT operations together with the ambipolar mode. b) Cross-sectional depiction of a Three-Gated RFET. c) False-colored SEM image of fabricated RFET device, based on 60 nm wide nanochannel. d) Schematic band diagrams of the most relevant operation modes of a Three-Gated RFET: off-states for both lowVT and highVT modes are shown, together with the on-state, which is the same for both operations. e) Table summarizing the possible RFET operations: the highlighted ones will be analyzed in this paper. f) Three-Gated RFET fabrication process flow. g) Ambipolar transfer curves for p/n-type branches, obtained on a different set of devices: the shaded area around the solid line (mean) shows the standard deviation calculated on 50 measured devices. h,i) P-type and n-type transfer curves of the lowVT mode for different values of the drain voltage. l,m) P-type and n-type transfer curves of the lowVT mode for different values of the program voltage. In m) it is possible to observe a shift in the VT when the device is programmed at 1 V: this non-ideality is probably due to traps generated in the gate oxide during measurement. 

Acknowledgements: This work was supported in part by the State budget by the delegates of the Saxon State Parliament and in part by the German Research Foundation (DFG) within the projects number 326384402 and SPP2253 under project number 439891087. 

[paper] TFT XNOR/XOR Circuit

E. Bestelink, O. de Sagazan*, I. S. Pesch and R. A. Sporea

Compact Unipolar XNOR/XOR Circuit Using Multimodal Thin-Film Transistors

in IEEE TED, vol. 68, no. 10, pp. 4951-4955, Oct. 2021,

DOI: 10.1109/TED.2021.3103491.

  

Advanced Technology Institute, University of Surrey (UK)

* IETR-DMM-UMR6164, University of Rennes (F)

Abstract: A novel compact realization of the XNOR/ XOR function is demonstrated with multimodal transistors (MMTs). The multimodal thin-film transistors (MMT’s) structure allows efficient use of layout area in an implementation optimized for unipolar thin-film transistor (TFT) technologies, which may serve as a multipurpose element for conventional and emerging large-area electronics. Microcrystalline silicon device fabrication is complemented by physical simulations.

Fig: Micrograph of fabricated microcrystalline MMT devices and circuits. Inset: individual MMT devices with single device (MMT) and two source control gates (SUMFGMMT). Scale bars: 500μm.

Acknowledgement: Devices were fabricated on the NanoRennes platform.

CCBY - IEEE is not the copyright holder of this material. 

Program 2021: Symposium on Schottky Barrier MOS Devices

The symposium goal is to combine the activities of an enthusiastic group of Schottky barrier researchers worldwide. The topics cover all important aspects of potential applications, simulation and modeling, processing and implementation for CMOS/SOI technologies, Quantum technologies and approaches for neuromorphic applications. The content will be beneficial for anyone who needs to learn the opportunities and challenges of this technology since the first introduction by Walter Schottky in the 1938s. New aspects and future proposals to make the Schottky barrier into the main stream are welcome.

Program 2021

Wed 30.06.2021 (Virtual)

13:00-13:05	Opening IEEE DL
13:05-14:00	IEEE Distinguished Lecture: Tunneling Graphene FET Gana Nath Dash, Sambalpur University (IN) Abstract: During the last few decades, aggressive scaling in Si MOSFET (Metal Oxide Semiconductor Field Effect Transistor) architecture has given rise to several short channel effects, which in turn has set a performance limit on the device owing to constraint in Si technology. The emergence of graphene at this juncture with a host of exotic and favorable electronic properties, generated new hopes for the FET industry. While the graphene based analogue FET witnessed some advantages, the digital counterpart showed a dismal performance, primarily due to the zero bandgap of graphene (poor ON/OFF ratio). For a way out, an alternative architecture based on the quantum tunneling process is augmented with the graphene FET resulting in the new device named TGFET.
14:00-14:05	Opening SSBMOS
14:05-14:35	Germanium nanosheet and nanowire transistor technologies for beyond CMOS applications Walter M. Weber, Raphael Böckle, Lukas Wind, Kilian Eysin, Daniele Nazzari, Tatli Ezgi, Oliver Solfronk, Alois Lugstein and Masiar Sistani, Institute of Solid State Electronics, TU Vienna (A) Abstract: The ultimate downscaling limits of conventional field effect transistors calls for alternative computational methods that provide perspectives towards the enhancement of computational complexity, circuit performance and energy efficiency. In this sense germanium nano-transistors offer both an approachable access to quantum confinement effects and promising electronic transport properties that distinctly are compatible with modern CMOS fabrication flows. We will discuss the applicability of different germanium active regions and gating architectures towards the realization of computational electronics with added functionality. On top of exploring different realizations of reconfigurable transistors with programmable polarity we will discuss further functionality enhancement by enabling operability within the negative differential resistance regime at room temperature. Prospective implications at the circuit level will be discussed.
14:40-15:10	Evolving contact-controlled thin-film transistors Radu Sporea, University of Surrey (UK) Abstract: TFT designs that comprise multiple gates and rectifying source contacts can be designed to produce linear transconductance and act as robust amplifiers and signal converters. This talk outlines device design and opportunities in emerging edge processing applications.
15:10-15:50	COFFEE BREAK
15:50-16:20	Compact Modelling of Dually-Gated Reconfigurable Field-Effect Transistors Christian Römer*, Ghader Darbandy*, Mike Schwarz*, Jens Trommer**, André Heinzig**, Thomas Mikolajick**, Walter M. Weber***, Benjamín Iñíguez**** and Alexander Kloes* *NanoP, THM (DE), **namLAB, TU Dresden (DE), ***TU Vienna (A), ****DEEEA, URV (ES) Abstract: This work presents a closed-form and physics-based DC compact model, which is applicable on dually-gated reconfigurable field-effect transistors (RFETs). The presented compact model is focused on the charge-carrier injection at the device’s source and drain side Schottky barriers, which can be separated into field emission and thermionic emission current contributions. This work explains the basic equations which are used to calculate the current contributions and shows calculated device characteristics compared to measurements.
16:25-16:55	The Schottky barrier transistor in all its forms Laurie Calvet*, John P. Snyder**, Mike Schwarz*** *C2N, University Paris (FR),** JCap, LLC (USA), ***NanoP, THM (DE) Abstract: The Schottky barrier (SB) transistor, where the source and drain of a conventional planar MOSFET are replaced with metallic contacts, was first explored in the 1960s. Since then, many variations on this structure have been explored in the literature including: different semiconductors materials such as other non-organic semiconductors and nano-structures such as carbon nanotubes and nanowires. In this talk we review some of the changes in the electronic transport that are observed as the geometry and materials of the SB transistors are changed.

SB-MOS Symposium at URV Tarragona (SP)

The Symposium on Schottky Barrier MOS (SB-MOS) devices is held in the timeframe of the Graduated Students Meeting of URV on June 30th at the University Rovira i Virgili, Spain. This is the first joint R&D event between the URV and Symposium on SB-MOS.

This year the joint R&D event is sponsored by the URV, THM, the IEEE EDS Spain & Germany Chapter, and organized by Dr. Laurie Calvet (C2N, Palaiseau, France), Prof. Mike Schwarz and Prof. Alexander Kloes (NanoP THM, Germany), Prof. Lluis Marsal (DEEEA, URV), and Prof. Benjamin Iniguez (DEEEA, URV) and the staff at the URV.

Our joint R&D event starts on June 30th with the Symposium of SB-MOS. On July 1st and July 2nd the Graduated Students Meeting is held. The following speakers have confirmed their invitations to SB-MOS: Dr. Radu Sporea (Advanced Technology Institute, University of Surrey, Guildford, UK), Dr. Laurie E. Calvet (C2N, CNRS-Université Paris-Sud, France), Prof. Walter Weber (TU Vienna) and further.

Attendees are welcome to participate in our joint R&D event. Further information is present at

Symposium of SBMOS

Graduated Student Meeting

To register for the event use the vTools of IEEE with the following link:
https://meetings.vtools.ieee.org/m/272299

Important dates:

• Event Announcement/CFP: May 2021
• Final Program: June 2021
• Registration deadline: June 27, 2021
• Symposium SB-MOS devices: June 30, 2021
• Graduated Students Meeting on Electronics Engineering: July 1st - 2nd, 2021

[paper] Compact Source-Gated Sensor

Eva Bestelink, Student Member, IEEE, Kham M. Niang, Georgios Bairaktaris, Luca Maiolo, Francesco Maita, Kalil Ali, Andrew J. Flewitt, S. Ravi P. Silva

and Radu A. Sporea, Senior Member, IEEE

Compact Source-Gated Transistor Analog Circuits for Ubiquitous Sensors

In IEEE Sensors. Jul 18, 2020

Abstract: Silicon-based digital electronics have evolved over decades through an aggressive scaling process following Moore’s law with increasingly complex device structures. Simultaneously, large-area electronics have continued to rely on the same field-effect transistor structure with minimal evolution. This limitation has resulted in less than ideal circuit designs, with increased complexity to account for shortcomings in material properties and process control. At present, this situation is holding back the development of novel systems required for printed and flexible electronic applications beyond the Internet of Things. In this work we demonstrate the opportunity offered by the source-gated transistor’s unique properties for low-cost, highly functional large-area applications in two extremely compact circuit blocks. Polysilicon common-source amplifiers show 49 dB gain, the highest reported for a twotransistor unipolar circuit. Current mirrors fabricated in polysilicon and InGaZnO have, in addition to excellent current copying performance, the ability to control the temperature dependence (degrees of positive, neutral or negative) of output current solely by choice of relative transistor geometry, giving further flexibility to the design engineer. Application examples are proposed, including local amplification of sensor output for improved signal integrity, as well as temperature-regulated delay stages and timing circuits for homeostatic operation in future wearables. Numerous applications will benefit from these highly competitive compact circuit designs with robust performance, improved energy efficiency and tolerance to geometrical variations: sensor front-ends, temperature sensors, pixel drivers, bias analog blocks and high-gain amplifiers.

FIG: a) Photomicrograph of a typical polysilicon SGT fabricated; b) Driver M1 output characteristics (black curves, VGmax = -15 V, step 0.5 V) and superimposed M2 load line (orange, VG = 0 V). VSAT1 occurs as a result from pinch-off at the source and VSAT2 represents channel pinch-off of the parasitic FET. 

Acknowledgment: R.A.S. acknowledges the Royal Academy of Engineering of Great Britain for the support through the Research Fellowship (Grant No. 10216/110), the Royal Society of Great Britain through project ARES IES\R3\170059 and EPSRC for grants EP/R028559/1 and EP/R025304/1. K.M.N. and A.J.F. acknowledge the support of the Engineering and Physical Sciences Research Council (EPSRC) through project EP/M013650/1. R.A.S. thanks Prof John Shannon for technical discussions, Dr Nigel Young and Dr Michael Trainor for assistance with polysilicon device design and fabrication.

Symposium on Schottky Barrier MOS devices

“Towards neuromorphic and quantum computing applications” 

October 4, 2019, Paris (F)

organized by EDS French Chapter & Universite Paris-Sud

A symposium on Schottky Barrier MOS (SB-MOS) devices is planned for October 4th at the new Center for Nanoscience and Nanotechnology laboratory in Palaiseau, France. This is the third meeting of an enthusiastic group of Schottky barrier researchers and this year it is sponsored by LabexNanoSaclay, the IEED EDS French chapter, the Robert Bosch GmbH and Silvaco Inc.

This year the theme of the symposium is “Towards neuromorphic and quantum computing applications” organized by Dr. Laurie Calvet (C2N, Palaiseau, France), Dr. Francesca Chiodi (C2N, Palaiseau, France), Dr. Mireille Mouis (IMEP-LAHC, Grenoble INP, France) and Dr. Mike Schwarz (Robert Bosch GmbH, NanoP THM, Germany) and the staff at the Centre of Nanoscience and Nanotechnology at the Université Paris-Sud. 

The symposium starts on October 4th at 9:00 am and the following speakers have confirmed their invitations: Prof. Benjamin Iniguez (DEEEA, Universitaet Rovira I Virgili), Dr. Laurie E. Calvet (C2N, CNRS-Université Paris-Sud), Dr. Mike Schwarz (Robert Bosch GmbH, NanoP THM, Germany), Dr. David Green / Dr. Ahmed Nejim (Silvaco Inc.), Dr. John Snyder (JCAP, LLC), Dr. Francesca Chiodi (C2N, CNRS-Université Paris-Sud), Dr. François Lefloch (CEA, Grenoble), Dr. Fabrice Nemouchi (CEA, Grenoble).

Symposium on Schottky Barrier MOS Devices 2018

"devil of savior"

It is the 40th anniversary of Institut für Halbleitertechnik und Nanoelektronik (IHTN) of the TU Darmstadt, Germany. In addition to many activities in September, a small symposium on Schottky Barrier MOS (SB-MOS) devices is planned for August 7th in Darmstadt. This is the second meeting of an enthusiastic group of Schottky barrier researchers and this year it is sponsored by the EDS German chapter and hosted by the IHTN of TU Darmstadt.

This year the symposium is organized by Dr. Tillmann Krauss, Dr. Udo E. Schwalke, Dr. Mike Schwarz and the staff of the TU Darmstadt. The symposium starts at 11:00 am in the lecture hall at the ITHN TU Darmstadt. 

The following agenda is planned:






AGENDA:

11:00 – 11:15 Welcome and introduction by Prof. Schwalke
11:15 – 11:30 “Wrap-Up of Schottky Barrier Simulation Methodologies”, Dr. Mike Schwarz (Robert Bosch GmbH, NanoP THM) (15mins)
11:30 – 12:00 “DC/AC compact modeling of Tunnel-FETs”, Prof. Alexander Kloes (NanoP THM) (30mins)
12:00 – 12:30 “Benefits of Schottky Barrier vs. Conventional Doped Source/Drain MOS devices”, Dr. John Snyder (JCap, LLC) (30mins)
12:30 – 13:30 “Lunch”
13:30 – 14:00 “Nanowire Schottky devices”, Dr. Walter Weber (TU Dresden) (30mins)
14:00 – 14:30 “Nanoelectronics: From Silicon to Carbon”, Prof. Udo Schwalke (TU Darmstadt) (30mins)
14:30 – 14:45 “Coffee Break”
14:45 – 15:15 “Transfer-free fabrication of nanocrystalline graphene field-effect sensors”, Dennis Noll (TU Darmstadt) (30mins)
15:15 – 15:45 “Modeling of neuromorphic devices”, Dr. Laurie E. Calvet (Université Paris-Sud) (30mins)

Attendees are welcome to attend the symposium. Further information are present at http://www.iht.tu-darmstadt.de/ihtn_institute/

[paper] On the Physical Behavior of Cryogenic IV and III-V Schottky Barrier MOSFET Devices

On the Physical Behavior of Cryogenic IV and III–V Schottky Barrier MOSFET Devices

Mike Schwarz, Member, IEEE, Laurie E. Calvet, Member, IEEE, John P. Snyder, Member, IEEE, Tillmann Krauss, Udo Schwalke, Senior Member, IEEE, and Alexander Kloes, Senior Member, IEEE

in IEEE TED , vol.PP, no.99, pp.1-8

doi: 10.1109/TED.2017.2726899

Abstract: The physical influence of temperature down to the cryogenic regime is analyzed in a comprehensive study and the comparison of IV and III-V Schottky barrier (SB) double-gate MOSFETs. The exploration is done using the Synopsys TCAD Sentaurus device simulator and first benchmarked with experimental data. The important device physics of both SB-MOSFETs and conventional MOSFETs are reviewed. The impact of temperature on device performance down to the liquid-nitrogen regime is then explored. We find reduced drive currents in SB-MOSFETs fabricated on small effective mass materials and that SB lowering can significantly improve SB-MOSFETs, especially at low temperatures [read more...]

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