Old glories never die... do they?

It's quite hard for an old glory like HSPICE to die. See the post in aboutSpice.com:
SMIC Deploys Synopsys HSPICE Simulator for 45-nm Physical IP and Standard Cell Development (Synopsys)

Have a nice summertim

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An Insider’s View to the Swiss LP/LV CMOS Design History

Organizers: Jean-Michel Sallese; EPFL and Wladek Grabinski; GMC Consulting
Host: Predrag Habas; EM Marin

Where: EPFL - Swiss Federal Institute of Technology, Lausanne, Room CO017
When: Friday, July 3, 2009, 5:00 pm

Title: An Insider’s View to the Swiss LP/LV CMOS Design History
Presenter: Stefan Cserveny

Abstract: I worked the last 30 years at CEH - CSEM, the amazing Swiss crucible at the origin of the very low power integrated circuits, taking advantage of its highly professional, creative and enthusiastic teams and the close and fruitful collaboration with the EPFL and the Swiss industry. I will present some of these historical developments as viewed by the subjects in which I had the opportunity to add my contribution. After a short overview of my background and work done before joining the CEH, I will first present the early compact MOS modeling work done in order to satisfy the requirements for the LP/LV design including the near threshold range - a work setting the path towards the presently largely used EKV model. The following items are some of the sensor interface circuits, the realization of embedded low power non-volatile memories and, finally, the very low leakage SRAM memories essential for many critical applications.

Short Bio: Stefan Cserveny is retiring after 47 years of teaching and research and development activities as an electron device engineer and as a circuit designer, especially for designs requiring device expertise. The first 17 years he lectured electron devices and circuits at the Polytechnic Institute of Bucharest, Romania and at the Telecommunication Institute of Oran, Algeria, which he helped to create, writing several textbooks and scientific papers. In 1972 he obtained a one year specialization grant he spent at the University of California Berkeley where he received the M.S. degree in electrical engineering. In 1979 he joined the 17 years old CEH, which in 1984 became part of CSEM, getting involved with the LP/LV challenge first needed for the watch industry. In his position of scientific expert he contributed to research projects and ASIC developments; most interesting results have been published. He also participated in the BCTM technical program committee, reviewed a large number of papers and did consulting for Swiss companies.

QUCS developments

The QUCS development team is taking part in the MOS Modelling and Extraction Working Group (MOS-AK) Verilog-A standardisation initiative.

Read more...

The QUCS Team is also contributing to the MIXDES special session "Device Level Support for Emerging CMOS Technologies" organised by Daniel Tomaszewski; ITE, Poland and Wladek Grabiński; GMC Suisse (with MOS-AK/GSA Group and COMON EU Project coordination)

Read the QUCS paper's abstract: "Compact Device Modeling for Established and Emerging Technologies with the Qucs GPL Circuit Simulator"

Future Solutions of System On Chip (SoC)

Frédéric Boeuf, Principal Engineer at STM, gave a short course at the VLSI Symposium 2009 in Kyoto. It is a synthesis on the silicon technology uses for system on chip applications, and some prospect about the future solutions.

View the slide presentation...

IMEC Tips 10 nm Options at Tech Forum

I copy a post from Semiconductor International:
IMEC Tips 10 nm Options at Tech Forum: "At the IMEC Technology Forum in Brussels, Belgium, IMEC Fellow Marc Heyns presented various CMOS transistor possibilities for 15 nm and beyond. "We are at the brink of a new era of innovation," Heyns said, adding that he sees no fundamental barriers to scaling to the 10 nm node. One roadmap involves the integration of new materials and structures over time..."
(read more)