(stream now) Crowdfunding, #FOSDEM, cases, contributions and self-assembly https://t.co/WuZj64zQ92 #opensource

(stream now) Crowdfunding, #FOSDEM, cases, contributions and self-assembly https://t.co/WuZj64zQ92 #opensource

— Wladek Grabinski (@wladek60) December 30, 2018

from Twitter https://twitter.com/wladek60

December 30, 2018 at 08:03PM
via IFTTT

[mos-ak] [press note] 11th International MOS-AK Workshop, Silicon Valley, December 5, 2018

Modeling of Systems and Parameter Extraction Working Group

11th International MOS-AK Workshop

Silvaco Inc. Headquarters, Silicon Valley, December 5, 2018

Summary

The MOS-AK Compact Modeling Association, a global standardization forum for semiconductor device models, held its 11th MOS-AK Workshop at the Silvaco Inc. headquarters in Santa Clara, Calif. on December 5, 2018. The event was co-located with the 2018 IEEE International Electron Devices (IEDM) and the Q4 Compact Modeling Coalition (CMC) meetings. The workshop receives technical program co-sponsorship from the IEEE Santa Clara Valley-San Francisco Chapter of the Electron Devices Society, Europractice, IJHSES as well as NEEDS of nanoHUB.org.

Bogdan Tudor, Silvaco Inc. and Wladek Grabinski, MOS-AK, welcomed more than 30 international academic researchers and modeling engineers. The nine technical compact modeling presentations covered nanoscale technologies, semiconductor devices modeling and advanced IC design.

The MOS-AK speakers shared their latest perspectives on compact/SPICE modeling and Verilog-A standardization in response to the dynamically evolving semiconductor industry and academic R&D efforts. The event featured advanced technical presentations covering compact model development, implementation, and deployment. For more information about each of the presentations, including full abstracts, go online to MOS-AK Workshop Silicon Valley 2018.

The nine topics presented were the following:

1. Silvaco GaN HEMT Compact Modeling Perspective, Bogdan Tudor, Colin Shaw and Sungwon Kong, Silvaco, Inc.
2. GaN HEMT Devices and Modeling for Operational Electronics at Harsh Environments, Saleh Kargarrazi, XLab, Stanford University
3. Impact of Basal Plane Dislocations and Ruggedness of 10 kV 4H-SiC Transistors, Victor Veliadis, PowerAmerica, North Carolina State University
4. Direct measurement of white noise in MOSFETs, Kenji Ohmori, Device Lab Inc.
5. NEREID Technology Roadmap, Enrico Sangiorgi, NEREID, University of Bologna
6. A Physics-Based Compact Model of RRAM for Emerging Applications, Paolo Pavan, University of Modena and Reggio Emilia
7. From Physics to Power, Performance, and Parasitics, Oskar Baumgartner, Global TCAD Solutions GmbH
8. MOS-AK FOSS Compact Modeling Perspective, Wladek Grabinski, IEEE EDS DL, MOS-AK
9. Compact Model of Single TeraFET Spectrometer, Michael Shur, Rensselaer Polytechnic Institute

There were also presentations of Late News with the following topics:

1. CMC Developer Model Software Licenses, Peter Lee, Micron
2. Xyce Parallel Electronic Simulator (Ver. 6.10), Jason Verley, Sandia National Laboratories
3. Call for Papers for ESSDERC/ESSCIRC 2019 in Krakow, Wladek Grabinski, MOS-AK

Photo: Some of the participants of the 11th MOS-AK Workshop at Silvaco Inc. Headquarters in Silicon Valley.

The MOS-AK Association plans to continue its standardization efforts by organizing future compact modeling meetings, workshops and courses in India, China, Europe, USA and, for the very first time, in Latin America, throughout the coming year, including:

• FOSDEM CAD/EDA DevRoom Feb. 2-3, 2019, ULB Solbosch
• 1st MOS-AK at LAEDC Feb. 25-28, 2019, Armenia, Columbia
• 2nd MOS-AK India Conference Feb. 25-27, 2019, IIT Hyderabad
• 4th Sino MOS-AK Workshop Jun. 20-23, 2019, UECST Chengdu
• MIXDES Special CM Session June 27-29, 2019, Rzeszow
• ESSDERC/ESSCIRC Sept. 23-26, 2019, AHG Krakow

About Silvaco:
Silvaco, Inc. is a leading EDA tools and semiconductor IP provider used for process and device development for advanced semiconductors, power IC, display and memory design. For over 30 years, Silvaco has enabled its customers to develop next generation semiconductor products in the shortest time with reduced cost. We are a technology company outpacing the EDA industry by delivering innovative smart silicon solutions to meet the world's ever-growing demand for mobile intelligent computing. The company is headquartered in Santa Clara, California and has a global presence with offices located in North America, Europe, Japan and Asia.

About Europractice IC Service:
The EUROPRACTICE IC Service brings ASIC design and manufacturing capability within the technical and financial reach of any company that wishes to use ASICs. The EUROPRACTICE IC Service, offered by IMEC and Fraunhofer, offers low-cost ASIC prototyping and ASIC small volume production ramp-up to high volume production through Multi Project Wafer - MPW - and dedicated wafer runs.

About MOS-AK Association:
MOS-AK is an international compact modeling association primarily focused in Europe, to enable international compact modeling R&D exchange in the North/Latin Americas, EMEA and Asia/Pacific Regions. The MOS-AK Modeling Working Group plays a central role in developing a common information exchange system among foundries, CAD vendors, IC designers and model developers by contributing and promoting different elements of compact/SPICE modeling and its Verilog-A standardization and related CAD/EDA tools including FOSS for compact/SPICE model development, validation/implementation and distribution. For more information please visit mos-ak.org

[C4P] EuroSOI-ULIS April 1-3, 2019, Grenoble (F)

5th Joint International EUROSOI and ULIS Conference

at Minatec, Grenoble (F) 

on April 1-3, 2019

The Conference Committee hopes that you will actively participate by submitting high quality papers and will enjoy the conference. The Conference Technical Digest will be published by IEEE and will be available online through IEEE Xplore. The abstract submission deadline is January 15, 2019.

Invited Speakers:

• Dr. Ionut RADU, SOITEC : "SOI technology: from niche to mainstream applications"
• Dr. Anabela VELOSO, IMEC: "Nanowire for ultra-scaled, high-density logic and memory applications"
• Dr. Marc GAILLARDIN, CEA: "Radiation effects in innovative devices"
• Prof. Ru HUANG, Peking University: "Steep slope devices"

More information are provided in the attached 2nd C4P and on the Conference website

DEVSIM 1.0.0 Release #Opensource, #DEVSIM uses finite volume methods to predict behavior of semiconductor devices. In addition to drift-diffusion equations, the density-gradient method can be used to account for quantum effects near boundaries. https://t.co/q4fiJ9IMWK

DEVSIM 1.0.0 Release #Opensource, #DEVSIM uses finite volume methods to predict behavior of semiconductor devices. In addition to drift-diffusion equations, the density-gradient method can be used to account for quantum effects near boundaries. https://t.co/q4fiJ9IMWK

— Wladek Grabinski (@wladek60) December 20, 2018

from Twitter https://twitter.com/wladek60

December 20, 2018 at 10:49AM
via IFTTT

Compact Transistor Modeling with Radiation Effects

A Radiation-Hardened Instrumentation Amplifier for Sensor Readout Integrated Circuits in Nuclear Fusion Applications

Kyungsoo Jeong 1, Duckhoon Ro 1, Gwanho Lee 2  Myounggon Kang 2* and Hyung-Min Lee 1*

1 School of Electrical Engineering, Korea University, Seoul 02841, Korea; jksoo2002@korea.ac.kr (K.J.); roduckhoon@korea.ac.kr (D.R.)

2 Department of Electronics Engineering, Korea National University of Transportation, Chungju 27469, Korea; ghlee@ut.ac.kr

* Correspondence: mgkang@ut.ac.kr (M.K.); hyungmin@korea.ac.kr (H.-M.L.); Tel.: +82-43-841-5164 (M.K.); +82-2-3290-3219 (H.-M.L.)

Abstract: A nuclear fusion reactor requires a radiation-hardened sensor readout integrated circuit (IC), whose operation should be tolerant against harsh radiation effects up to MGy or higher. This paper proposes radiation-hardening circuit design techniques for an instrumentation amplifier (IA), which is one of the most sensitive circuits in the sensor readout IC. The paper studied design considerations for choosing the IA topology for radiation environments and proposes a radiation-hardened IA structure with total-ionizing-dose (TID) effect monitoring and adaptive reference control functions. The radiation-hardened performance of the proposed IA was verified through model-based circuit simulations by using compact transistor models that reflected the TID effects into complementary metal–oxide–semiconductor (CMOS) parameters. The proposed IA was designed with the 65 nm standard CMOS process and provides adjustable voltage gain between 3 and 15, bandwidth up to 400 kHz, and power consumption of 34.6 µW, while maintaining a stable performance over TID effects up to 1 MGy.

Electronics 2018, 7, 429; doi:10.3390/electronics7120429
Received: 22 November 2018; Accepted: 9 December 2018; Published: 12 December 2018