[mos-ak] Final Program: 10th MOS-AK/GSA ESSDERC/ESSCIRC Workshop in Bordeaux, Sept. 21, 2012

Together with the Organizing Committee, Extended MOS-AK/GSA TPC Committee, and the IEEE EDS French Branch, the technical program sponsor, as well as with the industrial sponsors Agilent Technologies, LFoundry, CSEM, STM, AMS we have pleasure to invite to the 10th MOS-AK/GSA Compact Modeling Workshop at the ESSDERC/ESSCIRC Conference in Bordeaux, Sept. 21, 2012.  

The final workshop program is available on-line: <http://mos-ak.org/bordeaux/> 

To register please visit official ESSDERC/ESSCIRC registration website.

- with regards - WG (for the MOS-AK/GSA Committee) 

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MOS-AK/GSA Bordeaux (F) Sept.21, 2012 

MOS-AK/GSA San Francisco, CA Q4 2012 

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Why- and how- to integrate Verilog-A compact models in SPICE simulators

A nice paper from Maria-Anna Chalkiadaki, Cédric Valla, Frédéric Poullet, and Matthias Bucher:

Why- and how- to integrate Verilog-A compact models in SPICE simulators

This article presents a fast and accurate way to integrate and validate Verilog-A compact models in SPICE-like simulators. Modifications in the models' Verilog-A source code may be required prior to their conversion into low-level C language by a code generator. The most common of these modifications is discussed. The generated C code is then directly compiled in the target simulator resulting in an equivalent SPICE model. The comparison between Verilog-A and SPICE models in the same simulation environment, for simple and complex circuits, validates the procedure. Performance tests for demanding designs are carried out for both models. Results highlight the higher simulation speed and lower memory consumption of SPICE models. Copyright © 2012 John Wiley & Sons, Ltd.

Birthday (61) of the JUNCTION transistor

From EDN:

Bell Labs and primarily William Shockley announced the invention of the junction transistor at a press conference in Murray Hill, NJ, the first week of July, 1951.
Sources vary as to when the formal announcement was actually made, July 4, 1951, or July 5, 1951.
At the time, Shockley was with Bell Labs’ solid state physics group, a unit to which he was a group head and a unit that saw much internal competition.
This new type of transistor overcame problems created by earlier point-contact transistors, developed by Bell Labs’ Joe Bardeen and Walter Brattain without Shockley but based in part on his previous work. It is said that when the patent process began for the point-contact transistor, Shockley made an effort to have his name only placed on the patent and made sure his fellow engineers knew of that effort.
Shockley has been described as having a “tremendous ego” by his co-workers. He was also known as having openly racist views.
Although Shockley is often known as “the inventor” of the transistor and despite his reported ego, he was often noted as correcting such misstatement and noting that he led the effort with others involved. Notes made during the development of the junction transistor can be viewed here.
Shockley left Bell Labs a few years after working on the junction transistor and eventually became a professor emeritus of electrical engineering at Stanford. He died on campus in 1989 at the age of 79.

For more moments in tech history, see this blog.

NANOTEC-Tutorial at ESSCIRC/ESSDERC in Bordeaux on 09/17/2012

The NANO-TEC project will held a half day tutorial at the ESSDERC/ESSCIRC Conference in Bordeaux on Monday, September 17, 2012. This Tutorial will be on the ECOSYSTEMS TECHNOLOGY and DESIGN for NANOELECTRONICS in Europe and will present the current outcome of the EU project NANOTEC [read more...]

[mos-ak] C4P: Special Issue of IEEE TED on Advanced Modeling of Power Devices and Their Applications

Call for Papers

For the Special Issue of

IEEE Transactions on Electron Devices 

On

Advanced Modeling of Power Devices and Their Applications

The special issue on "Advanced Modeling of Power Devices and Their Applications" is devoted to the research and development activities on power devices, the correlation of modeling approaches to the physics of power devices and in particular on emerging models of advanced power devices for power circuit applications. 

The importance of accurate circuit design with power devices is increasing according to the necessity of realizing efficient energy consumption. High-voltage MOSFETs are also utilized in all kinds of consumer electronics, and electric vehicles are controlled by IGBT circuit, where an urgent task is to achieve better energy control at about 1 kV bias condition. Accurate and even predictable models based on a close correlation to the important physical effects occurring in such power devices are therefore highly desired for precise circuit design. Presently many investigations are also undertaken intensively for new materials such as SiC and GaN replacing Silicon for extremely high voltage applications e.g. beyond 10 kV. A good understanding of the device operation under such extremely high bias conditions requires a lot physical analysis, and as a result leads to more effective utilization of these power devices. Together with the strong self-heating effect, the dynamically changing resistivity makes convergence in circuit simulation unstable. Techniques and physical analysis to overcome such problems are also urgently requested. 

Due to the wide range of covered bias conditions and the large variety of device structures applied, a lack of  communication occurs in the high-voltage community even though the basic tasks are the same. Therefore, the objective of this special issue is to bring together a diversity of R&D activities and advancements in the physical analysis and modeling of MOS-based power devices and other types of emerging power devices including Bipolar, Thyristor and Diode. Models for active and passive components integrated in advanced silicon as well as new material technologies, statistical modeling and mixed-mode simulation are also of special interest. 

The requirements for modeling high-voltage devices on the part of the circuit design community are now much more demanding due to urgent necessity to reduce energy consumption, where the high-voltage devices play an important role. Submissions should address advances in device characterization, physical models, as well as applications preferably but not limited to the following areas:

1. Compact modeling of power devices such as high-voltage MOSFETs, Bipolar, Thyristor and IGBT for 

circuit applications from a few volts up to beyond 10kV.

2. Modeling of passive elements such as Diode, Inductor, Resistor.

3. Investigations on new material such as SiC and GaN and their applications.

4. Circuit simulation for real applications of power devices together.

5. Investigation for computation efficiency for circuit simulation

Please submit manuscript by using the following:
http://mc.manuscriptcentral.com/ted

MAKE SURE TO MENTION THE SPECIAL ISSUE IN THE COVER LETTER

Paper Submission Deadline: July 15, 2012 

Scheduled Publication Date: February, 2013 

Guest Editors: 

Mitiko Miura-Mattausch, Hiroshima University, mmm@hiroshima-u.ac.jp  

Narain Arora, Silterra Malaysia, narain@silterra.com

Ehrenfried Seebacher,  Austriamicrosystems AG, ehrenfried.seebacher@austriamicrosystems.com

Samar K. Saha, SuVolta, Inc., samar@ieee.org

If you have any questions about submitting a manuscript, please contact:

Jo Ann Marsh (j.marsh@ieee.org)

IEEE EDS Publications Office

445 Hoes Lane Piscataway NJ 08854

Phone: +1 732 562 6855   Fax: +1 732 562 6831

http://www.ieee.org/

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