Apr 30, 2008
Process for the Selection of the Next Generation SOI MOSFET Compact Models
The CMC is soliciting SOI models for both partially-depleted (PD) and dynamic depletion (DD) applications. DD refers to SOI devices which exhibit PD behavior forsome bias regions, but are fully-depleted (FD) for others.
The deadline for candidate submission is May 5 2008. CMC officers will invite a number of selected model developers to the CMC Meeting in Boston, MA on 6/5/2008.
A new selection will be done after CMC members have had time to review the presentations given by model developers.
A SOI MOSFET model recommended by CMC will make lots of money!
Who wants to compete?
Training Course on SOI for analog,digital and RF SOCs and microsystems applications
This course is organized by the IMEC Training Center in collaboration with Prof. Denis Flandre (UCL, Louvain-la-Neuve, Belgium).
The course will address topics such as SOI MOSFET specific behaviors and performance assessments, SOI MOS analog design, micromachined SOI MEMS, on-wafer wideband characterization, and SOI FinFET integration and circuits.
The lecturers are prestigeous researchers from IMEC and UCL, all of them experts in SOI technologies.
It seems a very interesting course for SOI MOS circuit designers!
Course: "New Trends in Nanoelectronics" in Lausanne
The purpose of the course is to provide a general knowledge about emerging nanoelectronics including technology, nanowires and nanotubes, memory device architectures, nanoelectromechanical devices, and benchmarking for circuit and system applications.
The lecturers that will participate will be A. M. Ionescu, K. E. Moselund (EPFL) and H. -S. Philip Wong (stanford University).
Apr 29, 2008
Open Ph D Student position in nanoelectronic device modeling
We offer one fellowship for a Ph D student position in the Department of Electronic Engineering in the Universitat Rovira i Virgili (URV), in
The duration of the grant will be at least three years, possibly four. The monthly salary will be 1000 Euro/month.
The candidate should have a Bachelor or Master degree in Electrical Engineering, Electronic Engineering, Telecommunication Engineering or Physics. A good background in Semiconductor Physics, Semiconductor Devices, or Integrated Circuit Design will be highly appreciated.
The work to be done by the candidate will be focused on the development of new techniques of characterization and modeling of novel nanoscale semiconductor devices. It will be related to two European projects in which the hosting group participates.
To get more information about our areas of research in the DEEEA, you can visit the website:
http://sauron.etse.urv.es/DEEEA/angles/recerca/nephos/scholarships.htm
And
http://sauron.etse.urv.es/DEEEA/angles/recerca/nephos
Required documents for applicants
Applicants are required to send to the address specified below the following documents (in English or Spanish):
1) a full Curriculum Vitae (as complete as possible)
2) Copy of their diploma
3) copy of their passport
4) Academic certificate including their marks (it is important that the number of hours of each subject). It is also very important that the document specifies what is the minimum mark for passing a given subject and what is the maximum mark that can be awarded.
Candidates can send their documents by e-mail, but in fact we will need original and copy documents (or authenticated copy) of them; therefore we suggest to send the documents by postal mail.
Applications should be sent to:
Prof. Benjamin Iñiguez
Department of Electronic, Electrical and Automatic Control Engineering
Universitat Rovira i Virgili (URV)
Avinguda Països Catalans, 26
43007
Email: benjamin.iniguez@urv.cat
Tel: +34977558521 Fax:+34977559610
Deadline:
You can contact Prof. Benjamin Iñiguez (Benjamin.Iniguez@urv.cat) for more information
Apr 21, 2008
MIGAS'08 Summer School
MIGAS 2008 will take place in Autrans (French Alps) from June 28 to July 4 2008.
MIGAS is addressed to PhD students, engineers and researchers coming both from the university and from industry of the semiconductors.
The attendees will be able to improve their knowledge on nanoelectronic devices by means a set of lectures conducted by top international scientists.
The scienfific programme will consists of the following lectures:
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Registration includes accomodation in the resort as well as all meals.