[paper] RTN and BTI statistical compact modeling

G.Pedreira^a, J.Martin-Martinez^a, P.Saraza-Canflanca^b, R.Castro Lopez^b, R.Rodriguez^a, E.Roca^b, F.V.Fernandez^b, M.Nafria^a 

Unified RTN and BTI statistical compact modeling from a defect-centric perspective

Solid-State Electronics

Available online 25 June 2021, 108112

In Press, Journal Pre-proof

DOI: 10.1016/j.sse.2021.108112

a Universitat Autònoma de Barcelona (UAB), Electronic Engineering Department, REDEC group. Barcelona, Spain
b Instituto de Microelectrónica de Sevilla, IMSE-CNM, CSIC and Universidad de Sevilla, Spain

Abstract: In nowadays, deeply scaled CMOS technologies, time-dependent variability effects have become important concerns for analog and digital circuit design. Transistor parameter shifts caused by Bias Temperature Instability and Random Telegraph Noise phenomena can lead to deviations of the circuit performance or even to its fatal failure. In this scenario extensive and accurate device characterization under several test conditions has become an unavoidable step towards trustworthy implementing the stochastic reliability models. In this paper, the statistical distributions of threshold voltage shifts in nanometric CMOS transistors will be studied at near threshold, nominal and accelerated aging conditions. Statistical modelling of RTN and BTI combined effects covering the full voltage range is presented. 

The results of this work suppose a complete modelling approach of BTI and RTN that can be applied in a wide range of voltages for reliability predictions.

[paper] Performance limits of hBN as an insulator for scaled CMOS

Theresia Knobloch¹, Yury Yu. Illarionov^1,2, Fabian Ducry³, Christian Schleich⁴, Stefan Wachter⁵, Kenji Watanabe⁶, Takashi Taniguchi⁷, Thomas Mueller⁵, Michael Waltl⁴, Mario Lanza⁸, Mikhail I. Vexler², Mathieu Luisier³ and Tibor Grasser¹

The performance limits of hexagonal boron nitride as an insulator for scaled CMOS devices based on two-dimensional materials

Nature Electronics; Vol 4; Feb.2021; pp.98–108;

DOI: 10.1038/s41928-020-00529-x

1. Institute for Microelectronics, TU Wien, Vienna, Austria.
2. Ioffe Institute, St Petersburg, Russia.
3. Integrated Systems Laboratory, ETH Zürich, Zurich, Switzerland.
4. Christian Doppler Laboratory for Single-Defect Spectroscopy in Semiconductor Devices at the Institute for Microelectronics, TU Wien, Vienna, Austria.
5. Institute for Photonics, TU Wien, Vienna, Austria.
6. Research Center for Functional Materials, National Institute for Matierals Science, Tsukuba, Japan.
7. International Center for Materials Nanoarchitectonics, National Institute for Materials Science, Tsukuba, Japan.
8. Physical Sciences and Engineering Division, King Abdullah University of Science and Technology (KAUST), Thuwal, Saudi Arabia.

Abstract: Complementary metal–oxide–semiconductor (CMOS) logic circuits at their ultimate scaling limits place extreme demands on the properties of all materials involved. The requirements for semiconductors are well explored and could possibly be satisfied by a number of layered two-dimensional (2D) materials, such as transition metal dichalcogenides or black phosphorus. The requirements for gate insulators are arguably even more challenging. At present, hexagonal boron nitride (hBN) is the most common 2D insulator and is widely considered to be the most promising gate insulator in 2D material-based transistors. Here we assess the material parameters and performance limits of hBN. We compare experimental and theoretical tunnel currents through ultrathin layers (equivalent oxide thickness of less than 1 nm) of hBN and other 2D gate insulators, including the ideal case of defect-free hBN. Though its properties make hBN a candidate for many applications in 2D nanoelectronics, excessive leakage currents lead us to conclude that hBN is unlikely to be suitable for use as a gate insulator in ultrascaled CMOS devices.

Fig: Comparison of gate insulators for ultrascaled CMOS devices based on 2D materials. a.) Currents at constant EOT for 3D oxides and layered insulators. The leakage currents as calculated with the Tsu–Esaki model are given for 3D amorphous oxide and 2D layered insulators at a constant thickness of EOT=0.76nm. If no tunnel masses were known, the free-electron mass was used. The filled circles indicate the results of ab initio calculations and the dotted line connecting the circles is a guide to the eye. b.) Currents at constant EOT for native oxides and fluorides. The leakage currents are given for native oxides and ionic fluorides at a constant thickness of EOT=0.76nm.

Acknowledgements: T.K., Y.Y.I. and T.G. acknowledge the financial support through FWF grant numbers I2606-N30, I4123-N30 and P29119-N35. Y.Y.I. and M.I.V. acknowledge financial support by the Ministry of Science and Higher Education of the Russian Federation under project number 075-15-2020-790. F.D. and M. Luisier thank CSCS for giving them access to the Piz Daint supercomputer under project number s876. C.S. and M.W. gratefully acknowledge financial support by the Austrian Federal Ministry for Digital and Economic Affairs and the National Foundation for Research, Technology and Development and the Christian Doppler Research Association. The computational results presented have been achieved in part using the Vienna Scientific Cluster (VSC). S.W. and T.M. acknowledge financial support through the Graphene Flagship number 785219 and number 881603. K.W. and T.T. acknowledge support from the Elemental Strategy Initiative conducted by the MEXT, Japan, number JPMXP0112101001, JSPS KAKENHI grant number JP20H00354 and the CREST(JPMJCR15F3), JST. M. Lanza acknowledges support from the Ministry of Science and Technology of China (grant numbers 2018YFE0100800, 2019YFE0124200) and the National Natural Science Foundation of China (grant number 61874075).

[papers] compact modeling

Rabnawaz Sarmad Uqaili, Faraz Bashir Soomro, Junaid Ahmed Uqaili, Ahsin Murtaza Bughio 

and Khalid Ali Khan

Study on Compact Equivalent Circuit Model for RF CMOS Transistor 

International Journal of Scientific & Technology Research 

Vol.10, Issue 02, February 2021 ISSN 2277-8616

Abstract: In this study, a physical-based radio-frequency (RF) compact equivalent circuit model (CECM) for complementary metal-oxidesemiconductor (CMOS) transistor and its parameter extraction is presented. The whole structure of CECM that includes a small-signal equivalent circuit model of the transistor, a MOSFET small-signal substrate model, an input and output ground-signal-ground (GSG) pad model, a pad coupling model and a metal interconnection model are briefly studied and discussed. Based on this study, a complete test structure model for RF CMOS is designed and the initial values of parameters are extracted by using the analytical method. The multi-bias scattering parameters (S-Parameters) of model correspondence to the experimentation are validated up to 66 GHz and 220 GHz respectively. A good agreement has been achieved between the simulation and experimental under multi-bias conditions.

Fig: Complete CECM for RF CMOS transistor with an entire test structure.

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El Mashade, Mohamed B., and Ahmed Abdel Monem

Transient model for modern microelectronic devices applicable to EKV PMOS model 

Radioelectronics and Communications Systems 

Vol.64, no. 2 (2021): 64-79

Abstract: Massive advances in microelectronic manufacturing technology with an exponential growth of their complexity and speed are needed to ensure a continuous development of novel techniques, structures, devices, circuits and systems. This paper is intended for the introduction of a new PMOS transient model for modern microelectronic devices that provides a fast transient response. Such suggested model expresses the transient terminal currents as polynomial functions of the normalized channel charge densities at the channel bounds with the assistance of a modified version of the cubic spline collocation methodology in symmetrical telescopic fashion. Additionally, the optimum number of segments, which is suitable for the new version of the cubic spline collocation algorithm, is investigated. Moreover, the normalized channel charge density at collocation points is modeled in terms of its values at the channel bounds through the quasi-static approach. Furthermore, by means of introducing an inverse function for the normalized overdrive channel voltage, the transient terminal currents are formulated as a function of the terminal voltages. In comparison with usual cubic spline collocation structure, the novel model has much better accuracy in its application to EKV structure. The developed model has been applied to the standard 0.15 mm technology and validated by MATLAB R2014a. The obtained results demonstrate that it gives a very high degree of relative accuracy, on average of 99%, for the total time and exhibits absolute error of less than 5% of the maximum value, in its worst case.

---

Rakeshkumar Mahto and Reshma John 

Modeling of Photovoltaic Module 

(April 1st 2021)

DOI: 10.5772/intechopen.97082. 

Abstract: A Photovoltaic (PV) cell is a device that converts sunlight or incident light into direct current (DC) based electricity. Among other forms of renewable energy, PV-based power sources are considered a cleaner form of energy generation. Due to lower prices and increased efficiency, they have become much more popular than any other renewable energy source. In a PV module, PV cells are connected in a series and parallel configuration, depending on the voltage and current rating, respectively. Hence, PV modules tend to have a fixed topology. However, in the case of partial shading, mismatching or failure of a single PV cell can lead to many anomalies in a PV module’s functioning. If proper attention is not given, it can lead to the forward biasing of healthy PV cells in the module, causing them to consume the electricity instead of producing it, hence reducing the PV module’s overall efficiency. Hence, to further the PV module research, it is essential to have an approximate way to model them. Doing so allows for understanding the design’s pros and cons before deploying the PV module-based power system in the field. In the last decade, many mathematical models for PV cell simulation and modeling techniques have been proposed. The most popular among all the techniques are diode based PV modeling. In this book chapter, the author will present a double diode based PV cell modeling. Later, the PV module modeling will be presented using these techniques that incorporate mismatch, partial shading, and open/short fault. The partial shading and mismatch are reduced by incorporating a bypass diode along with a group of four PV cells. The mathematical model for showing the effectiveness of bypass diode with PV cells in reducing partial shading effect will also be presented. Additionally, in recent times besides fixed topology of series–parallel, Total Cross-Tied (TCT), Bridge Link (BL), and Honey-Comb (H-C) have shown a better capability in dealing with partial shading and mismatch. The book chapter will also cover PV module modeling using TCT, BL, and H-C in detail.

Available: https://www.intechopen.com/online-first/modeling-of-photovoltaic-module

[C4P] DevIC 2021

DevIC 2021: Call for Papers

IEEE KGEC Student Branch Chapter in association with Department of ECE, KGEC, technically co-sponsored by IEEE EDS Kolkata Chapter  organizes International conference 4th Int. Conference DevIC 2021 “Devices for Integrated Circuit (DevIC)”.  There will be keynote lectures/talks, tutorials, and oral presentations  by eminent researchers. The conference organizers invite original papers in the research areas of various aspects of semiconductor technology and circuits that creates an opportunity to symbiosis on topic ranging from process technology to system-on-chip. Articles announcing significant and original results are highly requested. Papers are solicited across the general field of electronic devices. Topics of interest include, but are not limited to;

• CMOS Processes, Devices and Integration;
• VLSI Technology and Circuits;
• Innovative Systems;
• Emerging Non-CMOS Devices & Technologies;
• Device Modelling & Simulation; 
• Device Characterization, Reliability & Yield; 
• Devices with New material systems;
• Devices for Low power applications;
• Low dimensional devices;
• Low dimensional Semiconductors; 
• Design and Simulation of Circuits with nanoscale devices;
• MEMS, Sensors & Display Technologies;
• Advanced & Emerging Memories; 
• High frequency wireless communication;

DevIC 2021 Conference Committee

[paper] Perspective of Ultra-Scaled CMOS

Ab initio perspective of ultra-scaled CMOS

from 2D-material fundamentals to dynamically doped transistors

Aryan Afzalian 

Open Access; npj 2D Mater Appl 5, 5 (2021) 

DOI: 10.1038/s41699-020-00181-1 

Abstract: Using accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10-nm scaling for high-performance complementary metal oxide semiconductor (CMOS) applications. We show that a combination of good electrostatic control together with high mobility is paramount to meet the stringent roadmap targets. Such requirements typically play against each other at sub-10-nm gate length for MOS transistors made of conventional semiconductor materials like Si, Ge, or III–V and dimensional scaling is expected to end ~12 nm gate-length (pitch of 40 nm). We demonstrate that using alternative 2D channel materials, such as the less-explored HfS2 or ZrS2, high-drive current down to ~6 nm is, however, achievable. We also propose a dynamically doped field-effect transistor concept, that scales better than its MOSFET counterpart. Used in combination with a high-mobility material such as HfS2, it allows for keeping the stringent high-performance CMOS on current and competitive energy-delay performance, when scaling down to virtually 0 nm gate length using a single-gate architecture and an ultra-compact design (pitch of 22 nm). The dynamically doped field-effect transistor further addresses the grand-challenge of doping in ultra-scaled devices and 2D materials in particular.

Fig: Switching energy vs delay (EDP) of high-performance MOSFET and D2-FET inverters. EDP of 1ML-HfS2 high-performance inverter cells, at various VDD (0.4 V to 0.7 V), made of L = 5 nm and L = 3 nm stacked DG MOSFETs (5 ribbons/device) and L = 0 nm and L = nm stacked SG-D2-FETs (nine ribbons/device). The EDP performance of Si HP inverter cells made of L = 12 nm stacked Si-GAA MOSFETs (tS = 5 nm, 8 wires/device) and L = 5 nm stacked Si SG-D2-FETs (tS = 3 nm, 7 ribbons/device) are also shown for comparison. The inverters are loaded with a 50 contacted-gate-pitch-long metal line (https://irds.ieee.org/editions/2018). The extrinsic capacitances of the cell layout are also included in the load capacitance. IOFF = 10 nA/μm. ΔL = 4 nm for the D2-FETs.

Acknowledgements: Part of the computing resources and services used in this work were provided by the VSC (Flemish Supercomputer Center), funded by the Research Foundation–Flanders (FWO) and the Flemish Government. The author acknowledges the support of Dr. G. Gaddemane for the DFTP e-ph coupling calculations.

Open Access: This article is licensed under a Creative Commons Attribution 4.0 International License

[papers] Compact Modeling

Q. C. Nguyen, P. Tounsi, J. Fradin and J. Reynes, "Development of SiC MOSFET Electrical Model and Experimental Validation: Improvement and Reduction of Parameter Number," 2019 MIXDES - 26th International Conference "Mixed Design of Integrated Circuits and Systems", Rzeszów, Poland, 2019, pp. 298-301.

doi: 10.23919/MIXDES.2019.8787050

Abstract: In this work, a new approach for electrical modeling of Silicon Carbide (SiC) MOSFET is presented. The developed model is inspired from the Curtice model which is using a mathematic function reflecting MOSFET output characteristics. The first simulation results showed good agreement with measurements. Improvement is needed in order to increase model accuracy and to take into account the influence of the junction temperature on device characteristics.

D. Kasprowicz, "Semiconductor Device Parameter Extraction Based on I–V Measurements and Simulation," 2019 MIXDES - 26th International Conference "Mixed Design of Integrated Circuits and Systems", Rzeszów, Poland, 2019, pp. 321-326.

doi: 10.23919/MIXDES.2019.8787195

Abstract: The paper presents a method for extracting the physical parameters of a semiconductor device based on the measurements of its electrical response (e.g. transfer characteristics) combined with simulation. Such extraction is usually performed by an optimization algorithm seeking device-parameter values that minimize the difference between the measured response and its simulated equivalent. The proposed approach needs only an average of 13 objective-function evaluations, i.e. device simulations, to extract three parameters of a single device. If the parameters of a group of devices of the same type are to be extracted, the average number of simulations drops to four per device. This number is much smaller than in conventional optimization procedures. Thus, the proposed procedure can be used even in the absence of an accurate compact model, when time-consuming TCAD simulation must be used to determine the device’s response.

D. Tomaszewski, J. Malesińska, G. Głuszko and K. Kucharski, "Current vs Substrate Bias Characteristics of MOSFETs as a Tool for Parameter Extraction," 2019 MIXDES - 26th International Conference "Mixed Design of Integrated Circuits and Systems", Rzeszów, Poland, 2019, pp. 87-91.

doi: 10.23919/MIXDES.2019.8787068

Abstract: An application of the drain current vs substrate bias characteristics of MOSFETs for the device parameter extraction is presented. Modeling of the substrate bias effect on the MOSFET drain current is briefly discussed. A method of the MOSFET characterization is formulated. It requires a measurement of two I(V) characteristics, including the ID(VBS) smooth curve measured in a "sweep" mode. The method allows to extract the threshold voltage parameters and to estimate the in-depth doping profile in the substrate. The proposed approach is demonstrated using I(V) data of the MOSFETs manufactured in ITE in a bulk CMOS process.

IEEE EDS MQ at Hotel Plaza, Begumpet (IN)

Joint Chapter of Electron Devices and Circuits and Systems Societies (ED/CAS)

presents

IEEE Electron Devices Mini Colloquia

Date:  Sunday, 24 February 2019 Time:  3.00 P.M to 6.00 P.M

Venue: Hotel Plaza, Begumpet. Free Registration Link 

For any further details please contact the MQ Coordinators:

• Dr. Mohammed Arifuddin Sohel, Chair, IEEE CAS/EDS joint Chapter
• Dr. A.G. Krishna Kanth, Vice Chair, IEEE CAS/EDS joint Chapter

Registrations: 3:00PM to 3.15 PM

DL Talk 1: 3.15 PM to 4.00PM, Speaker: Prof. Charvaka Duvvury, iT2 Technologies (USA)
Topic: ESD Issues and Challenges for Advanced Semiconductor Technologies

Electro-static Discharge (ESD) has been a constant reliability concern for IC technologies for several decades and it is heading to be a roadblock to newer applications for electronic devices. The seminar will begin with a summary of the understanding about ESD and how this is applied to develop protection at the IC level for Digital, Analog, and RF circuits. This will be followed by a review of the problems posed by advanced technologies beyond the 32 nm node and the corresponding challenge of hitting the available ESD design window while meeting the IO high-speed performance requirements. The talk will conclude with a survey of the upcoming challenges from emerging technologies such as GaN and CNT, as well as IoT applications. 

Speaker Bio: Charvaka Duvvury was a Texas Instruments fellow while he worked in the Silicon Technology Development group at TI.  He received his PhD in engineering science from the University of Toledo and afterwards worked as a post-doctoral fellow in Physics at the University of Alberta. His experience at Texas Instruments spanned for 35 years in semiconductor device physics with pioneering development work in ESD design. He has also mentored PhD students at several leading US universities on their investigations in ESD research and received Outstanding Industry Mentor Award twice from the SRC. Charvaka has published over 150 papers in technical journals and conferences and holds more than US 75 patents. He co-authored and contributed to 5 books on the subject. He is a recipient of the IEEE Electron Devices Society’s Education Award and Outstanding Contributions Award from the EOS/ESD Symposium. Charvaka has been serving on Board of Directors of the ESD Association (ESDA) since 1997 promoting ESD education and research at academic institutes. He is co-founder and co-chair of the Industry Council on ESD since 2006. During 2015 he became a co-founder of the iT2 Technologies that utilizes software engine and machine learning for rapid ESD data analysis. Charvaka is also Fellow of the IEEE.

Hi Tea and Networking: 4.00 PM to 4.15 PM

DL Talk 2: 4.15 PM to 5.00PM Speaker: Dr. Wladek Grabinski, MOS-AK (Switzerland)

Topic: FOSS TCAD/EDA Process/Device Simulations for Compact/SPICE Modeling

Compact/SPICE models of circuit elements (passive, active, MEMS, RF) are essential to enable advanced IC design using nanoscaled semiconductor technologies. To explore all related interactions, we are discussing selected FOSS CAD tools along complete technology/design tool chain from nanascaled technology processes. New technology and device development will be illustrated by application examples of the FOSS TCAD tools: Cogenda TCAD and DEVSIM. Compact modeling will be highlighted by review topics related to its parameter extraction and standardization of the experimental and measurement data exchange formats. Finally, we will present FOSS CAD simulation and design tools: ngspice, Qucs, GnuCap, Xyce.

Speaker Bio: Wladek Grabinski received the Ph.D. degree from the Institute of Electron Technology, Warsaw, Poland, in 1991. From 1991 to 1998 he was a Research Assistant at the Integrated Systems Lab, ETHZ, Switzerland, supporting the CMOS and BiCMOS technology developments by electrical characterization of the processes and devices. From 1999 to 2000, he was with LEG, EPFL, and was engaged in the compact MOSFET model developments supporting numerical device simulation and parameter extraction. Later, he was a technical staff engineer at Motorola, and subsequently at Freescale Semiconductor, Geneva Modeling Center, Switzerland. He is now a consultant responsible for modeling, characterization and parameter extraction of MOST devices for the IC design. Wladek is the chair of the ESSDERC Track4: "Device and circuit compact modeling" as well as has served as a member of organization committee of ESSDERC/ESSDERC, TPC of SBMicro, SISPAD, MIXDES Conferences; reviewer of the IEEE TED, IEEE MWCL, IJNM, MEE, MEJ/ Wladek is involved in activities of the MOS-AK Association and serves as a coordinating manager since 1999.

DL Talk 3: 5.00PM to 5.45 PM Speaker: Prof. Roberto Murphy, INAOE (Mexico)
Topic: Fundamental Aspects of CMOS RF Modeling and Characterization

As CMOS technology evolves, higher frequencies can be attained while more complex functions and operations become possible in Integrated Circuits. At the design stage, there are several fundamental aspects which have to be taken into account in order to have successful fabrication results, the closest to simulation predictions as possible. Furthermore, this evolution leads to more time-consuming characterization routines, which require both personnel and time to be performed. Some of the aspects dealt with in this talk refer to characterization techniques, substrate network effects, and geometry effects.

Speaker Profile:  Roberto S. Murphy-Arteaga (M´92, SM´02) received his B.Sc. degree in Physics from St. John’s University, Minnesota, and got his M.Sc. and Ph.D. degrees from the National Institute for Research on Astrophysics, Optics and Electronics (INAOE), in Tonantzintla, Puebla, México.  He has been a researcher at INAOE since 1988. Since then, he has presented over 110 talks at scientific conferences, directed nine Ph.D. theses, 16 M.Sc. and 2 B.Sc. theses, published more than 140 articles in scientific journals, conference proceedings and newspapers, and is the author of a text book on Electromagnetic Theory.  He is currently a senior researcher with the Microelectronics Laboratory.  Dr. Murphy’s research interests are the physics, modeling and characterization of the MOS Transistor and passive components for high frequency applications, especially for CMOS wireless circuits, and antenna design.  For the last 30 years, he has been active in the organization of conferences, mostly in Latin America, such as the IEEE International Caribbean Conference on Devices, Circuits and Systems; the Latin American Symposium on Circuits and Systems; VLSI-SoC, and others related to microelectronics and IC design. He is a Senior Member of IEEE, a Distinguished Lecturer of the Electron Devices Society, the President of ISTEC, a member of the Mexican Academy of Sciences, and a member of the Mexican National System of Researchers (SNI).

Cryogenic characterization of CMOS technologies

A. Beckers, F. Jazaeri, A. Ruffino, C. Bruschini, A. Baschirotto and C. Enz

Cryogenic characterization of 28 nm bulk CMOS technology for quantum computing

47th ESSDERC, Leuven, Belgium, 2017, pp. 62-65.

Abstract: This paper presents the first experimental investigation and physical discussion of the cryogenic behavior of a commercial 28 nm bulk CMOS technology. Here we extract the fundamental physical parameters of this technology at 300,77 and 4.2 K based on DC measurement results. The extracted values are then used to demonstrate the impact of cryogenic temperatures on the essential analog design parameters. We find that the simplified charge-based EKV model can accurately predict the cryogenic behavior. This represents a main step towards the design of analog/RF circuits integrated in an advanced bulk CMOS process and operating at cryogenic temperature for quantum computing control systems [read more...] doi: 10.1109/ESSDERC.2017.8066592

R. M. Incandela, L. Song, H. A. R. Homulle, F. Sebastiano, E. Charbon and A. Vladimirescu

Nanometer CMOS characterization and compact modeling at deep-cryogenic temperatures

47th ESSDERC, Leuven, Belgium, 2017, pp. 58-61.

Abstract: The characterization of nanometer CMOS transistors of different aspect ratios at deep-cryogenic temperatures (4 K and 100 mK) is presented for two standard CMOS technologies (40 nm and 160 nm). A detailed understanding of the device physics at those temperatures was developed and captured in an augmented MOS11/PSP model. The accuracy of the proposed model is demonstrated by matching simulations and measurements for DC and time-domain at 4 K and, for the first time, at 100 mK [read more...] doi: 10.1109/ESSDERC.2017.8066591

[paper] Improvements to a compact MOSFET model for design by hand

Improvements to a compact MOSFET model for design by hand

A. de Jesus Costa, F. Martins Cardoso, E. Pinto Santana and A. I. Araújo Cunha

15th IEEE NEWCAS

Strasbourg, France, 2017, pp. 225-228

doi: 10.1109/NEWCAS.2017.8010146

Abstract: In this work, an improved version of the basic structure of a compact MOSFET model and the respective parameters extraction methodology are proposed. The aim of this approach is to increase accuracy in hand calculations for analog circuit design without significantly increasing its complexity. The influences of both inversion level and channel length are considered in the modeling of a few features such as mobility, threshold voltage and onset of saturation. Simple design examples of current sinks and sources are accomplished to compare the basic and the improved models [read more...]

[paper] Compact On-Wafer Test Structures for Device RF Characterization

B. Kazemi Esfeh, K. Ben Ali and J. P. Raskin IEEE Fellow

Compact On-Wafer Test Structures for Device RF Characterization

in IEEE TED, vol. 64, no. 8, pp. 3101-3107, Aug. 2017
doi: 10.1109/TED.2017.2717196

Abstract: The main objective of this paper is to validate the radio frequency (RF) characterization procedure based on compact test structures compatible with 50um pitch RF probes. It is shown that by using these new test structures, the layout geometry and hence the on-chip space consumption for complete sets of passive and active devices, e.g., coplanar waveguide transmission lines and RF MOSFETs, is divided by a factor of two. The validity domain of these new compact test structures is demonstrated by comparing their measurement results with classical test structures compatible with 100–150um pitch RF probes. 50um -pitch de-embedding structures have been implemented on 0.18um RF silicon-on-insulator (SOI) technology. Cutoff frequencies and parasitic elements of the RF SOI transistors are extracted and the RF performance of trap-rich SOI substrates is analyzed under small- and large-signal conditions [read more...]

[chapter] Near-Threshold Digital Circuits for Nearly-Minimum Energy Processing

Near-Threshold Digital Circuits for Nearly-Minimum Energy Processing

Massimo Alioto

Department of Electrical & Computer Engineering, National University of Singapore

in Enabling the Internet of Things; pp 95-148 

DOI: 10.1007/978-3-319-51482-6_4

This chapter addresses the challenges and the opportunities to perform computation with nearly-minimum energy consumption through the adoption of logic circuits operating at near-threshold voltages. Simple models are provided to gain an insight into the fundamental design tradeoffs. A wide set of design techniques is presented to preserve the nearly-minimum energy feature in spite of the fundamental challenges in terms of performance, leakage and variations. Emphasis is given on debunking the incorrect assumptions that stem from traditional low-power common wisdom at above-threshold voltages. The traditional EKV model is very useful for quick estimates, but it oversimplifies the IV characteristics that is observed in actual nanometer CMOS technologies [read more...]

[Course] Advanced CMOS/FinFET Fabrication

February 6, 2017; Portland, OR, USA

Semiconductor and integrated circuit developments continue to proceed at an incredible pace. For example, today’s microprocessor chips have one thousand times the processing power of those a decade ago. These challenges have been accomplished because of the integrated circuit industry’s ability to track something known as Moore’s Law. Moore’s Law states that an integrated circuit’s processing power will double every two years. This has been accomplished by making devices smaller and smaller. The question looming in everyone’s mind is “How far into the future can this continue?” Advanced CMOS/FinFET Fabrication is a 1-day course that offers detailed instruction on the processing used in a modern integrated circuit, and the processing technologies required to make them. We place special emphasis on current issues related to manufacturing the next generation devices. This course is a must for every manager, engineer and technician working in the semiconductor industry, using semiconductor components or supplying tools to the industry.

Register for this Course

[paper] Radiation-Induced Fault Simulation of SOI/SOS CMOS LSI’s Using Universal Rad-SPICE MOSFET Model

Radiation-Induced Fault Simulation of SOI/SOS CMOS LSI’s 

Using Universal Rad-SPICE MOSFET Model

Konstantin O. Petrosyants, Lev M. Sambursky, Igor A. Kharitonov, Boris G. Lvov

J Electron Test (2017)

doi:10.1007/s10836-016-5635-8

Abstract: The methodology of modeling and simulation of environmentally induced faults in radiation hardened SOI/SOS CMOS IC’s is presented. It is realized at three levels: CMOS devices – typical analog or digital circuit fragments – complete IC’s. For this purpose, a universal compact SOI/SOS MOSFET model for SPICE simulation software with account for TID, dose rate and single event effects is developed. The model parameters extraction procedure is described in great depth taking into consideration radiation effects and peculiarities of novel radiation-hardened (RH) SOI/SOS MOS structures. Examples of radiation-induced fault simulation in analog and digital SOI/SOS CMOS LSI’s are presented for different types of radiation influence. The simulation results show the difference with experimental data not larger than 10–20% for all types of radiation.

The electrical schematics of SOS CMOS opamp and 4-bit counter are presented; two variants of either macromodel were used for body-tied partially-depleted transistors: a) core EKV-SOI/ BSIMSOI model; b) EKV-RAD/ BSIMSOI-RAD macromodel. [read more...]

AMS Multi Project Wafer Service

AMS MPW Service:

ams' Multi Project Wafer (MPW) service, also known as shuttle runs, is a fast and cost-efficient prototyping service, which combines several designs from different customers onto a single wafer.

ams’ best in class MPW service offers significant cost advantages for foundry customers as the costs for wafers and masks are shared among a number of different shuttle participants. It includes the whole range of 0.18µm and 0.35µm specialty processes:

• CMOS Mixed Signal
• CMOS Mixed Signal with embedded EEPROM
• CMOS High Voltage (up to 120 Volts)
• CMOS High Voltage with embedded EEPROM
• CMOS Opto
• SiGe-BiCMOS

The complete MPW schedule including detailed start dates per process is available on the web at http://asic.ams.com/MPW

Deliverables: Participating the ams MPW service includes the delivery of 40 prototypes for design verification. Packaged engineering samples are offered within 2 days (ceramic) and 3 weeks (plastics) cycle time, respectively. The total turnaround time from MPW deadline to delivery is app. 8 weeks (CMOS). Overall, ams offers almost 150 MPW start dates in 2016 and 2017, enabled by long lasting co-operations with partner organizations such as CMP, Europractice, Fraunhofer IIS and Mosis. Customers located in APAC region may also participate via our local MPW program partners Toppan Technical Design Center Co., Ltd (TDC) and MEDs Technologies [read more...]

Sub-Minimum-Area MPW Sharing

Is Your Multi-Project Wafer Project Smaller Than the Fab Minimum Area?

Share the minimum area with other MPW customers to save mask costs

With the cost of mask sets going up with every node, even a multi-project wafer (MPW) can break your NRE budget, particularly if you plan to run multiple test spins. At 28nm, a 6mm2 area tile can cost over $100,000.

One solution is to share the minimum tile area with someone else who is using the same technology and metal stack that you are targeting. We periodically get these kinds of requests from customers. Please contact directly star@esilicon.com if you would like eSilicon to list your own MPW shuttle sharing opportunity, or if you would like eSilicon to contact you when future MPW tile sharing opportunities are available.

Following are upcoming opportunities to share a multi-project wafer (MPW) tapeout with another eSilicon customer. If you are interested, just email eSilicon.

Multi-Project Wafer Minimum Tile Sharing Opportunities for TSMC Technologies

Tapeout Month	Technology	Metal Stack	I/O	Price/mm2	Minimum Area	Final GDSII Due	Tapeout Date	Estimated Ship Date
October	65nm MS RF GP	1P9M_6x1z1u	2.5V	$4,700	1mm2	October 10	October 12	November 23
	65nm MS RF LP	1P9M_6x1z1u	2.5V	$4,700	1mm2	October 10	October 12	November 23
	180nm MS RF G	1P6M_4x1u	3.3V	$1,000	5mm2	October 24	October 26	December 7
November	40nm MS RF LP	1P10M	1.8V	$7,500	1mm2	October 31	November 2	January 17

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Alliance: FOSS VLSI/CAD System

Alliance is a complete set of free cad tools and portable libraries for VLSI design. It includes a VHDL compiler and simulator, logic synthesis tools, and automatic place and route tools. A complete set of portable CMOS libraries is provided. Alliance is the result of a twelve year effort spent at SoC department of LIP6 laboratory of the Pierre & Marie Curie University (Paris VI, France). Alliance has been used for research projects such as the 875 000 transistors StaCS superscalar microprocessor and 400 000 transistors IEEE Gigabit HSL Router.

Alliance VLSI CAD System is free software. Binaries, source code and cells libraries are freely available under the GNU General Public License (GPL). You are welcome to use the software package even for commercial designs without any fee. You are kindly requested to mention: "Designed with Alliance © LIP6, Université Pierre et Marie Curie".

ICs Designed with Alliance

• Smartlabs/Smarthome designed a complete circuit in the XFAB XH035 technology (2014).
• Tokai University (Shimizu Lab) designed the SNX, a 16 bits processor in the ROHM 0.18µm (2010).

Useful Links

• Improved Standard Cell libraries and documentation on how to design them, by Graham Petley: VLSI Technology
• A book presenting Alliance in depth: Introduction to VLSI CMOS Circuits design by Carlos SilvaCardenas, Takeo Yoshida & Alberto Palacios Pawlovsky.
• For Spanish readers, a set of tutorials made by Miguel Eduardo Flores Gomez from Don Bosco University: Tutorial de Alliance

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Analog CMOS from 5 micrometer to 5 nanometer

 Sansen, W., "1.3 Analog CMOS from 5 micrometer to 5 nanometer," ISSCC 2015 IEEE International , vol., no., pp.1,6, 22-26 Feb. 2015 doi: 10.1109/ISSCC.2015.7062848 

Abstract: In our future, as usual, analog designers will continue to expand their expertise and knowledge in response to changing needs. While devices will change their nature and operate at higher and higher frequencies, their I-V characteristics will remain similar. In the near term, increased speed of MOS circuits, will be reached by operating deeper in weak inversion. Offset and 1/f noise will continue to play a critical role. Thus, in general, it seems that analog expertise is insensitive to technology change.

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Semiconductor Devices Characterization Seminar

Technical Seminars addressing the challenges of CMOS, Power and RF

semiconductor device measurement and modeling 

Agilent and it´s 25 collaborative partners invite you to attend this complimentary technical seminar on characterization and modeling of semiconductor devices. Two tracks in parallel will address the needs for:

• Small scale silicon industry
• Power silicon industry and RF Power

Common topics to both Tracks:

• Live demonstration of GaN device characterization flow: DC I-V characteristic extraction, RF Power measurement, Spice models creation for further usage in design stage.

CMOS Track:

• Accurate and repeatable on-the-wafer device extraction – Cascade Microtech
• DC characterization for emerging nano-technologies
• Flicker Noise and Random Telegraph Noise
• Spice model libraries optimization for dedicated application

Power & RF Power Track:

• High Power Devices measurement
• III-V devices spice model (DynaFET)
• Nonlinear Component characterization
• Non-50ohm Load Pull solution – Maury

Where/when:
To obtain the detail agenda of the nearest session, please select one of the locations below.

Country	City	Date	More Information
FR	Grenoble	18 September 2014	Register here
FI	Helsinki	23 September 2014	Register here
DE	Munich	30 September 2014	Register here
DE	Dresden	2 October 2014	Register here
CH	Lausanne	14 October 2014	Register here
BE	Leuven	16 October 2014	Register here
NL	Eindhoven	17 October 2014	Register here
SW	Goteborg	28 October 2014	Register here
UK	Cambridge	30 October 2014	Register here
FR	Les Ulis	6 November 2014	Register here

 

 

VI Regional Seminar MNE & MS 2014

VI Regional Seminar on Computer Modeling and Designing in Micro- and Nanoelectronics and in Microelectromechanical Systems (MNE & MS 2014),

Orel, Russia, March 28 2014

1. С.И. Матюхин¹, Welcome and Seminar Openning,
   ¹Госуниверситет-УНПК
2. Турин В.О.¹, Кильчицкая М.В.², Герасимов К.А.², Simulation of power bipolar transistor,
   ¹Госуниверситет-УНПК, ²БГТУ, г. Брянск
3. Ващенко В.А., The physical ESD design for integrated circuits and electronic devices,
   Maxim Integrated Corp., г. Сан Хосе, Калифорния, США
4. Цырлов А.М., Development of CMOS optocoupler,
   ОАО «Протон», г. Орёл
5. Студенников А.С., Development of CMOS ICs,
   ОАО «Протон», г. Орёл
6. Малый Д.О.¹, Матюхин С.И.², Ставцев А.В.¹, "Proton-Elektroteks" IGBT-devices JSC: basic approaches of production and quality assurance,
   ¹ЗАО «Протон-Электротекс», г. Орёл, ²Госуниверситет-УНПК
7. Макулевский Г.Р., Матюхин С.И., Current-voltage characteristics of laser diodes based on AlGaAs,
   Госуниверситет-УНПК
8. Матюхин С.И., Гришин В.О., Radiation effects of on the current-voltage characteristic of power diodes and thyristors,
   Госуниверситет-УНПК
9. Писарев А.А.¹, Матюхин С.И.², Сурма А.М.¹, Черников А.А.¹, Electrical characteristics of fast diodes with soft recovery,
   ¹ЗАО «Протон-Электротекс», г. Орёл, ²Госуниверситет-УНПК
10. Koziol Z., Aestimo quantum mechanical software for modeling quantum wells in nanoelectronics,
    TU Rzeszow, Polska

LETI Devices Workshop

The Churchill Hotel - 1914 Connecticut Ave. NW (across from the Hilton)

Washington D.C. 6-9 p.m on December 8, 2013

Inventing the future together: a stimulating discussion of our vision for silicon nanotechnologies in the next 10 years followed by a networking cocktail. Program is as follow:

• Introduction (10min)
  Jean-René Lequepeys; VP Silicon Components Division 
• Lithography cost-effective solutions for 1X nodes (15min)
  Serge Tedesco; Lithography Program Manager 
• 3D: Dream and reality (15 min)
  Mark Scannell; Senior Business Development Manager 
• High-performance and reliable resistive memories embedded in advanced logic CMOS technologies (15min)
  Barbara de Salvo; Advanced Memories Fellow
• M&NEMS platforms: an enabler for the next generation of sensors in consumer electronics (15min)
  Hugues Metras; VP Strategic Partnerships, North America
• CMOS technologies: our most power efficient solution today and our vision toward 10nm node and beyond (15 min)
  Maud Vinet; Advanced CMOS Manager

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