[Workshop] Open Source PDKs and EDA

 Workshop 1: Open Source PDKs and EDAs, 

Community Experiences toward Democratization of Chip Design

RIHGA Royal Hotel Kyoto, Horikawa Shiokoji, Shimogyo ku, Kyoto 600 8237, Japan.

Date & Time: 5:30pm.-7:15pm on June 11 (Sun), 2023

Since its launch in 2020, the Open MPW shuttle program has received over 500 project submissions spanning 9 shuttles. This workshop will explore various topics related to designers' experiences, including measured results, foundry perspectives, and governmental expectations.

Organizers: 

• Makoto Ikeda (The University of Tokyo)
• Mehdi Saligane (University of Michigan)

Program:

1. Design experience: “The Journey of Two Novice LSI Enthusiasts: Tape-Out of CPU+RAM in Just One Month”, Kazuhide Uchiyama, University of Electro-Communications and Yuki Azuma, University of Tsukuba
2. From Zero to 1000 Open Source Custom Designs in Two Years, Mohamed Kassem, Co-founder and CTO, Efabless
3. The SKY130 Open Source PDK: Building an Open Source Innovation Ecosystem, Steve Kosier, Skywater technology
4. Open Source Chip Design on GF180MCU – A foundry perspective, Karthik Chandrasekaran, Global Foundries
5. Japan Foundries' Perspectives on Silicon design democratization, Shiro Hara, Minimal Fab & AIST
6. Google's perspective on Open source PDKs, Open source EDA tools, and OpenMPW shuttle program, Johan Euphrosine and Tim Ansell, Google
7. The Nanofabrication Accelerator Project, Matthew Daniels, NIST
8. Japanese government perspective on Silicon design democratization, Yohei Ogino, The Ministry of Economy, Trade and Industry METI

VLSI Symposium Workshop1 "Open Source PDKs and EDA" Audience

AMS Multi Project Wafer Service

AMS MPW Service:

ams' Multi Project Wafer (MPW) service, also known as shuttle runs, is a fast and cost-efficient prototyping service, which combines several designs from different customers onto a single wafer.

ams’ best in class MPW service offers significant cost advantages for foundry customers as the costs for wafers and masks are shared among a number of different shuttle participants. It includes the whole range of 0.18µm and 0.35µm specialty processes:

• CMOS Mixed Signal
• CMOS Mixed Signal with embedded EEPROM
• CMOS High Voltage (up to 120 Volts)
• CMOS High Voltage with embedded EEPROM
• CMOS Opto
• SiGe-BiCMOS

The complete MPW schedule including detailed start dates per process is available on the web at http://asic.ams.com/MPW

Deliverables: Participating the ams MPW service includes the delivery of 40 prototypes for design verification. Packaged engineering samples are offered within 2 days (ceramic) and 3 weeks (plastics) cycle time, respectively. The total turnaround time from MPW deadline to delivery is app. 8 weeks (CMOS). Overall, ams offers almost 150 MPW start dates in 2016 and 2017, enabled by long lasting co-operations with partner organizations such as CMP, Europractice, Fraunhofer IIS and Mosis. Customers located in APAC region may also participate via our local MPW program partners Toppan Technical Design Center Co., Ltd (TDC) and MEDs Technologies [read more...]

Sub-Minimum-Area MPW Sharing

Is Your Multi-Project Wafer Project Smaller Than the Fab Minimum Area?

Share the minimum area with other MPW customers to save mask costs

With the cost of mask sets going up with every node, even a multi-project wafer (MPW) can break your NRE budget, particularly if you plan to run multiple test spins. At 28nm, a 6mm2 area tile can cost over $100,000.

One solution is to share the minimum tile area with someone else who is using the same technology and metal stack that you are targeting. We periodically get these kinds of requests from customers. Please contact directly star@esilicon.com if you would like eSilicon to list your own MPW shuttle sharing opportunity, or if you would like eSilicon to contact you when future MPW tile sharing opportunities are available.

Following are upcoming opportunities to share a multi-project wafer (MPW) tapeout with another eSilicon customer. If you are interested, just email eSilicon.

Multi-Project Wafer Minimum Tile Sharing Opportunities for TSMC Technologies

Tapeout Month	Technology	Metal Stack	I/O	Price/mm2	Minimum Area	Final GDSII Due	Tapeout Date	Estimated Ship Date
October	65nm MS RF GP	1P9M_6x1z1u	2.5V	$4,700	1mm2	October 10	October 12	November 23
	65nm MS RF LP	1P9M_6x1z1u	2.5V	$4,700	1mm2	October 10	October 12	November 23
	180nm MS RF G	1P6M_4x1u	3.3V	$1,000	5mm2	October 24	October 26	December 7
November	40nm MS RF LP	1P10M	1.8V	$7,500	1mm2	October 31	November 2	January 17

[read more...]