[paper] SiC Power MOSFET SPICE modelling

Akbar Ghulam

Accurate & Complete behaviourial SPICE modelling 

of commercial SiC Power MOSFET OF 1200V, 75A

25th EuroSimE, Catania, Italy, 2024, pp. 1-4,

DOI: 10.1109/EuroSimE60745.2024.10491420

* UNIPA Palermo (IT)

Abstract: Silicon Carbide (SiC) is proved to be an excellent replacement for Silicon in high voltage and high frequency applications due to its electro-thermal properties. Since SiC power MOSFETs have only recently been more widely available commercially, accurate simulation models are immediately required to forecast device behavior and facilitate circuit designs. The goal of this paper is to develop an accurate LTSPICE model based on a modified Enz-Krumenacher-Vittoz (EKV), MOSFET model for a 1200V, 30mΩ & 75ASiC power MOSFET “SCTW100N120G2AG” provided by STMicroelectronics that is currently on the market. The modified EKV model outperforms the reduced quadratic model by describing MOSFET behavior over different zones which are weak, moderate, and strong inversion zones with only a single equation. A wide range of experimental data was used to build the model's parameters. To estimate device performance in high frequency switching applications, the model has been expanded to include package parasitic components that include parasitic capacitances. The model's static and transient properties were simulated, and the results were compared with those acquired from the actual device.

FIG: The SiC MOSFET's circuit schematic utilizing a modified EKV model

Acknowledgements: We would like to thank STMicroelectronics, as for completion of this study has been greatly aided by their participation and availability of relevant data.

[paper] Modeling a 2D Electrostatic Potential in MOS Devices

Francois Lim, Benjamin Iñiguez, Alexander Kloes

A new analytical method for modeling a 2D electrostatic potential in MOS devices, 

applicable to compact modeling

J. Appl. Phys. 28 January 2024; 135 (4): 044501

DOI: 10.1063/5.0188863

Abstract: This paper presents a new conformal mapping method to solve 2D Laplace and Poisson equations in MOS devices. More specifically, it consists of an analytical solution of the 2D Laplace equation in a rectangular domain with Dirichlet boundary conditions, with arbitrary values on the boundaries. The advantages of the new method are that all four edges of the rectangle are taken into account and the solution consists of closed-form analytical expressions, which make it fast and suitable for compact modeling. The new model was validated against other similar methods. It was found that the new model is much faster, easier to implement, and avoids many numerical issues, especially near the boundaries, at the cost of a very small loss in accuracy.

FIG: (a) The calculated 2D potential from the closed-form analytic model,
for a Double Gate MOSFET with tsc=12nm, tox=1.6nm, and L=25nm.
(b) Corresponding equipotentials. 

Acknowledgments: This work was funded by the Spanish Ministry of Science through Contract No. PRX21/00726.

[paper] Universal Charge Model for Multigate MOS Structures

Kwang-Woon Lee and Sung-Min Hong

Derivation of a Universal Charge Model for Multigate MOS Structures

with Arbitrary Cross Sections

IEEE TED (2022, Early Access)

DOI:  10.1109/TED.2022.316486

   

* Gwangju Institute of Science and Technology (KR)

Abstract: A universal equation for the charge-voltage characteristics in the multigate metal oxide semiconductor (MOS) structure with an arbitrary cross section is presented. A generalized coordinate is proposed and the Poisson equation is integrated with a weighting factor related with the generalized coordinate and the electric field. A compact charge model is derived and analytic and numerical examples for various MOS structures are shown.

Fig: Thin slab in the semiconductor channel region of the multigate MOS structure. The A∗ surfaces are perpendicular to the z-direction, which is the transport direction and its generalized coordinate, ψ, for rectangular nanosheet MOS structures at 0.0 V (top) and 0.7 V (bottom).

Aknowlegements: This workwas supported by the National Research Foundation of Korea (NRF) Grant funded by the Korean Government under Grant NRF- 2019R1A2C1086656 and Grant NRF-2020M3H4A3081800.

[papers] compact/SPICE modeling

[1] M. Müller, P. Dollfus and M. Schröter, "1-D Drift-Diffusion Simulation of Two-Valley Semiconductors and Devices," in IEEE Transactions on Electron Devices, vol. 68, no. 3, pp. 1221-1227, March 2021, doi: 10.1109/TED.2021.3051552.

Abstract: A two-valley formulation of 1-D drift-diffusion transport is presented that takes the coupling between the valleys into account via a new approximation for the nonlocal electric field. The proposed formulation is suitable for the simulation of III–V heterojunction bipolar transistors as opposed to formulations that employ the single electron gas approximation with a modified velocity-field model, which also causes convergence problems. Based on Boltzmann transport equation simulations, model parameters of the proposed two-valley formulation are given for GaAs, InP, InAs, and GaSb at room temperature. Applications of the new formulation are also demonstrated. 
Code/Dataset: This article contains datasets made available via IEEE DataPort, a repository of datasets intended to facilitate analysis and enable reproducible research. Click the dataset name below to access it on the IEEE DataPort website.

[2] A. Rawat et al., "Experimental Validation of Process-Induced Variability Aware SPICE Simulation Platform for Sub-20 nm FinFET Technologies," in IEEE Transactions on Electron Devices, vol. 68, no. 3, pp. 976-980, March 2021, doi: 10.1109/TED.2021.3053185.

Abstract:We propose an experimentally validated physics-based process-induced variability (PIV) aware SPICE simulation framework–enabling the estimation of performance variation due to line-edge-roughness (LER), metal-gate-granularity (MGG), random-dopant-fluctuation (RDF), and oxide-thickness-variation (OTV) at sub-20 nm technology node devices. The framework utilizes LER, RDF, OTV, and MGG defining parameters such as fin-edge correlation coefficient (ρ), autocorrelation length (Λ), grain-size (GS), σ[EOT], etc. as the inputs, and produces IdVg distribution of ensemble size 250 as an output. We have validated the framework against 14 nm FinFET experimental data for IdVg trends as well as for the threshold-voltage (Vth), ON-current (Ion), and subthreshold slope (SS) distributions for a range of device dimensions with a reasonably good match. The worst and the best case R square errors are 0.64 and 0.98, respectively, for the validation. The very nature of the proposed framework allows the designers to use it for a vast range of process technologies. Such models are of dual importance, as it enables a PIV aware prediction of circuit-level performance, and provides a platform to estimate PIV parameters efficiently, on-par with sophisticated structural characterization tools.

[3] Blake W. Nelson, Andrew N. Lemmon, Sergio J. Jimenez, H. Alan Mantooth, Brian T. DeBoi, Christopher D. New, Md Maksudul Hossain, "Computational Efficiency Analysis of SiC MOSFET Models in SPICE: Dynamic Behavior," in IEEE Open Journal of Power Electronics, vol. 2, pp. 106-123, 2021, doi: 10.1109/OJPEL.2021.3056075.

Abstract: Transient simulation of complex converter topologies is a challenging problem, especially in detailed analysis tools like SPICE. Transistor models presented for SPICE are often evaluated by accuracy, with less consideration for the computational cost of model elements. In order to optimize models for application simulations, this research quantifies the relative simulation performance of modeling approaches and contextualizes the results with regard to accuracy. It is well established that the primary contributor to semiconductor dynamic behavior is the voltage-dependent interelectrode capacitances. Therefore, this study isolates these model components to resolve their influence on model accuracy and run-time. Both the voltage-dependencies modeled, and the mathematic formulation chosen strongly influence the accuracy of interelectrode capacitance models. In addition to these factors, the specific implementation chosen within SPICE also determines simulation performance. Through careful evaluation of these factors, this study offers specific recommendations for optimal implementations of interelectrode capacitances in SPICE.

Fig: DPT system schematic, components, and metrology.

[4] Sherif M. Sharroush & Yasser S. Abdalla; Parameter extraction and modelling of the MOS transistor by an equivalent resistance, Mathematical and Computer Modelling of Dynamical Systems, (2021) 27:1, 50-86, DOI: 10.1080/13873954.2020.1857790

Abstract: During the analysis of multi-transistor circuits, the need arises to evaluate the time delay or the power consumption of the circuit. Due to the complexity of the transistor model, several complicated equations arise from which a compact-form solution cannot be obtained and a suitable physical insight cannot be drawn. With this regard, two contributions are presented in this paper. The first one is a fully analytical parameter extraction approach to be applied on the MOS transistors. The second one is a quantitative method for simplifying the analysis of MOS circuits by modelling the MOS transistor by a suitable equivalent resistance adopting the time-delay or the power-consumption equivalence criteria. The parameter-extraction method is verified by using the extracted parameters in the derived expressions according to the second contribution. Compared to other representations, the agreement of the proposed model with the simulation results is very good.

Fig: Finding Vthn0 as the intercept of the linear portion of the Id-Vgs characteristics with the horizontal axis. The curve corresponds to Vds=1V. The term ‘exact relationship’ means data from the simulation results

[paper] Modeling Power GaN-HEMTs in SPICE

Utkarsh Jadli, Faisal Mohd-Yasin, Hamid Amini Moghadam, Peyush Pande*, Mayank Chaturvedi and Sima Dimitrijev

Modeling Power GaN-HEMTs Using Standard MOSFET Equations and Parameters in SPICE

Electronics 2021, 10, 130

DOI: 10.3390/electronics10020130

Queensland Micro- and Nanotechnology Centre, Griffith University, Brisbane, QLD 4111, Australia;

*Electronics Department, Graphic Era (Deemed to Be University), Dehradun, Uttarakhand 248002, India;

Abstract: The device library in the standard circuit simulator (SPICE) lacks a gallium nitride based high-electron-mobility-transistor (GaN-HEMT) model, required for the design and verification of power-electronic circuits. This paper shows that GaN-HEMTs can be modeled by selected equations from the standard MOSFET LEVEL3 model in SPICE. A method is proposed for the extraction of SPICE parameters in these equations. The selected equations and the proposed parameter-extraction method are verified with measured static and dynamic characteristics of commercial GaN-HEMTs. Furthermore, a double pulse test is performed in LTSpice and compared to its manufacturer model to demonstrate the effectiveness of the MOSFET LEVEL3 model. The advantage of the proposed approach to use the MOSFET LEVEL3 model, in comparison to the alternative behavioral-based model provided by some manufacturers, is that users can apply the proposed method to adjust the parameters of the MOSFET LEVEL3 model for the case of manufacturers who do not provide SPICE models for their HEMTs.

Fig: Internal cross-sectional structure of GaN-HEMT

Acknowledgments: The authors would like to acknowledge the Innovative Manufacturing Co- operative Research Centre (IMCRC) for providing a PhD scholarship to the first author. We also acknowledge the School of Engineering and Built Environments (EBE) of Griffith University for funding this project. This work was performed in part at the Queensland node of the Australian National Fabrication Facility, a company established under the National Collaborative Research Infrastructure Strategy to provide nano- and micro-fabrication facilities for Australia’s researchers.

[paper] Symmetric Source and Drain Voltage Clamping Scheme

K. Xia¹ (Senior Member, IEEE)

Symmetric Source and Drain Voltage Clamping Scheme

for Complete Source-Drain Symmetry in Field-Effect Transistor Modeling

in IEEE Transactions on Electron Devices

DOI: 10.1109/TED.2020.3004799

¹NXP Semiconductors N.V., Chandler, AZ 85224 USA

Abstract: For structurally symmetric field-effect transistors with respect to the source and the drain, their models should be electrically symmetric about the source-drain interchange. This article shows that the commonly used drain-source voltage clamping technique breaks such a symmetry. This article then presents a symmetric source and drain voltage clamping scheme to solve the problem. The effectiveness of the new scheme is demonstrated by both the planar MOSFET model PSP and the FinFET model BSIM-CMG.

Fig: Fourth order derivative of I_x with respect to V_x during Gummel symmetry test for an n-MOSFET on a 130nm technology. V_g = 1.15V. Vb = 0V. W/L = 10.02μm/0.15μm. V_d = −V_s = V_x. T=27^◦C. V_x stepsize is 10mV in the measurement and 0.1mV in the simulation, respectively.

[paper] A Compact Model for SiC Schottky Barrier Diodes Based on the Fundamental Current Mechanisms

J. R. Nicholls and S. Dimitrijev

Queensland Micro- and Nanotechnology Centre

School of Engineering and Built Environment

Griffith University, Brisbane, QLD 4111, Australia

A Compact Model for SiC Schottky Barrier Diodes Based on the Fundamental Current Mechanisms

IEEE Journal of the Electron Devices Society

doi: 10.1109/JEDS.2020.2991121.

Abstract - We develop a complete compact model to describe the forward current, reverse current, and capacitance of SiC Schottky barrier diodes. The model is based on the fundamental current mechanisms of thermionic emission and tunneling, and is usable over a large range of voltages, temperatures, and for a large range of device parameters. We also demonstrate good agreement with measured data. Furthermore, the development of this model outlines a methodology for transforming a tunneling equation into a compact form without numerical integration-this methodology can potentially be applied to other device structures.

Fig: (a) Structure of a Schottky barrier diode. (b) Equivalent circuit of a Schottky barrier diode, consisting of two current sources (for the forward and reverse bias currents), a shunt capacitance and a series resistance

Acknowledgement - This work was performed at the Queensland Microtechnology Facility (Griffith University), part of the Queensland node of the Australian National Fabrication Facility (ANFF), a company established under the National Collaboration Research Infrastructure Strategy to provide nanofabrication and microfabrication facilities to Australia’s researchers. 

URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9081977&isnumber=6423298

[paper] Two Transistors Voltage-Measurement-Based Test Structure for Fast MOSFET Device Mismatch Characterization

J. P. M. Brito and S. Bampi

Two Transistors Voltage-Measurement-Based Test Structure 

for Fast MOSFET Device Mismatch Characterization

IEEE Transactions on Semiconductor Manufacturing

doi: 10.1109/TSM.2020.2988095

Abstract - This work presents a test structure targeted to measure MOSFET mismatches with a fast method. It relies on two single-spot voltage measurements in order to extract VTH and β/β separately. The new methodology gives a theoretical increase in the measurement speed of 30x (23.17x in practice). The coefficient of determination (R2) of the linear regression analysis is used to compare standalone transistor measurements against the new proposed methodology. The correlation in the data demonstrates values not less than 0.94 (R2≥ 0.94). The test structure can reproduce parameter correlations, and it is capable of extracting MOSFET mismatch design parameters, such as Pelgrom’s AVTH, with an error of 2% and Aβ, with a negligible error. The experimental data presented herein are taken from measurements in prototypes fabricated in a 65nm CMOS bulk process. The whole circuit is composed of 16 2D addressable DUT device matrices, each having 256 same-size closely-placed MOSFET devices, totaling 4,096 MOS devices used in single-type (NMOS) transistor array. 

URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9068274&isnumber=5159394

conference paper reached 700 reads

M. Bucher, A. Bazigos and W. Grabinski, "Determining MOSFET Parameters in Moderate Inversion," 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems, Krakow, 2007, pp. 1-4.

Abstract: Deep submicron CMOS technology scaling leads to reduced strong inversion voltage range due to non-scalability of threshold voltage, while supply voltage is reduced. Moderate inversion operation therefore becomes increasingly important. In this paper, a new method of determining MOSFET parameters in moderate inversion is presented. Model parameters are determined using a constant current bias technique, where the biasing current is estimated from the transconductance-to-current ratio. This technique is largely insensitive to mobility effects and series resistance. Statistical data measured on 40 dies a 0.25 um standard CMOS technology are used for the illustration of this method.

[paper] Improvements to a compact MOSFET model for design by hand

Improvements to a compact MOSFET model for design by hand

A. de Jesus Costa, F. Martins Cardoso, E. Pinto Santana and A. I. Araújo Cunha

15th IEEE NEWCAS

Strasbourg, France, 2017, pp. 225-228

doi: 10.1109/NEWCAS.2017.8010146

Abstract: In this work, an improved version of the basic structure of a compact MOSFET model and the respective parameters extraction methodology are proposed. The aim of this approach is to increase accuracy in hand calculations for analog circuit design without significantly increasing its complexity. The influences of both inversion level and channel length are considered in the modeling of a few features such as mobility, threshold voltage and onset of saturation. Simple design examples of current sinks and sources are accomplished to compare the basic and the improved models [read more...]

[paper] A Compact Model for the Statistics of the Low-Frequency Noise of MOSFETs With Laterally Uniform Doping

M. Banaszeski da Silva, H. P. Tuinhout, A. Zegers-van Duijnhoven, G. I. Wirth and A. J. Scholten

"A Compact Model for the Statistics of the Low-Frequency Noise of MOSFETs With Laterally Uniform Doping" 

in IEEE TED, vol. 64, no. 8, pp. 3331-3336, Aug. 2017.
doi: 10.1109/TED.2017.2713301

Abstract: In this paper, we develop a compact physics-based statistical model for random telegraph noise-related low-frequency noise in bulk MOSFETS with laterally uniform doping. The proposed model is suited for modern compact device models, such as PSP, BSIM, and EKV. With our proposed model, one can calculate the expected value and the variability of the noise as a function of bias and device parameters. We validate the model through numerous experimental results from different CMOS nodes, down to 40 nm [read more...]

[paper] A Compact Model for the Statistics of the Low-Frequency Noise of MOSFETs With Laterally Uniform Doping

A Compact Model for the Statistics of the Low-Frequency Noise of MOSFETs With Laterally Uniform Doping

M. Banaszeski da Silva; H. P. Tuinhout; A. Zegers-van Duijnhoven; G. I. Wirth; A. J. Scholten;

in IEEE Transactions on Electron Devices, vol.PP, no.99, pp.1-6
doi: 10.1109/TED.2017.2713301

Abstract: In this paper, we develop a compact physics-based statistical model for random telegraph noise-related low-frequency noise in bulk MOSFETS with laterally uniform doping. The proposed model is suited for modern compact device models, such as PSP, BSIM, and EKV. With our proposed model, one can calculate the expected value and the variability of the noise as a function of bias and device parameters. We validate the model through numerous experimental results from different CMOS nodes, down to 40 nm. [read more...]

[Incize] Senior Semiconductor R&D Engineer

Incize is recruiting a senior semiconductor R&D engineer for a three-year research project. The project aims to develop an innovative semiconductor characterization technique that is of great interest for the semiconductor industry.

What Incize offers:

• Permanent contract
• Infinite opportunities to learn
• Friendly and flexible environment
• Competitive salary

What Incize requires:

• PhD in physics, electronics or material science
• Knowledge of semiconductor physics, microwave theory, optics and their applications
• Experience  in  designing  and  running  experiments  in  microwave  and  optics domains
• Experience in TCAD and ADS simulations
• Clean-room experience is an advantage
• Passion for research and innovation
• 2-3 years of experience in R&D after PhD

Your Responsibilities

• Development of a new characterization method and its theoretical background
• Planning and execution of experiments
• Numerical TCAD and ADS simulations
• Literature search

How to apply

Please send your CV, a list of publications and a cover letter to info@incize.com with the subject line job_RD01_2016_lastname. References should be provided upon request.

About Incize

Incize provides characterization and modelling services for semiconductor foundries and fabless companies. It is a spin-off from Université catholique de Louvain and is based in Louvain-la-Neuve, Belgium. Visit www.incize.com to find out more.

www.incize.com

Chemin du Cyclotron, 6

B-1348 Louvain-la-Neuve, Belgium

T: +32 10 39 22 60

F: +32 10 39 20 01

Semiconductor Devices Characterization Seminar

Technical Seminars addressing the challenges of CMOS, Power and RF

semiconductor device measurement and modeling 

Agilent and it´s 25 collaborative partners invite you to attend this complimentary technical seminar on characterization and modeling of semiconductor devices. Two tracks in parallel will address the needs for:

• Small scale silicon industry
• Power silicon industry and RF Power

Common topics to both Tracks:

• Live demonstration of GaN device characterization flow: DC I-V characteristic extraction, RF Power measurement, Spice models creation for further usage in design stage.

CMOS Track:

• Accurate and repeatable on-the-wafer device extraction – Cascade Microtech
• DC characterization for emerging nano-technologies
• Flicker Noise and Random Telegraph Noise
• Spice model libraries optimization for dedicated application

Power & RF Power Track:

• High Power Devices measurement
• III-V devices spice model (DynaFET)
• Nonlinear Component characterization
• Non-50ohm Load Pull solution – Maury

Where/when:
To obtain the detail agenda of the nearest session, please select one of the locations below.

Country	City	Date	More Information
FR	Grenoble	18 September 2014	Register here
FI	Helsinki	23 September 2014	Register here
DE	Munich	30 September 2014	Register here
DE	Dresden	2 October 2014	Register here
CH	Lausanne	14 October 2014	Register here
BE	Leuven	16 October 2014	Register here
NL	Eindhoven	17 October 2014	Register here
SW	Goteborg	28 October 2014	Register here
UK	Cambridge	30 October 2014	Register here
FR	Les Ulis	6 November 2014	Register here

 

 

Call for IJNM papers: Noise modeling of high-frequency semiconductor devices

INTERNATIONAL JOURNAL OF NUMERICAL MODELLING: ELECTRONIC NETWORKS, DEVICES AND FIELDS Int. J. Numer. Model. (2014)

Call for IJNM papers: Noise modeling of high-frequency semiconductor devices 

Noise processes in solid-state active devices often determine their fundamental operational limits. This is especially true in situations where a device operates under tight sensitivity and accuracy constraints, as is the case in satellite communication systems, aerospace instrumentation, and deep-space radio astronomy. Today’s ultra-high frequency transistors that meet these demanding low-noise performance characteristics often leverage progressive device downscaling techniques in conjunction with improved semiconductor alloys. 

To enable the design of next-generation low-noise devices, however, accurate and flexible models that characterize the connection between the physics of microscopic noise processes and measurable macroscopic performance are called for. The objective of this Special Issue is to collect and disseminate recent results addressing the topic of modeling and simulation of the macroscopic noise performance of high- frequency transistors including but not limited to GaAs-based and GaN-based field-effect transistors, Si metal–oxide–semiconductor FETs and FinFETs, InP-based high-electron-mobility transistors, and GaAs and SiGe heterojunction bipolar transistors. It is worth pointing out that because of frequency up-conversion phenomena caused by a device’s nonlinearities, low frequency noise processes may strongly impact microwave and millimeter wave behavior as well. Contributions focusing on low-frequency noise modeling therefore will be considered as well. 

This issue will include both invited and contributed manuscripts.

Manuscripts for this Special Issue should adhere to the requirements for regular papers of the IJNM as specified in the Author Guidelines at 

http://onlinelibrary.wiley.com/journal/10.1002/(ISSN)1099-1204/ homepage/ForAuthors.html. 

Potential contributors may contact the Guest Editors to determine the suitability of their contribution to the Special Issue. All manuscripts should be submitted via the IJNM’s manuscript website, with a statement that they are intended for this Special Issue. 

Guest Editors: 
Prof. Alina Caddemi University of Messina, Italy Email:
Prof. Ernesto Limiti University of Rome Tor Vergata, Italy Email:

Manuscript submission deadline: July 31, 2014

Compact DC Modeling of Organic Field-Effect Transistors: Review and Perspectives

In spite of impressive improvements achieved for organic field-effect transistors (OFETs), there is still a lack of theoretical understanding of their behaviors. Furthermore, it is challenging to develop a universal model that would cover a huge variety of materials and device structures available for state-of-the-art OFETs. Nonetheless, currently there is a strong need for specific OFET compact models when device-to-system integration is an important issue. We briefly describe the most fundamental characters of organic semiconductors and OFETs, which set the bottom line dictating the requirement of an original model different from that of conventional inorganic devices. Along with an introduction to the principles of compact modeling for circuit simulation, a comparative analysis of the reported models is presented with an emphasis on their primary assumptions and applicability aspects. Critical points for advancing OFET compact models are discussed in consideration of the recent understanding of device physics.

[1] Kim, C.-H.; Bonnassieux, Y.; Horowitz, G., "Compact DC Modeling of Organic Field-Effect Transistors: Review and Perspectives," Electron Devices, IEEE Transactions on , vol.61, no.2, pp.278,287, Feb. 2014
doi: 10.1109/TED.2013.2281054
URL