[webinar] Power WBG Semiconductor Technology Opportunities

"Power WBG Semiconductor Technology Opportunities"

webinar hosted by 

Dr. Victor Veliadis, 

Executive Director and CTO of PowerAmerica, 

a WBG semiconductor power electronics consortium

Event by Łukasiewicz - Institute of Microelectronics and Photonics

Register now: https://lukasiewiczimif.clickmeeting.com/poweramerica/register

Silicon power devices have dominated power electronics due to their excellent starting material quality, ease of fabrication, low-cost volume production, and proven reliability. However, they’re approaching their operational limits primarily due to their relatively low bandgap and critical electric field that results in high conduction and switching losses, and poor high-temperature performance. So what can we do? Well, let’s talk about the favorable WBG material properties, their volume application opportunities, and last but not least let's highlight the respective competitive advantages of SiC and GaN.

You will additionally learn about:

• the lateral and vertical power device configurations that will be analyzed in the context of bidirectional switching
• specific applications and needs for bidirectional switches
• key topologies, enabled by bidirectional switches
• PowerAmerica’s work to accelerate WBG power electronics commercialization

About Dr. Veliadis: Dr. Victor Veliadis is Executive Director and CTO of PowerAmerica, a WBG semiconductor power electronics consortium. At PowerAmerica, he has managed a budget of $146 million that he strategically allocated to 200 industrial and University projects to accelerate WBG semiconductor clean energy manufacturing, workforce development, and job creation. His PowerAmerica educational activities have trained 410 University FTE students in applied WBG projects, and engaged 4100 attendees in tutorials, short courses, and webinars. Dr. Veliadis is an ECE Professor at NCSU and an IEEE Fellow and EDS Distinguished Lecturer. He has 27 issued U.S. patents, 6 book chapters, and over 125 peer-reviewed publications. Prior to entering academia and taking an executive position at Power America in 2016, Dr. Veliadis spent 21 years in the semiconductor industry where his work included design, fabrication, and testing of SiC devices, GaN devices for military radar amplifiers, and financial and operations management of a commercial semiconductor fab. He has a Ph.D. degree in Electrical Engineering from John Hopkins University (1995).

[paper] SPICE Modeling and Circuit Demonstration of a SiC Power IC Technology

Tianshi Liu¹, Hua Zhang¹, Sundar Babu Isukapati², Emran Ashik³, Adam J. Morgan², Bongmook Lee³, Woongje Sung², Ayman Fayed¹, Marvin H. White¹, and Anant K. Agarwal¹

SPICE Modeling and Circuit Demonstration of a SiC Power IC Technology

IEEE Journal of the Electron Devices Society, vol. 10, pp. 129-138, 2022, 

DOI: 10.1109/JEDS.2022.315036

   
1 Department of Electrical & Computer Engineering, The Ohio State University, Columbus, OH 43210, USA
2 College of Nanoscale Science and Engineering, State University of New York Polytechnic Institute, Albany, NY 12309, USA
3 Department of Electrical & Computer Engineering, North Carolina State University, Raleigh, NC 27695, USA

Abstract: Silicon carbide (SiC) power integrated circuit (IC) technology allows monolithic integration of 600 V lateral SiC power MOSFETs and low-voltage SiC CMOS devices. It enables application-specific SiC ICs with high power output and work under harsh (high-temperature and radioactive) environments compared to Si power ICs. This work presents the device characteristics, SPICE modeling, and SiC CMOS circuit demonstrations of the first two lots of the proposed SiC power IC technology. Level 3 SPICE models are created for the high-voltage lateral power MOSFETs and low-voltage CMOS devices. SiC ICs, such as the SiC CMOS inverter and ring oscillator, have been designed, packaged, and characterized. Proper operations of the circuits are demonstrated. The effects of the trapped interface charges on the characteristics of SiC MOSFETs and SiC ICs are also discussed.

FIG: Cross-sectional view of the SiC MOSFETs (lot2)

Acknowledgment The authors would like to thank the team at Analog Devices (ADI), Hillview facility for the fabrication of devices and Advanced Research Projects Agency-Energy (ARPA-E). The authors also thank D. Xing for providing the customized gate driver for the dynamic characterizations of the circuits

[paper] Modeling of SIC VDMOS FET

Anirban Kar∗, Ahtisham Pampori∗, Noriyoshi Hashimoto† and Yogesh Singh Chauhan∗

A Charge-Based Silicon Carbide MOSFET Compact Model for Power Electronics Applications

2021 IEEE 8th Uttar Pradesh Section UPCON)

DOI: 10.1109/UPCON52273.2021.9667643

∗Department of Electrical Engineering, IIT Kanpur (IN)
†Keysight Technologies (J)

Abstract: This paper presents a charge-based compact model for Silicon Carbide (SiC) power MOSFETs, which captures the static characteristics of the device over a wide range of voltages and currents. The drift region resistance and charges in the channel have been formulated to calculate the drain current in a self-consistent manner. The proposed model has been validated against the measured transfer and output characteristics of a commercial 1.2kV power MOSFET (Infineon IMW120R045M1) with a maximum current rating of 52A.

Fig: a) Transfer characteristics of SiC MOSFET with Vd=1 to 20V

b) Transconductance of SiC MOSFET with Vd=1 to 20V 

Acknowledgement: This work was supported in part by the Swarna Jayanti Fellowship under Grant DST/SJF/ETA02/2017-18 and in part by the Department of Science and Technology through the FIST Scheme under Grant SR/FST/ETII-072/2016 and Keysight Technologies, USA. The measurement of the device was carried out at Keysight Technologies, Japan.

[paper] Compact Model for SiC Power MOSFETs

Cristino Salcines¹, Sourabh Khandelwal² and Ingmar Kallfass¹ 

A Compact Model for SiC Power MOSFETs 

for Large Current and High Voltage Operation Conditions 

(2021) arXiv-2104. 

1 University of Stuttgart Stuttgart, Germany

2 Macquarie University Sydney, Australia  

Abstract: This work presents a physics based compact model for SiC power MOSFETs that accurately describes the I-V characteristics up to large voltages and currents. Charge-based formulations accounting for the different physics of SiC power MOSFETs are presented. The formulations account for the effect of the large SiC/SiO2 interface traps density characteristic of SiC MOSFETs and its dependence with temperature. The modeling of interface charge density is found to be necessary to describe the electrostatics of SiC power MOSFETs when operating at simultaneous high current and high voltage regions. The proposed compact model accurately fits the measurement data extracted of a 160 milli ohms, 1200V SiC power MOSFET in the complete IV plane from drain-voltage Vd = 5mV up to 800 V and current ranges from few mA to 30 A.

Fig: Output characteristics up to high current and high voltage in logarithmic scale for VGS = 6V to 20V in steps of 0.5V. Symbols are measurements and solid lines simulations of the proposed model. The logarithmic scale eases the visualization of both low and high VDS voltages in a single graph.

[Si2 CMC] to Standardize SPICE Model for SiC MOSFET

May 03, 2021 // By Peter Clarke [eenewsanalog.com] 

The Compact Model Coalition (CMC) working group of the Silicon Integration Initiative (SI2) has agreed to standardize a model for the behaviour of a silicon-carbide MOSFET.

Silicon-carbide offers higher efficiency and faster operation than silicon and has been adopted for several power applications including photovoltaic inverters and converters, industrial motor drives, electric vehicle powertrain and EV charging, and power supply and distribution. A CMC working group will oversee the model development with Analog Devices, Cadence Design Systems, Infineon, Qualcomm, Siemens EDA, Silvaco and Synopsys set to participate.

"I'd encourage companies with a stake in silicon-carbide devices to join this effort and help guide selection of the model which best represents their intended use," 

advised Peter Lee, chair of the CMC.

Now in its 25th year, the Si2 Compact Model Coalition provides semiconductor manufacturers, designers, and simulation tool providers a means to pool resources to fund standardization and optimization of standard compact SPICE models and standard interfaces to promote simulation tool interoperability [Read more...]

[paper] SiC MOSFET SPICE Model

Lefdal Hove, Haavard, Ole Christian Spro, Giuseppe Guidi

and Dimosthenis Peftitsis

Improved SiC MOSFET SPICE Model to Avoid Convergence Errors

Materials Science Forum 1004 (July 2020): 856–64

DOI: 10.4028/www.scientific.net/msf.1004.856

Abstract: This paper presents improvements to a SPICE model for a commercially available SiC MOSFET to avoid convergence errors while still providing reliable simulation results. Functionality in the internal part of the model that shapes the transconductance of the device according to its junction temperature and gate-source voltage dependency has been improved to provide a continuous characteristic rather than the initial discontinuous performance. Furthermore, the output characteristics from the initial and the proposed model have been compared to lab measurements of an actual device. The results show that the proposed and initial model provide equally reliable simulation results. However, the proposed model does not run into convergence problems.

References 

[1] X. She, A. Huang, O. Lucia, and B. Ozpineci, Review of Silicon Carbide Power Devices and Their Applications, IEEE Transactions on Industrial Electronics, vol. 64, no. 10, p.8193–8205, (2017).

[2] J. Rabkowski, D. Peftitsis, and H. P. Nee, Silicon carbide power transistors: A new era in power electronics is initiated, IEEE Industrial Electronics Magazine, vol. 6, no. 2, p.17–26, (2012).

[3] A. Stefanskyi, L. Starzak, A. Napieralski, and M. Lobur, Analysis of SPICE models for SiC MOSFET power devices,, 2017 14th CADSM 2017 - Proceedings, p.79–81, (2017).

[4] H. L. Hove, O. C. Spro, D. Peftitsis, G. Guidi, and K. Ljøkelsøy, Minimization of dead time effect on bridge converter output voltage quality by use of advanced gate drivers, 2019 10th ICPE 2019 ECCE Asia, (2019).

[5] N. Mohan, T. Undeland, and W. Robbins, Power Electronics; Converters, Applications, and Design, third ed., Wiley, (2003).

[6] C. Enz, F. Krummenacher, and E. Vittoz, An Analytical MOS Transistor Model Valid in All Regions of Operation and Dedicated to Low-Voltage and Low-Current Application, Analog Integrated Circuits and Signal Processing, vol. 8, p.83–114, (1995).

[7] M. Bucher, C. Lallement, C. Enz, F. Théodoloz, and F. Krummenacher, The EPFL-EKV MOSFET Model Equations for Simulation Technical Report V2.6,, EPFL, Lausanne, Switzerland, (1999).

[8] B. N. Pushpakaran, S. B. Bayne, G. Wang, and J. Mookken, Fast and accurate electro-thermal behavioral model of a commercial SiC 1200V, 80 mΩ power MOSFET,, Digest of Technical Papers IEEE IPPC, vol. 2015-Octob, p.1–5, (2015).

[slides] (Ultra-) Wide-Bandgap Devices

(Ultra-) Wide-Bandgap Devices: Reshaping the Power Electronics Landscape

Presenter Dr. Yuhao Zhang, Assistant Professor,
Center for Power Electronics Systems, Virginia Tech

IEEE EDS SCV-SF Seminar 

Friday, June 12, 2020 at 12PM – 1PM PDT

Abstract: Power electronics is the application of solid-state electronics for the control and processing of electrical energy. It is used ubiquitously in consumer electronics, electric vehicles, data centers, renewable energy systems, and smart grid. The power semiconductor device, as the cornerstone technology in power electronics, is key to improving the efficiency, cost and form factor of power electronic systems.  Recently, the power electronics landscape has been significantly reshaped with the production and application of power devices based on wide-bandgap (WBG) semiconductors, such as gallium nitride (GaN) and silicon carbide (SiC). Besides advancing the performance of traditional power systems, WBG devices have also enabled many emerging applications that are beyond the realm of silicon (Si) as well as changed the manufacturing paradigm of power electronics. On the horizon is the power devices based on ultra-wide-bandgap (UWBG) materials, which promises superior performance over GaN and SiC and is at the relatively early stage of research development.  This talk will provide a comprehensive overview of major WBG and UWBG power device technologies, spanning materials, devices, reliability and applications. Some research projects in the PI’s group in collaboration with industry will also be introduced.

FIG: WBG Semiconductor: Superior Power Semiconductor Over Si

The seminar presentation is now available on our IEEE EDS SCV-SF webpage:
http://site.ieee.org/scv-eds/files/2020/06/SCV_SF_EDS_Yuhao_Zhang_excerpt.pdf

More information at the IEEE EDS Santa Clara Valley-San Francisco Chapter Home Page. Subscribe or Invite your friends to sign up for our mailing list and get to hear about exciting electron-device relevant talks. We, EDS SCV-SF, promise no spam and try to minimize email. You can (un)subscribe easily.

Open PhD/PostDoc positions at the University of Pisa

device and 2D materials modeling, analog circuit design, 

power electronics, wireless sensors design

We are in the process of opening a few positions for PhD students and for Post Docs at the University of Pisa, in the fields of modeling of nanoscale electron devices, 2D materials, analog circuit design, power electronics design and wireless sensors for harsh environments. We are now asking for expressions of interest from perspective candidates.

I would be very grateful if you could forward this information to whom you think could be interested in applying.

Expressions of interest must be submitted by email, together with a CV and contact information by 31 Dec 2019 to giuseppe.iannaccone@unipi.it.

The available research topics are listed below. They are typically performed in the framework of a larger project within a European collaboration or of a bilateral project with an industrial sponsor.

1. Theoretical investigation of ultra-low-power nanoscale transistors and memories for large scale integrated circuits. This will include devices based on heterostructures of 2D materials. We are looking for candidates with strong background in Electrical Engineering and/or Physics.

2. Quantum engineering of materials and devices based on heterostructures of 2D materials. This activity is based on materials modeling with quantum chemistry methods and quantum transport modeling. We are looking for candidates with strong background in Physical Chemistry and/or Physics.

3. Design of low-power analog integrated circuits for analog hardware  accelerators of artificial intelligence (deep learning) algorithms and for new computing architectures. We are looking for candidates with strong background in Electrical Engineering.

4. Design of low-power mixed signal circuits for security hardware, such as physical unclonable functions and hardware security signatures. We are looking for candidates with strong background in Electrical Engineering.

5. Modeling of power devices based on GaN and SiC for performance and reliability optimization and model development. We are looking for candidates with strong background in Electrical Engineering and/or in Physics.

6. Design of highly efficient power management circuits and systems based on switched capacitors. Both circuits based on silicon technology, on SiC and on GaN will be considered. We are looking for candidates with strong background in Electrical Engineering.

PhD positions are for three years, Post Doc positions are initially for one year and might be renewed for up to four years. Positions of shorter duration (for visiting students/scholars or for MS  thesis projects) might be considered depending on the expertise of the candidate and the definition of a suitable subproject.

For additional information and specific information on the projects, please send an email to
Prof. Giuseppe Iannaccone
giuseppe.iannaccone@unipi.it

[papers] Compact Modeling

Q. C. Nguyen, P. Tounsi, J. Fradin and J. Reynes, "Development of SiC MOSFET Electrical Model and Experimental Validation: Improvement and Reduction of Parameter Number," 2019 MIXDES - 26th International Conference "Mixed Design of Integrated Circuits and Systems", Rzeszów, Poland, 2019, pp. 298-301.

doi: 10.23919/MIXDES.2019.8787050

Abstract: In this work, a new approach for electrical modeling of Silicon Carbide (SiC) MOSFET is presented. The developed model is inspired from the Curtice model which is using a mathematic function reflecting MOSFET output characteristics. The first simulation results showed good agreement with measurements. Improvement is needed in order to increase model accuracy and to take into account the influence of the junction temperature on device characteristics.

D. Kasprowicz, "Semiconductor Device Parameter Extraction Based on I–V Measurements and Simulation," 2019 MIXDES - 26th International Conference "Mixed Design of Integrated Circuits and Systems", Rzeszów, Poland, 2019, pp. 321-326.

doi: 10.23919/MIXDES.2019.8787195

Abstract: The paper presents a method for extracting the physical parameters of a semiconductor device based on the measurements of its electrical response (e.g. transfer characteristics) combined with simulation. Such extraction is usually performed by an optimization algorithm seeking device-parameter values that minimize the difference between the measured response and its simulated equivalent. The proposed approach needs only an average of 13 objective-function evaluations, i.e. device simulations, to extract three parameters of a single device. If the parameters of a group of devices of the same type are to be extracted, the average number of simulations drops to four per device. This number is much smaller than in conventional optimization procedures. Thus, the proposed procedure can be used even in the absence of an accurate compact model, when time-consuming TCAD simulation must be used to determine the device’s response.

D. Tomaszewski, J. Malesińska, G. Głuszko and K. Kucharski, "Current vs Substrate Bias Characteristics of MOSFETs as a Tool for Parameter Extraction," 2019 MIXDES - 26th International Conference "Mixed Design of Integrated Circuits and Systems", Rzeszów, Poland, 2019, pp. 87-91.

doi: 10.23919/MIXDES.2019.8787068

Abstract: An application of the drain current vs substrate bias characteristics of MOSFETs for the device parameter extraction is presented. Modeling of the substrate bias effect on the MOSFET drain current is briefly discussed. A method of the MOSFET characterization is formulated. It requires a measurement of two I(V) characteristics, including the ID(VBS) smooth curve measured in a "sweep" mode. The method allows to extract the threshold voltage parameters and to estimate the in-depth doping profile in the substrate. The proposed approach is demonstrated using I(V) data of the MOSFETs manufactured in ITE in a bulk CMOS process.

EDS DL MQ Gdynia Maritime University, June 20, 2018, Gdynia, Poland

EDS Distinguished Lecturer Mini-Colloquium
SiC: technology, devices, modeling
Gdynia Maritime University, June 20, 2018, Gdynia, Poland
admission: free of charge

organized by:	ED Poland Chapter Gdynia Maritime University Instytut Technologii Elektronowej (ITE, Warsaw)
technical support:	Lodz University of Technology, Department of Microelectronics and Computer Science
venue:	Gdynia Maritime University ul. Morska 83, 81-225 Gdynia, Poland

9:00-9:05

Introduction

Dr. Daniel Tomaszewski, IEEE EDS Member, ITE, Warsaw

9:05-9:50 SiC technology offerings; challenges and opportunities

Lecturer: Dr. Muhammad Nawaz, IEEE Senior Member, IEEE EDS Distinguished Lecturer,
ABB Corporate Research, Sweden

Abstract: A wide bandgap SiC technology has now entered in transitional phase on various power electronics front; thanks to its superior physical properties such as wide bandgap, larger breakdown field strength, higher carrier saturation velocity, and larger thermal conductivity than that of Si counterpart. Low voltage SiC MOSFET discrete devices and power modules within voltage range of 1.2-1.7 kV are commercially available. On the other side, medium voltage MOSFET devices of 3.3-6.5 kV and high voltage MOSFET devices of 10-15 kV are also visible in the scientific literature with excellent static and dynamic performance, illustrating the potential benefit for high power applications in energy transmission and distribution networks. This talk will focus on the requirement and issues using SiC MOSFETs facing high power applications while addressing simultaneously the potential benefits for high power converters. Reliability concerns from the end user’s perspective will be addressed as well.

10:00-10:45 On the way to the Energy and Variability Efficient (E.V.E.) Era

Lecturer: Prof. Simon Deleonibus, IEEE Fellow, IEEE EDS Distinguished Lecturer, Fellow Electrochemical Society, CEA Research Director, France

Abstract: Major power consumption reduction will drive future design of technologies and architectures that will request less greedy devices and interconnect systems. The electronic market will be able to face an exponential growth thanks to the availability and feasibility of autonomous and mobile systems necessary to societal needs. The increasing complexity of high volume fabricated systems will be possible if we aim at zero intrinsic variability, and generalize 3-dimensional integration of hybrid, heterogeneous technologies at the device, functional and system levels. Weighing on the world energy saving balance will be possible and realistic by maximizing the energy efficiency of co integrated Low Power and High Performance Logic and Memory devices.The future of Nanoelectronics will face the major concerns of being Energy and Variability Efficient (E.V.E.).

10:55-11:15 Coffee break

11:15-12:00 SiC power device fabrication and path to commercialization

Lecturer: Prof. Victor Veliadis, IEEE Fellow, IEEE EDS Distinguished Lecturer, Deputy Executive Director and CTO, PowerAmerica Professor of Electrical and Computer Engineering, North Carolina State University

Abstract: The presentation will discuss major SiC power device application areas and touch on foundry models, cost reduction strategies, and path to commercialization. The advantages of SiC over other power electronic materials will be outlined, and SiC devices currently developed for power electronic applications will be introduced. Emphasis will be placed on SiC MOSFETs, which are currently being inserted in the majority of SiC based power electronic systems. Aspects of device fabrication will be given, with stress on processes that do not carry over from the mature Si manufacturing world and are thus specific to SiC. Finally, the presentation will highlight common SiC Edge Termination techniques, which allow devices to reach their full high-voltage potential.

12:10-12:55 The importance of the diffusion currents in the photoelectric investigations of the MIS system

Lecturer: Prof. Henryk M. Przewłocki, IEEE Senior Member, IEEE EDS Distinguished Lecturer, Instytut Technologii Elektronowej (ITE Warsaw), Poland

Abstract: The fundamental property of any nanoelectronic material or system is its energy band diagram, which allows to predict its physical properties, potential applications and/or limitations. The most effective methods of band diagram determination are the photoelectric methods, which deserve therefore detailed theoretical analysis, as well as precisely controlled experimental procedures. It is shown in this paper that the commonly accepted and currently applied theory (further called classical theory) of internal photoemission in the metal-insulator-semiconductor (MIS) system, which very well represents its experimental characteristics taken at high enough electric fields E, in the insulator, fails at low electric fields (usually for E < (104-105) V/cm), i.e. in the vicinity of the point where the photocurrent changes sign (I=0). This failure of the classical theory will be demonstrated by comparing the characteristics calculated using the classical theory with the experimental characteristics taken in the range of low electric fields in the insulator. It was already shown some time ago, by the present author that this discrepancy results from the neglect of the diffusion currents, which become important at low electric fields in the insulator. In this paper the origin, the magnitude and the role of diffusion current in determination of the MIS system photoelectric characteristics at low electric fields in the insulator will be quantitatively analyzed. The theory of the photocurrent vs. gate voltage characteristics, at different wavelengths of light illuminating the structure under test, with diffusion currents taken into account will be presented. It will be shown that characteristics calculated using this theory remain in good agreement with the relevant experimental characteristics. The ability to accurately predict these characteristics in the range of low electric fields opens the possibilities of developing new measurement methods of the MIS system crucial parameters. Examples of such methods will be demonstrated.

13:05-14:05 Lunch Break

14:05-14:50 Verilog-A compact modelling of SiC devices with Qucs-S, QucsStudio and MAPP/Octave FOSS tools

Lecturer: Prof. Mike Brinson, Fellow of the IET, CEng., Member of the Institute of Physics, CPhys. Centre for Communications Technology, London Metropolitan University, UK

Abstract: The purpose of this presentation is provide an overview of the fundamentals of the Verilog-A hardware description language and its use in compact modelling of established and emerging semiconductor technology devices. With the adoption of Verilog-A as the standardised model interchange language by CMC, a knowledge of this subject is of increasing importance to the modelling community. Similarly, access to freely available Verilog-A modelling tools and circuit simulators is essential if Verilog-A modelling techniques are to be widely adopted. For this reason, in an attempt to encouraging all who attend to experiment with Verilog-A. the presentation is based on the Qucs-S, QucsStudio and the MAPP/Octave FOSS software. Throughout the talk a series of modelling case studies outline the stages in the development of Verilog-A models for established and SiC semiconductor devices. In the later stages of the presentation participants are also introduced to using the Berkeley MAPP tools with Qucs-S/Xyce.

15:00-15:45 FOSS TCAD/EDA Tools for Advanced Compact Modeling

Lecturer: Dr. Wladek Grabinski, IEEE Senior Member, IEEE EDS Distinguished Lecturer, MOS-AK (EU), Switzerland

Abstract: Compact/SPICE models of circuit elements (passive, active, MEMS, RF) are essential to enable advanced IC design using nanoscaled semiconductor technologies. Compact/SPICE models are also a communication means between the semiconductor foundries and the IC design teams to share and exchange all engineering and design information. To explore all related interactions, we are discussing selected FOSS CAD tools along complete technology/design tool chain from nanascaled technology processes; thru the MOSFET, FDSOI, FinFET and TFET compact modeling; to advanced IC transistor level design support. New technology and device development will be illustrated by application examples of the FOSS TCAD tools: Cogenda TCAD and DEVSIM. Compact modeling will be highlighted by review topics related to its parameter extraction and standardization of the experimental and measurement data exchange formats. Finally, we will present two FOSS CAD simulation and design tools: ngspice and Qucs. Application and use of these tools for advanced IC design (e.g. analog/RF IC applications) directly depends the quality of the compact models implementations in these tools as well as reliability of extracted models and generated libraries/PDKs. Discussing new model implementation into the FOSS CAD tools (Gnucap, Xyce, ngspice and Qucs as well as others) we will also address an open question of the compact/SPICE model Verilog-A standardization. We hope that this presentation will be useful to all the researchers and engineers actively involved in the developing compact/SPICE models as well as designing the integrated circuits in particular at the transistor level and then trigger further discussion on the compact/SPICE model Verilog-A standardization and development supporting FOSS CAD tools.

15:55 End of MQ

[paper] Compact modeling of SiC Schottky barrier diode and its extension to junction barrier Schottky diode

Dondee Navarro1, Fernando Herrera1, Hiroshi Zenitani2, Mitiko Miura-Mattausch1, Naoto Yorino2, Hans Jürgen Mattausch1,2, Mamoru Takusagawa3, Jun Kobayashi3 and Masafumi Hara3

Published 19 February 2018 • © 2018 The Japan Society of Applied Physics

Japanese Journal of Applied Physics, Volume 57, Number 4S

1 HiSIM Research Center, Hiroshima University, Hiroshima 739-8530, Japan

2 Graduate School of Engineering, Hiroshima University, Hiroshima 739-8530, Japan

3 Toyota Motor Corporation, Toyota, Aichi 470-0309, Japan

Abstract: A compact model applicable for both Schottky barrier diode (SBD) and junction barrier Schottky diode (JBS) structures is developed. The SBD model considers the current due to thermionic emission in the metal/semiconductor junction together with the resistance of the lightly doped drift layer. Extension of the SBD model to JBS is accomplished by modeling the distributed resistance induced by the p+ implant developed for minimizing the leakage current at reverse bias. Only the geometrical features of the p+ implant are necessary to model the distributed resistance. Reproduction of 4H-SiC SBD and JBS current–voltage characteristics with the developed compact model are validated against two-dimensional (2D) device-simulation results as well as measurements at different temperatures [read more: https://doi.org/10.7567/JJAP.57.04FR03]

Fig.: Electron current density in a JBS cross-section. JBS has a peak density at the n− region adjacent to the p+ implant.

[paper] Compact electro-thermal modeling of a SiC MOSFET power module under short-circuit conditions

Proceedings of 43rd Annual Conference of the IEEE Industrial Electronics Society

IECON 2017

Lorenzo Ceccarelli, Paula Diaz Reigosa, Amir Sajjad Bahman, Francesco Iannuzzo,

Frede Blaabjerg

Center of Reliable Power Electronics, Department of Energy Technology Aalborg University,

Pontoppidanstræde 101

9220 Aalborg, Denmark 

ABSTRACT: A novel physics-based, electro-thermal model which is capable of estimating accurately the short-circuit behavior and thermal instabilities of silicon carbide MOSFET multi-chip power modules is proposed in this paper. The model has been implemented in PSpice and describes the internal structure of the module, including stray elements in the multi-chip layout, self-heating effect, drain leakage current and threshold voltage mismatch. A lumped-parameter thermal network is extracted in order to estimate the internal temperature of the chips. The case study is a half-bridge power module from CREE with 1.2 kV breakdown voltage and about 300 A rated current. The short-circuit behavior of the module is investigated experimentally through a non-destructive test setup and the model is validated. The estimation of overcurrent and temperature distribution among the chips can provide useful information for the reliability assessment and fault-mode analysis of a new-generation SiC high-power modules [read more...]

Fig.: SiC MOSFET model structure.