[paper] FOSS support for CM with Verilog-A

Bűrmen, Árpád, Tadej Tuma, Iztok Fajfar, Janez Puhan, Žiga Rojec, Matevž Kunaver

and Sašo Tomažič

Free software support for compact modelling with Verilog-A

Informacije MIDEM 54, no. 4 (October 9, 2024)

<https://ojs.midem-drustvo.si/index.php/InfMIDEM/article/view/1999>

Abstract: Verilog-A is the analog subset of Verilog-AMS - a hardware description language for analog and mixed-signal systems. Verilog-A is commonly used for the distribution of compact models of semiconductor devices. For such models to be usable a Verilog-A compiler is required. The compiler converts the model equations into a form that can be used by the simulator. Such compilers have been supplied with commercial simulators for many years now. Free software alternatives are much more scarce and limited in the features they offer. The paper gives an overview of Verilog-A, Free software Verilog-A compilers, and Free software/Open source simulators that can simulate compact models defined in Verilog-A. Advantages and disadvantages of individual compilers and simulators are highlighted.

Tab: Comparison of Free software simulators

Asterisk denotes a feature under development as of Sep. 2024

Acknowledgements: This research was funded in part by the Slovenian Research Agency within the research program ICT4QoL—Information and Communications Technologies for Quality of Life, grant number P2-0246.

[paper] Compact Modeling of Hysteresis in OTFTs

Compact modeling of hysteresis in organic thin-film transistors

A. Romero^a, J.A. Jiménez-Tejada^a, R. Picos^b, D. Lara^a, J.B. Roldán^a, M.J. Deen^c

Organic Electronics 129 (2024) 107048

DOI : 10.1016/j.orgel.2024.107048

a Departamento de Electrónica y Tecnología de Computadores, CITIC-UGR, Uni Granada, Spain
b Department of Industrial Engineering and Construction, Universitat de les Illes Balears, Spain
c Department of Electrical and Computer Engineering, McMaster University, Canada

Abstract: In this work, we propose a model that describes the temporal evolution of the threshold voltage and trapped charge density in Thin-Film Transistors (TFTs) under dynamic conditions, paving the way for the characterization and modeling of memory transistors. The model is expressed as a first-order differential equation for the trapped charge density, which is controlled by a time constant and an independent term proportional to the drain current. The time-dependent threshold voltage is introduced in a previously developed compact model for TFTs with special consideration to the contact effects. The combination of both models and the use of an evolutionary parameter extraction procedure allow for reproducing the experimental dynamic behavior of TFTs. The results of the model and the evolutionary procedure have been validated with published experimental data of pentacene-based transistors. The procedure is able to simultaneously reproduce three kinds of experiments with different initialization routines and constraints in each of them: output and transfer characteristics with hysteresis and current transients characteristics

FIG: a.) Modeling the contact regions and intrinsic channel of an OTFT structure (a bottom contact configuration); b.)  Comparison of experimental transfer characteristics

Acknowledgements : The authors acknowledge support from the project PID2022 139586NB-44 funded by MCIN/AEI/10.13039/501100011033 and FEDER, EU. Funding for open access charge: Universidad de Granada / CBUA.

Appendix: Supplementary material related to this article can be found online.

[paper] Neural Compact Modeling Framework

Eom, Seungjoon, Hyeok Yun, Hyundong Jang, Kyeongrae Cho, Seunghwan Lee, Jinsu Jeong, and Rock‐Hyun Baek

Neural Compact Modeling Framework for Flexible Model Parameter Selection with High Accuracy and Fast SPICE Simulation

Advanced Intelligent Systems (2023): 2300435

DOI: 10.1002/aisy.202300435

Department of Electrical Engineering, Pohang University of Science and Technology, Pohang 37673 (KR)

Abstract: Neural compact models are proposed to simplify device-modeling processes without requiring domain expertise. However, the existing models have certain limitations. Specifically, some models are not parameterized, while others compromise accuracy and speed, which limits their usefulness in multi-device applications and reduces the quality of circuit simulations. To address these drawbacks, a neural compact modeling framework with a flexible selection of technology-based model parameters using a two-stage neural network (NN) architecture is proposed. The proposed neural compact model comprises two NN components: one utilizes model parameters to program the other, which can then describe the current–voltage (IV) characteristics of the device. Unlike previous neural compact models, this two-stage network structure enables high accuracy and fast simulation program with integrated circuit emphasis (SPICE) simulation without any trade-off. The IV characteristics of 1000 amorphous indium–gallium–zinc-oxide thin-film transistor devices with different properties obtained through fully calibrated technology computer-aided design simulations are utilized to train and test the model and a highly precise neural compact model with an average IDS error of 0.27% and R2 DC characteristic values above 0.995 is acquired. Moreover, the proposed framework outperforms the previous neural compact modeling methods in terms of SPICE simulation speed, training speed, and accuracy.

Fig: a) The structure of a-IGZO TFT structure simulated with TCAD

b) Calibrated a-IGZO sub-gap DOS

Acknowledgements: This work was supported in part by the LG Display Company, in part by the Brain Korea 21 Fostering Outstanding Universities for Research (BK21 FOUR) program, in part by Institute of Information and Communications Technology Planning and Evaluation (IITP) grant funded by the Korea government (MSIT) (grant no. 2019-0-01906, Artificial Intelligence Graduate School Program [POSTECH]), in part by the Ministry of Trade, Industry and Energy (MOTIE) under grant no. 20020265, in part by Korea Semiconductor Research Consortium (KSRC) support program for the development of the future semiconductor device, and in part by the Technology Innovation Program (grant no. RS2023-00231985) funded by the Ministry of Trade, Industry and Energy (MOTIE, Korea) (grant no. 1415187390).

[paper] Surface-Potential-Based Compact Modeling

M. Miura-Mattausch, T. Iizuka, H. Kikuchihara, H. J. Mattausch, and S. Saha

Evolution of Surface-Potential-Based Compact Modeling

IEEE EDS NEWSLETTER

OCTOBER 2023 VOL. 30, NO. 4 ISSN: 1074 1879

Abstract: Conventionally, a compact model of an electronic device is developed for utilization in circuit simulation. This means that the main task of the compact model is to accurately describe the characteristics of a device as a function of the applied voltages by simple equations in order to predict the performance of circuits using this device with sufficient precision. This overview article focuses on the compact modeling of the metal-oxide-semiconductor field-effect transistor (MOSFET)-device structure, which has the largest variety of applications. However, the modeling methodology is valid for any type of transistor or electronic device. The development of the compact modeling approach, based on the potential distribution induced within a transistor, is reviewed. The purpose of a compact model is to describe the transistor characteristics in a simple but accurate way, to enable correct circuit-performance prediction. Therefore, the basic physics of observed phenomena must be modeled by simplified and yet physically correct equations. To meet such requirements, potential-based modeling is a natural fit. A compact model and TCAD are both based on the same transistor equations. The difference is that TCAD considers the distribution of all physical quantities within a device, and a compact model integrates these distributions to calculate transistor characteristics at its nodes. The shortcomings of resulting simplifications, introduced for analytical integration, can be examined using TCAD, to identify observed phenomena still missing in the compact modeling. In this way, compact modeling is performed by learning from measurements macroscopically and from TCAD microscopically.

Fig: Schematic of a HV LDMOS FET (top) 

and its potential distribution (bottom)

[book chapters] Equation-Based Compact Modeling

 

Debnath, P., Sarkar, B., & Chanda, M. (Eds.). (2023).

Differential Equation Based Solutions 

for Emerging Real-Time Problems

(1st ed.). CRC Press 

DOI 10.1201/9781003227847

Chapter: Differential Equation-Based Compact 2-D Modeling of Asymmetric Gate Oxide Heterojunction Tunnel FET; By: Sudipta Ghosh, Arghyadeep Sarkar

Abstract: Tunnel Field Effect Transistor (TFET) has emerged as an effective alternative device to replace MOSFET for a few decades. The major drawbacks of MOSFET devices are the short-channel effects, due to which the leakage current increases with a decrease in device dimension. So, scaling down TFET is more efficacious than that of MOSFETs. Sub-threshold swing (SS) is another advantageous characteristic of TFET devices for high-speed digital applications. In TFETs the SS could be well below 60 mV/decade, which is the thermal limit for MOSFET devices and therefore makes it more suitable than MOSFET for faster switching applications. It is observed from the literature studies that the performances of the TFET devices have been explored thoroughly by using 2-D TCAD simulation but an analytical model is always essential to understand the physical behavior of the device and the physics behind this; which facilitates further, the analysis of the device performances at circuit level as and when implemented.

Chapter: Differential Equation-Based Analytical Modeling of the Characteristics Parameters of the Junctionless MOSFET-Based Label-Free Biosensors; by: Manash Chanda, Papiya Debnath, Avtar Singh

Abstract: Recently Field Effect transistor (FET)-based biosensing applications have gained significant attention due to the demand for quick and accurate diagnosis of different enzymes, proteins, DNA, viruses, etc; cost-effective fabrication process; portability and better sensitivity and selectivity compared to the existing biosensors. FET is basically a three-terminal device with source, drain, and gate terminals. Basically, the gate terminal controls the current flow between the source and drain terminals. In FETs, first, a nanogap is created in the oxide layer or in the gate by etching adequate materials. When the biomolecules are trapped inside the nanocavity then the surface potentials change and also the threshold voltage varies. As a result, the output current also changes. Finally, by measuring the changes in the threshold voltage or the device current, one can easily detect the biomolecules easily.

[paper] Schottky Barrier FET at Deep Cryogenic Temperatures

Christian Roemer^1,2, Nadine Dersch¹, Ghader Darbandy¹, Mike Schwarz¹,

Yi Han³, Qing-Tai Zhao³, Benjamın Iniguez² and Alexander Kloes¹

Compact Modeling of Schottky Barrier Field-Effect Transistors 

at Deep Cryogenic Temperatures

EUROSOI-ULIS 2023

in Tarragona (Catalonia, Spain) on May 10-12 2023

1 NanoP, TH Mittelhessen - University of Applied Sciences, Giessen, Germany
2 DEEEA, Universitat Rovira i Virgili, Tarragona, Spain
3 Peter-Grunberg-Institute (PGI 9), Forschungszentrum Julich, Germany

Abstract: In this paper, a physics-based DC compact model for Schottky barrier field-effect transistors at deep cryogenic temperatures is presented. The model uses simplified tunneling equations at temperatures of ϑ ≈ 0 K in order to calculate the field emission injection current at the device’s Schottky barriers. The compact model is also compared to and verified by measurements of ultra-thin body and buried oxide SOI Schottky barrier field-effect transistors and is able to capture the signature of resonant tunneling effects in the transfer characteristics.

FIG: Band diagram at the source side Schottky junction (left-hand side). The solid blue line is the conduction band of the channel and the blue dashed line shows the metal’s Fermi energy level. The right-hand side subplot shows the tunneling probability, with the exponential part (red line) and the total probability, including the oscillations (green line).

Compact Modeling of 2D Field-Effect Biosensors

Francisco Pasadas¹, Tarek El Grour², Enrique G. Marin¹, Alberto Medina-Rull¹, Alejandro Toral-Lopez¹, Juan Cuesta-Lopez¹, Francisco G. Ruiz¹, Lassaad El Mir² and Andrés Godoy¹

Compact Modeling of Two-Dimensional Field-Effect Biosensors.

Sensors 2023, 23, 1840.

DOI: 10.3390/s23041840

1 Pervasive Electronics Advanced Research Laboratory (PEARL), Departamento de Electrónica y Tecnología de Computadores, Universidad de Granada,18071 Granada, Spain
2 Laboratory of Physics of Materials and Nanomaterials Applied at Environment (LaPhyMNE) LR05ES14, Faculty of Sciences of Gabes, Gabes University, Erriadh City, Zrig, 6072 Gabes, Tunisia

Abstract: A compact model able to predict the electrical read-out of field-effect biosensors based on two-dimensional (2D) semiconductors is introduced. It comprises the analytical description of the electrostatics including the charge density in the 2D semiconductor, the site-binding modeling of the barrier oxide surface charge, and the Stern layer plus an ion-permeable membrane, all coupled with the carrier transport inside the biosensor and solved by making use of the Donnan potential inside the ion-permeable membrane formed by charged macromolecules. This electrostatics and transport description account for the main surface-related physical and chemical processes that impact the biosensor electrical performance, including the transport along the low-dimensional channel in the diffusive regime, electrolyte screening, and the impact of biological charges. The model is implemented in Verilog-A and can be employed on standard circuit design tools. The theoretical predictions obtained with the model are validated against measurements of a MoS2 field-effect biosensor for streptavidin detection, showing excellent agreement in all operation regimes and leading the way for the circuit-level simulation of biosensors based on 2D semiconductors

FIG: Schematic of a two-dimensional field-effect biosensor. A sketch of the position-dependent potential is also shown, highlighting the surface charge density at the 2D channel (σ2D), at the oxide-electrolyte interface (σ0), and at the membrane-diffuse regions of the electrolyte (σmd). The latter comprises a charge-free layer (Stern layer) and an ion-permeable membrane due to the presence of charged macromolecules, with a diffusion layer located between the barrier oxide surface and the bulk electrolyte. The potential difference from the electrolyte bulk to the barrier oxide surface, ψ0, encompasses two contributions originating from a potential drop (ψ0 − ψm) across the Stern layer extending between the outer Helmholtz plane (OHP) and the barrier oxide surface, and a potential drop across the ion-permeable membrane layer formed by charged macromolecules and the diffuse layer (ψm)

Funding: This work is funded by the Spanish Government MCIN/AEI/10.13039/501100011033 through the projects PID2020-116518GB-I00 and TED2021-129769B-I00 (MCIU/AEI/FEDER-UE); and by FEDER/Junta de Andalucía-Consejería de Transformacion Económica, Industria, Conocimiento y Universidades through the projects P20_00633 and A-TIC-646-UGR20. F. Pasadas acknowledges funding from PAIDI 2020 and the European Social Fund Operational Programme 2014–2020 no. 20804. A. Medina-Rull acknowledges the support of the MCIN/AEI/PTA grant, with reference PTA2020- 018250-I. J. Cuesta-Lopez acknowledges the FPU program FPU019/05132, and A. Toral-Lopez the support of Plan Propio of Universidad de Granada.

Data Availability Statement: The Verilog-A model for 2D EIS BioFETs is available from the corresponding author (fpasadas@ugr.es) upon reasonable request.

[analog-wg] Video of March 21 AWG Meeting

The Analog Workgroup (AWG) was formed by the CHIPS Alliance TSC to explore collaborations in open source Analog/Mixed-Signal design and verification. It focuses on sharing best practices, ideas, tooling (analog automation), and other challenge areas in the design space. The workgroup is composed of both industry and university members.

The AWG Video Meeting on March 21, 2023 included two presentations:

• Ken Kundert "Why Fund OpenVAF"
• Pascal Kuthe "OpenVAF: An innovative open-source Verilog-A Compiler"

Please note the following line of topics for the Analog Workgroup

• 4th April: Update from Tim Edwards: Magic and PEX extraction
• 18th April: Update from Sadayuki Yoshitomi: Ecosystem of compact model development 
• 2nd May (tentative): Update from C. Enz,EPFL:  test structures measurements

Neural networks and machine learning approach for compact modeling

[NN] Wang, Qiuwei, Mao Ye, Yao Li, Xiaoxiao Zheng, Jiaji He, Jun Du, and Yiqiang Zhao. "MOSFET modeling of 0.18 μm CMOS technology at 4.2 K using BP neural network." Microelectronics Journal (2023): 105678. DOI: 10.1016/j.sse.2022.108580

Highlights

• The cryogenic characterization of SMIC CMOS technology at 4.2K is presented.
• An optimization model VCCS is proposed to calibrate the cryogenic characteristics.
• BP neural network is, for the first time, used in MOSFET modeling.
• The cryo-model can be applied to SPICE simulator and assist in cryo-CMOS circuit design and simulation.

Fig: The structure of graph-based compact model of FinFET. The model receives the input features such as voltages, geometries, etc. as a vector and predicts the drain current (Ids) and its derivatives as output features.

[ML] Gaidhane, Amol D., Ziyao Yang, and Yu Cao. "Graph-based Compact Modeling (GCM) of CMOS transistors for efficient parameter extraction: A machine learning approach." Solid-State Electronics (2023): 108580.

Highlights

• Developed a Graph-based compact model for FinFET.
• Model implemented in Verilog-A for SPICE simulation.
• Requires less number of model parameters and is computationally efficient than BSIM

[paper] Universal Charge Model for Multigate MOS Structures

Kwang-Woon Lee and Sung-Min Hong

Derivation of a Universal Charge Model for Multigate MOS Structures

with Arbitrary Cross Sections

IEEE TED (2022, Early Access)

DOI:  10.1109/TED.2022.316486

   

* Gwangju Institute of Science and Technology (KR)

Abstract: A universal equation for the charge-voltage characteristics in the multigate metal oxide semiconductor (MOS) structure with an arbitrary cross section is presented. A generalized coordinate is proposed and the Poisson equation is integrated with a weighting factor related with the generalized coordinate and the electric field. A compact charge model is derived and analytic and numerical examples for various MOS structures are shown.

Fig: Thin slab in the semiconductor channel region of the multigate MOS structure. The A∗ surfaces are perpendicular to the z-direction, which is the transport direction and its generalized coordinate, ψ, for rectangular nanosheet MOS structures at 0.0 V (top) and 0.7 V (bottom).

Aknowlegements: This workwas supported by the National Research Foundation of Korea (NRF) Grant funded by the Korean Government under Grant NRF- 2019R1A2C1086656 and Grant NRF-2020M3H4A3081800.

[paper] Compact Modelling of Si Nanowire/Nanosheet MOSFETs

A. Cerdeira¹, M. Estrada¹, and M. A. Pavanello²

On the compact modelling of Si nanowire and Si nanosheet MOSFETs

Semiconductor Science and Technology, vol. 37, no. 2, p. 025014, Jan. 2022.

DOI: 10.1088/1361-6641/ac45c0

   

1 Centro de lnvestigacién y de Estudios Avanzados del IPN, Mexico City, Mexico
2 Centro Universitario PEI, Sao Bernardo do Cainpo, Sao Paulo, Brazil

Abstract: In this paper, three-dimensional technology computer aided design simulations are used to show that the electron concentration, current density, and electric field distribution from the interface at the lateral channels and from the top channel to the centre of the silicon wire, in nanowire and nanosheet structures, are practically same. This characteristic makes it possible to consider that the total channel width for these structures is equal to the perimeter of the transistor sheet, allowing to extend of the application of the symmetric doped double-gate model (SDDGM) model to nanowires and nanosheets metal-oxide-semiconductor field effect transistors, with no need to include new parameters. The model SDDGM is validated for this application using several measured and simulated structures of nanowires and nanosheets transistors, with different aspect ratios of fin width and fin height, showing very good agreement between measured or simulated characteristics and modelled. SDDGM is encoded in Verilog-A language and implemented in SPICE circuit simulator.

Fig: a.) Normalized measured and modelled transfer characteristics of stacked transistor in the linear region at VDS=0.025V and in saturation region at VDS=0.75V; b.) Output characteristic and conductance at VGS=1V.

Acknowledgments: The authors are grateful to CEA—Leti for providing the exper- imental samples used in this paper. This work was supported by the CONACYT project 236887, CNPq, Sao Paulo Research Foundation (FAPESP) Grants 2015/ 1049 1-7 and 2019/ 15500- 5, and the IBM/STMicroelectronics/Leti Joint Development Alliance.

 

8th EuroSOI-ULIS 2022 at University of Udine (Italy)

Organized by: University of Udine (Italy) Conference chair: Pierpaolo Palestri Local organizing Committee: Francesco Driussi David Esseni Daniel Lizzit Conference Secretariat: Centro Congressi Internazionali  Steering Committee: Francis BALESTRA (IMEP Minatec, France) Maryline BAWEDIN (IMEP-LAHC, France) Cor CLAEYS (KU-Leuven, Belgium) Bogdan CRETU (ENSICAEN, France) Sorin CRISTOLOVEANU (IMEP-LAHC, France) Francisco GAMIZ (UnivGranada, Spain) Elena GNANI (Univ. of Bologna, Italy) Benjamin INIGUEZ  (URV, Spain) Joris LACORD (CEA-Leti, France) Enrico SANGIORGI (Univ.Bologna, Italy) Luca SELMI (Univ. of Modena, Italy) Viktor SVERDLOV (TU Wien, Austria) Andrei VLADIMIRESCU (ISEP, France) Sponsors:

8th Joint International EuroSOI Workshop and International Conference on Ultimate Integration on Silicon (EuroSOI-ULIS) 2022 May 18-20, 2022 – Udine, Italy https://eurosoiulis2022.com The Conference aims at gathering together scientists and engineers working in academia, research centers and industry in the field of SOI technology and nanoscale devices in More-Moore and More-Than-Moore scenarios. High quality contributions in the following areas are solicited: Advanced SOI materials and structures, innovative SOI-like devices. Alternative transistor architectures (FDSOI, Nanowire, FinFET, MuGFET, vertical MOSFET, FeFET and TFET, MEMS/NEMS, Beyond-CMOS). New channel materials for CMOS (strained Si/Ge, III-V, carbon nanotubes; graphene and other 2D materials). Properties of ultra-thin semiconductor films and buried oxides, defects, interface quality; thin gate dielectrics: high-κ and ferroelectric materials for switches and memory. New functionalities and innovative devices in the More than Moore domain: nanoelectronic sensors, biosensor devices, energy harvesting devices, RF devices, imagers, integrated photonics (on SOI), etc. Transport phenomena, compact modeling, device simulation, front- and back-end process simulation. CMOS scaling perspectives; device/circuit level performance evaluation; switches and memory scaling; three-dimensional integration of devices and circuits, heterogeneous integration. Advanced test structures and characterization techniques, parameter extraction, reliability and variability assessment techniques for new materials and novel devices. Original 2-page abstracts with illustrations will be reviewed by the Scientific Committee. The accepted contributions will be published as 4-page letters in a special issue of the Elsevier journal Solid-State Electronics. Extended versions of outstanding papers will be published in a further special issue of Solid-State Electronics. A best poster award will be attributed by ELSEVIER.  The “Androula Nassiopoulou Best Paper Award" will be attributed by the SINANO institute. Important dates: abstract submission deadline: March 1, 2022 notification of acceptance: March 15, 2022

[paper] Parameter Extraction Approaches for Memristor Models

Dmitry Alexeevich Zhevnenko^1,2, Fedor Pavlovich Meshchaninov^1,2, Vladislav Sergeevich Kozhevnikov^1,2, Evgeniy Sergeevich Shamin^1,2, Oleg Alexandrovich Telminov^1,2, and Evgeniy Sergeevich Gornev^1,2

Research and Development of Parameter Extraction Approaches for Memristor Models

Micromachines 2021, 12, 1220. 

DOI: 10.3390/mi12101220

   
1 Moscow Institute of Physics and Technology, Moscow, Russia;
2 JSС MERI, Zelenograd, Russia

Abstract: Memristors are among the most promising devices for building neural processors and non-volatile memory. One circuit design stage involves modeling, which includes the option of memristor models. The most common approach is the use of compact models, the accuracy of which is often determined by the accuracy of their parameter extraction from experiment results. In this paper, a review of existing extraction methods was performed and new parameter extraction algorithms for an adaptive compact model were proposed. The effectiveness of the developed methods was confirmed for the volt-ampere characteristic of a memristor with a vertical structure: TiN/HfxAl1-xOy/HfO2/TiN.

Fig: Model VACs with different numbers of inhomogeneities: 

(a) four inhomogeneities; (b) no inhomogeneities.

Acknowledgments: This research was funded by the Ministry of Science and Higher Education of the Russian  Federation, grant number 075-15-2020-791. Authors thank the Institute of Microelectronics Technology and High-Purity Materials RAS for access to experimental data on the study of graphene oxide memristor switching cycles.

[paper] Compact Schottky-barrier CNTFET Modeling

Manojkumar Annamalai and Michael Schroter

Compact formulation for the bias dependent quasi-static mobile charge in Schottky-barrier CNTFETs IEEE Transactions on Nanotechnology (2021)

DOI: 10.1109/TNANO.2021.3116694

CEDIC, Technische Universität Dresden (D)

Abstract: Carbon nanotube (CNT) field-effect transistors (FETs) are promising candidates for future high-frequency (HF) system-on-chip applications. Understanding and modeling mobile charge storage on CNTs is therefore essential for device optimization and circuit design. A physics-based compact analytical formulation is presented that enables an accurate approximation of the mobile charge in Schottky-barrier CNTFETs over the practically relevant bias range for HF circuit design. The formulation is C∞ continuous and yields accurate results also for the capacitances. The new formulation has been verified for both ballistic and scattering dominated carrier transport by employing device simulation, which was calibrated to experimental data from multi-tube CNTFETs.

Fig: Band diagram in a CNTFET along the axial direction (left red arrow) and, with applied gate bias, along the radial direction perpendicular to the gate (right blue arrow).

Acknowledgments: The authors would like to thank Dr. S. Mothes, formerly with CEDIC, for valuable discussions regarding the device simulator. This project was financially supported in part by the German National Science Foundation (DFG SCHR695/6-2).  

[paper] Compact Model for Thin-Film Heterojunction Anti-Ambipolar Transistors

Hocheon Yoo and Chang-Hyun Kim, Senior Member, IEEE 

Unified Compact Model for Thin-Film Heterojunction Anti-Ambipolar Transistors

IEEE Electron Device Letters (2021)

DOI 10.1109/LED.2021.3102219

* Department of Electronic Engineering, Gachon University, Seongnam 13120, South Korea

Abstract: This letter proposes an advanced compact model for anti-ambipolar transistors based on a lateral thin-film material heterojunction. The modeling idea focuses on an analytical description of component currents and bridging methods necessary for controllable transition between operation regimes. The model is validated by experimental data, and predictive simulations are carried out to demonstrate its applicabilities.

Fig: (a) Cross-sectional device structure of an AAT and its energy diagram at a negative VD (G: gate, S: source, and D: drain). (b) Conceptual illustration of the geometrical origin of the anti-ambipolar switching behavior.

Acknowledgements: This work was supported by the National Research Foundation of Korea (NRF) grants funded by the Korean government (MSIT) (NRF-2019 R1C1C1003356, NRF2020 R1A2C1101647).

[papers] Aging and Device Reliability Compact Modeling

IEEE International Reliability Physics Symposium

(IRPS 2021)

[1] N. Chatterjee, J. Ortega, I. Meric, P. Xiao and I. Tsameret, "Machine Learning On Transistor Aging Data: Test Time Reduction and Modeling for Novel Devices," 2021 IEEE International Reliability Physics Symposium (IRPS), 2021, pp. 1-9, doi: 10.1109/IRPS46558.2021.9405188.

Abstract: Accurately modeling the I-V characteristics and current degradation for transistors is central to predicting circuit end-of-life behavior. In this work, we propose a machine learning model to accurately model current degradation at various stress conditions and extend that to make nominal use-bias predictions. The model can be extended to track and predict any parametric change. We show an excellent agreement of the model with experimental results. Furthermore, we use a deep neural network to model the I-V characteristics of aged transistors over a wide drain and gate playback bias range and show an excellent agreement with experimental results. We show that the model is reliably able to interpolate and extrapolate demonstrating that it learns the underlying functional form of the data.

URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9405188&isnumber=9405088

[2] P. B. Vyas et al., "Reliability-Conscious MOSFET Compact Modeling with Focus on the Defect-Screening Effect of Hot-Carrier Injection," 2021 IEEE International Reliability Physics Symposium (IRPS), 2021, pp. 1-4, doi: 10.1109/IRPS46558.2021.9405197.

Abstract: Accurate prediction of device aging plays a vital role in the circuit design of advanced-node CMOS technologies. In particular, hot-carrier induced aging is so complicated that its modeling is often significantly simplified, with focus limited to digital circuits. We present here a novel reliability-aware compact modeling method that can accurately capture the full post-stress I-V characteristics of the MOSFET, taking into account the impact of drain depletion region on induced defects.

URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9405197&isnumber=9405088

[3] Z. Wu et al., "Physics-based device aging modelling framework for accurate circuit reliability assessment," 2021 IEEE International Reliability Physics Symposium (IRPS), 2021, pp. 1-6, doi: 10.1109/IRPS46558.2021.9405106.

Abstract: An analytical device aging modelling framework, ranging from microscopic degradation physics up to the aged I-V characteristics, is demonstrated. We first expand our reliability oriented I-V compact model, now including temperature and body-bias effects; second, we propose an analytical solution for channel carrier profiling which-compared to our previous work-circumvents the need of TCAD aid; third, through Poisson's equation, we convert the extracted carrier density profile into channel lateral and oxide electric fields; fourth, we represent the device as an equivalent ballistic MOSFETs chain to enable channel “slicing” and propagate local degradation into the aged I-V characteristics, without requiring computationally-intensive self-consistent calculations. The local degradation in each channel “slice” is calculated with physics-based reliability models (2-state NMP, SVE/MVE). The demonstrated aging modelling framework is verified against TCAD and validated across a broad range of VG/VD/T stress conditions in a scaled finFET technology.

URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9405106&isnumber=9405088

[paper] An Accurate Analytical Modeling of Contact Resistances in MOSFETs

G. Bokitko, D. S. Malich, V. O. Turin*, and G. I. Zebrev

An Accurate Analytical Modeling of Contact Resistances in MOSFETs

Preprint · May 7, 2021 DOI: 10.13140/RG.2.2.29348.40321

National Research Nuclear University MEPHI, Moscow, Russia;
*Orel State University, Russia;

Abstract: As the MOSFET channel lengths decrease, the influence of parasitic source-drain resistance on the current characteristics becomes more and more important. The contact resistance is becoming a growing impediment to transistor power and performance scaling. This is a common challenge for SOI FETs, FinFETs and GAAFETs and any other type of transistor. Most of the modern compact models that are used in circuits simulations are too much technology oriented. We find it important to construct an analytical approach that could be served as a basis for compact modeling. This approach is based on analytical solution Kirchhoff’s equations and on the diffusion-drift field effect transistor model.

Fig: Equivalent MOSFET circuit with series resistance

[paper] Compact modeling of lab-on-chip

Alexi Bonament, Morgan Madec and Christophe Lallement

Compact modeling of reaction-diffusion-advection mechanisms 

for the virtual prototyping of lab-on-chip 

2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021, pp. 1-5,

doi: 10.1109/ISCAS51556.2021.9401396.

*Laboratory of Engineer Sciences, Computer Science and Imagine (ICube), UMR 7357 (Université de Strasbourg / Centre National de Recherche Scientifique), Strasbourg

Abstract: The topic of this paper is the development of compact models reaction-advection-diffusion phenomenon compatible with a SPICE simulation environment. From a mathematical perspective, biological systems that involve such phenomena are described by partial differential equations, which are not naturally handeled by SPICE. Our approach consists of discretizing these equations according to the finite-difference method and converting the resulting set of ordinary differential equations into an assembly of elementary equivalent electronic circuits written in Verilog-A. The main interest of this approach is the capability of coupling such models with third-party SPICE models of electronic circuits, sensors and transducers as well as biochemical models that can also be written in SPICE. The tool is validated both on simple problems for which analytical solutions are known and by comparison with a finite element simulator of reference

Fig: Core modules of the designed tool. Labels indicate the programming language.

Acknowledgment: This research was supported by the European Regional Development Fund (ERDF) and the Interreg V Upper Rhine Offensive Sciences Program (Project 3.14 – Water Pollution Sensor).

[paper] Deep-Learning Assisted Compact Modeling

Hei Kam

Deep-Learning Assisted Compact Modeling of Nanoscale Transistor

CS230 Deep Learning; Stanford University (2021)

Abstract - Transistors are the basic building blocks for all electronics. Accurate prediction of their current-voltage (IV) characteristics enables circuit simulations before the expensive silicon tape-out. In this work, we propose using deep neural network to improve the accuracy for the conventional, physics-based compact model for nanoscale transistors. Physics-driven requirements on the neural network are discussed. Using finite element simulation as the input dataset, together with a neural network with roughly 30 neurons, the final IV model can well-predict the IV to within 1%. This modelling methodologies can be extended for other transistor properties such as capacitance-voltage (CV) characteristics, and the trained model can readily be implemented by the hardware description language (HDL) such as Verilog-A for circuit simulation. The EKV model [1-2] is used as an example. Other transistor models such as BSIM-MG [3] or PSP [4] model can also be used.

Fig: Architecture for the 3-layer neural network together with the aforementioned transformation T. Hyperbolic tangent function tanh(x) is used as the activation function for the input and hidden layers due to its infinite differentiability.

References:

[1] Enz, Christian C., Eric A. Vittoz; "Charge-based MOS transistor modeling." John Wiely & Sons Inc 68 (2006).

[2] FOSS EKV 2.6 Compact Model <https://github.com/ekv26/model>

[3] Khandelwal, Sourabh, et al. "BSIM-IMG: A compact model for ultrathin-body SOI MOSFETs with back-gate control." IEEE Transactions on Electron Devices 59.8 (2012): 2019-2026.

[4] Gildenblat, G., et al. "PSP Model." Department of Electrical Engineering, The Pennsylvania State University and Philips Research, (Aug. 2005)

[Photos] MOS-AK LADEC Mexico April 18, 2021

Arbeitskreis Modellierung von Systemen und Parameterextraktion

Modeling of Systems and Parameter Extraction Working Group

MOS-AK LAEDC Workshop

(virtual/online) April 18, 2021

Together with local Host and LAEDC Organizers as well as all the Extended MOS-AK TPC Committee, we have organized the 3rd subsequent MOS-AK/LAEDC workshop which was the Virtual/Online event. There are a couple of the event photos:

MOS-AK Session 1 (APR.18) begun: 8:00am Mexico time zone (GMT-5)

T_1 FOSSEE eSIM: An open source CAD software for circuit simulation

Kannan Moudgalya

IIT Bombay (IN)

T_2 Memristor modeling

Arturo Sarmiento

INAOE (MX)

T_3 Modeling Issues for CMOS RF ICs

Roberto Murphy, Jose Valdes and Reydezel Torres

INAOE (MX)

T_4 Improving Time-Dependent Gate Breakdown of GaN HEMTs with p-type Gate

E. Sangiorgi, A. Tallarico, N. Posthuma, S. Decoutere, C. Fiegna

Universita di Bologna

MOS-AK Session 2 (APR.18) begun: 1:00pm Mexico time zone (GMT-5)

T_5 Compact Models of SiC and GaN Power Devices

Alan Mantooth, Arman Ur Rashid, Md Maksudul Hossain

University of Arkansas (US)

T_6 New analytical model for AOSTFTs

Antonio Cerdeira

CINVESTAV-IPN, Mexico City (MX)

T_7 On the Parameter Extraction of Thin-Film Transistors in Weak-Conduction

Adelmo Ortiz-Conde

Solid State Electronics Laboratory, Simon Bolivar University, Caracas (VE)

End of MOS-AK Workshop
Group Photo