[paper] EKV compact modeling for oxide CTFTs

Mingyu Zhuang, Zhiyuan Wang, Baochuan Liu, Jiawei Zhang, Qian Xin, Aimin Song

Neural-network-assisted EKV compact modeling for complementary oxide thin-film transistors

Appl. Phys. Lett. 129, 123504 (2026)

DOI: 10.1063/5.0349365

1. Shandong Technology Center of Nanodevices and Integration, Uni. Shandong (CN)
2. Department of Electrical and Electronic Engineering, Uni. Manchester (UK)
3. Southern University of Science and Technology, Shenzhen (CN)

ABSTRACT: This work reports a neural-network-assisted Enz–Krummenacher–Vittoz (EKV) compact-modeling framework for complementary oxidethin-film transistors (TFTs). The neural network is used as a bias-dependent effective-parameter generator for the equivalent mobility and onset voltage, while the drain current is calculated by the analytical EKV current core. This strategy represents defect-, contact-, and bias-dependent nonidealities of oxide TFTs through effective quantities without replacing the current equation with a black-box neural-networkpredictor. The model is validated using both n-type indium–gallium–zinc oxide TFTs and p-type tin monoxide (SnO) TFTs, achieving mean absolute percentage errors of 0.56% and 0.36%, respectively. The learned effective parameters further provide an EKV-constrained compact representation of bias-dependent transport capability and channel-onset behavior obtained from global fitting of the measuredoutput-characteristic dataset, rather than serving as directly extracted material parameters. The trained model is translated into aPSpice-compatible library and applied to complementary inverter simulation, showing good agreement with measured voltage-transfer characteristics and reproducing the main transient response characteristics. These results demonstrate an accurate, analytically structured, and Simulation Program with Integrated Circuit Emphasis-compatible compact-modeling strategy that links bias-dependent oxide-TFTtransport to circuit-level simulation. 

FIG. (a) Equivalent parasitic‑capacitance and measurement‑loading network used in the transient simulation of the complementary SnO/IGZO inverter. (b) Simulated output waveforms for different values of the additional external capacitance.

Selected References:

[24] C. C. Enz, F. Krummenacher, and E. A. Vittoz, “An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications,” Analog Integr. Circuits Signal Process. 8, 83–114 (1995)

DOI: 10.1007/BF01239381

[25] J.-M. Sallese et al, “Inversion charge linearization in MOSFET modeling and rigorous derivation of the EKV compact model,” Solid-State Electron. 47, 677–683 (2003) 

DOI: 10.1016/S0038-1101(02)00336-2

[26] W. Grabinski et al, “FOSS EKV 2.6 parameter extractor,” in Proceedings of the 22nd International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES) (IEEE, 2015), pp. 181–186

DOI: 10.1109/MIXDES.2015.7208507

[paper] Datasheet‑Driven Automated Device Modeling

Siddharth Mohan, Mike Engelhardt, Tim McCune, and Jeff Strang

Datasheet-Driven Automated Device Modeling

22nd IEEE SMACD (2026) Dresden, Germany

DOI: 10.1109/SMACD70206.2026.11647759

* Qorvo Inc., CA, USA

Abstract: Accurate device models are a prerequisite fortrustworthy SPICE simulations, yet generating compact models from vendor datasheets has traditionally been time‑consuming anderror‑prone. QSPICE adds a Model Generators that build MOSFET, JFET, and diode models from commonly available datasheet values in minutes, integrating directly with its mixed‑mode simulator. We formalize a datasheet‑drivenworkflow (digitization, automated parameter mapping, simulation), and report qualitative validation across ID–VDS, ID–VGS, Coss, Qg, and IS–VSD characteristics using overlays from an industrial case study. We discuss adoption guidance, limitations, and opportunities for further quantitative benchmarking.

Fig: Automated model-generation workflow diagram.

AOB414 datasheet Available: https://www.designing-electronics.com/the-qspice-model-generator/

[program] ICMC2026

INTERNATIONAL COMPACT MODELING CONFERENCE PROGRAM

2026.si2-icmc.org

The 2026 conference continues under the theme “Enhancing Collaboration in Modeling with the Semiconductor Industry.” This year, ICMC especially encourages contributions in several timely and important areas, including electrostatic discharge (ESD) modeling for protection design, reliability and aging-aware compact models and simulation techniques, and the use of AI or machine learning for model development, parameter extraction, and circuit simulation efficiency. The conference also covers a broad range of topics in compact modeling, including the application of device models, device model development, model enhancements and implementations, and emerging devices.

This year’s technical program includes 3 keynote speakers, 7 invited speakers, 28 technical talks, 12 posters and a panel session. The program reflects both the depth and diversity of current modeling research and practice, ranging from model calibration and validation methodologies to reliability, RF, high-voltage, cryogenic, and emerging device applications.

Program at a Glance

Speaker	Title
	Keynote Presentations
Chenming Hu	BSIM, FinFET, and Open Innovation
Yuan Taur	Physical Insights Beyond the Textbook Modeling of MOSFETs and pn-junctions
Elyse Rosenbaum	Measurement Challenges Impeding the Verification of ESD Compact Model Accuracy and Generalizability
	Invited Presentations
James Victory	Modeling and Simulation Challenges in Modern Power Discrete Semiconductor Technologies
Gilson Wirth	Modeling of Low-Frequency Noise and BTI in Electron Devices
Chien-Ting Tung	Application of AI and ML in the Compact Modeling Domain
Michael Stockinger	On-Chip ESD Protection Design Optimization Using ESD Device Compact Models
Darsen Lu	Ferroelectric Memory Devices Compact Modeling and Applications
Meng-Lin Lu	Applications of Machine Learning Techniques in the Compact Modeling Platform
Lorenzo Peri	Compact Quantum Dot Models for Hybrid Microwave Circuits and Quantum Information Processing

Program Grid – Friday, July 30

Time	Session
8:30 - 8:45	Day 1 Welcome (Queens Salon)
8:45 - 9:25	[Keynote] BSIM, FinFET, and Open Innovation by Prof. Chenming Hu
9:25 - 10:25	Advances in Compact Modeling (Queens Salon)
10:25 - 10:45	Coffee Break (Royal Salon & Kings View Room)
10:45 - 12:10	Ferroelectric and other Nonvolatile Memories (Queens Salon)
12:10 - 13:20	Lunch Served (Royal Salon & Kings View Room)
13:20 - 14:00	[Keynote] Physical Insights Beyond the Textbook Modeling of MOSFETs and p-n Junctions by Prof. Yuan Taur
14:00 - 15:05	Emerging Devices and Technologies (Queens Salon)
15:05 - 15:25	Coffee Break (Royal Salon & Kings View Room)
15:25 - 16:30	Wide Bandgap Material Device Models (Queens Salon)
16:30 - 17:00	Poster Introductions (Queens Salon)
17:00	Poster Session & Reception (Verandah Grill/Deck)

Program Grid – Friday, July 31

Time	Session
8:30 - 8:40	Day 2 Welcome (Queens Salon)
8:40 - 9:20	[Keynote] Measurement Challenges Impeding the Verification of ESD Compact Model Accuracy and Generalizability by Prof. Elyse Rosenbaum
9:20 - 10:05	ESD Protections Modeling (Queens Salon)
10:05 - 10:25	Coffee Break (Royal Salon & Kings View Room)
10:25 - 11:55	Machine Learning and Artificial Intelligence in Compact Modeling (Queens Salon)
11:55 - 12:55	Lunch Served (Royal Salon & Kings View Room)
12:55 - 13:55	Panel Session: Machine Learning for Compact Modeling – Promises, Pitfalls, and Paths to Industry Adoption
13:55 - 14:40	Modeling of Noise and Traps (Queens Salon)
14:40 - 15:00	Coffee Break (Royal Salon & Kings View Room)
15:00 - 16:20	Devices at Cryogenic Temperatures (Queens Salon)
16:20 - 17:00	Closing Ceremony & Awards (Queens Salon)

[paper] Compact Modeling of Ferroelectric Devices

J. Lee, J. Kim, M. Kim, H. Kim, C. Ra, H. Choi, and J. Jeon,

“Asymmetry-Aware Compact Modeling of Ferroelectric Devices for Circuit-Level Simulation,”

ACS Applied Electronic Materials, Feb. 2026,

doi: 10.1021/acsaelm.5c02300

* Department of Electrical and Computer Engineering, Sungkyunkwan University (SKKU), Suwon 16419 (KR)

Abstract: This paper presents a unified compact model that comprehensively captures nonideal behaviors such as asymmetric hysteresis and minor loops of ferroelectric devices based on hafnium zirconium oxide (HfO2–ZrO2, HZO). The proposed model, based on the Preisach framework, integrates branch-dependent slopes, asymmetric coercive voltages, imprint-induced loop shifts, and low-voltage minor-loop responses into a unified analytical form. Implemented in Verilog-A, the proposed model reproduces measured polarization–voltage (P–V) characteristics of a ferroelectric capacitor (FeCAP) with higher accuracy than conventional symmetric models. Furthermore, using an identical parameter set, it consistently scales from a single device to logic, memory, and neuromorphic circuits, enabling prediction of operating characteristics and read/write margins. Owing to these capabilities, the model serves as a reliable predictive tool for circuit-level design and provides a practical pathway for process–design feedback and co-optimization.

[Data] CMOS SKY130 Cryo Primitives

Akturk, Akin, Li, Anhang, Saligane, Mehdi, Riem, Joseph, Adam, Gina, Hoskins,

Brian D, Shrestha, Pragya

CMOS SKY130 Primitives measured at cryogenic temperatures

NIST, (2023: Part of CHIPS METIS Data Collection)

Version: 1.1. Revised: 2024-03-27

DOI: 10.18434/mds2-2997 (Accessed 2026-01-03)

Abstract: SKY130 is an open source complementary metal oxide semiconductor (CMOS) technology manufactured by Skywater Technology (SKY) in its facility in Bloomington, Minnesota. Since it is an open source technology, there are no legal restrictions on its characterization, unlike in typical foundry semiconductor technologies. To facilitate the development of cryogenic electronics, this data set includes measurements of devices manufactured in SKY130 at low temperatures.

Fig: NIST Cryo Circuit Module Description

Name	File Type	Size
2997_README_v4.txt	Plain text	4.46 kB
ETest Tile.zip	Compressed file archive	3.81 MB
MPW-5 Test Tile.zip	Compressed file archive	39.5 MB

[paper] Low-Frequency Noise in Single-Layer Graphene FETs

An extended low-frequency noise compact model for single-layer graphene FETs 

including correlated mobility fluctuations effect

Nikolaos Mavredakis, Anibal Pacheco-Sanchez, and David Jiménez

https://arxiv.org/pdf/2512.08388

Departament d’Enginyeria Electrònica, Escola d’Enginyeria, Universitat Autònoma de Barcelona, Bellaterra 08193 (SP)
Departamento de Electrónica y Tecnología de Computadores, Universidad de Granada, 18011 Granada (SP)

Abstract: Correlated mobility fluctuations are considered in the physics-based carrier number fluctuation (ΔΝ) low-frequency noise (LFN) compact model of single-layer graphene field effect transistors (GFET) in the present study. Trapped charge density and Coulomb scattering coefficient ΔΝ LFN parameters are obtained after applying a parameter extraction methodology, adapted from conventional silicon technologies,to the linear ambipolar regions of GFETs. Appropriate adjustments are considered in the method according to GFETs’physical characteristics. Afterwards, Hooge mobility as well asseries resistance fluctuations LFN parameters can be extracted.The updated LFN model is validated with experimental data from various long and short-channel GFETs at an extendedrange of gate and drain bias conditions.

Fig: SID2/ID2 vs. VGS at 1 Hz for B (a) and A (b) -type RF GFETs with W=12μm and L=100nm

at VDS=60 mV. Markers: measurements, solid lines:model, dashed lines in (b): 

θint=0 V-1. Different colors represent different LFN contributions.

Acknowledgments: This work has received funding from the European Union’s Horizon2020 research and innovation programme under grant agreements NoGrapheneCore3 881603, from Ministerio de Ciencia, Innovación y Universidades under grant agreements RTI2018-097876-B-C21(MCIU/ AEI/ FEDER, UE), PID2021-127840NB-I00(MCIN/AEI/FEDER, UE), and CNS2023-143727 RECAMBIO (MCIN/AEI/ 10.13039 /501100011033). 

This work is also supported by the European Union Next Generation EU/PRTR research project.

[paper] Benchmarks for SPICE AI/ML Modeling

Colin C. McAndrew, Andries J. Scholten, Kiran K. Gullapalli, Yogesh Chauhan, and Kejun Xia

Benchmarks for SPICE Modeling and Parameter Extraction Based on AI/ML

IEEE Transactions on Electron Devices (2025)

DOI: 10.1109/TED.2025.3537952

1 Computer Engineering, Iowa State University, (USA)
2 NXP Semiconductors N.V., Eindhoven (NL)
3 NXP Semiconductors N.V., Austin (USA)
4 IIT Kanpur, (IN)
5 TSMC, Hsinchu (TW)

Abstract: Over the past decades, the number of submitted articles that use numerical approaches for SPICE models or for characterization (extraction) of parameters of existing SPICE models has grown significantly. Many of those articles rely on synthetic data, generated either from technology computer-aided design (TCAD) or from physical SPICE model simulations; most do not model/fit measured data. Furthermore, those articles do not evaluate the physical correctness, smoothness/monotonicity, or asymptotic correctness of the approach they propose. That is sufficient for initial evaluation of proposed techniques. However, it does not prove that they are “industrial strength.” This article presents benchmarks/guidelines for the proposed artificial intelligence (AI)/machine learning (ML) SPICE modeling and characterization techniques to try to help them become practical and useful.

TAB: CHECKLIST FOR MODELS

Capability	Existing State-of-the-Art	Proposed AI/ML Approach	Best Prior AI/ML Approach
obeys the laws of thermodynamics	✓	?	?
accurate DC modeling for all terminal currents, on relevant log/linear scale	✓	?	?
accurate capacitance/charge modeling	✓	?	?
models DC and capacitance interaction where relevant	✓	?	?
accurate modeling of high-frequency/non-quasi-static effects where relevant	✓	?	?
works for large-signal transient simulation, including delay effects	✓	?	?
accurate noise modeling	✓	?	?
has full geometry dependence	✓	?	?
has complete temperature dependence	✓	?	?
models all necessary LDEs	✓	?	?
behaves “well” for unreasonable geometry or temperature or bias	✓	?	?
exhibits physical monotonicity over bias, geometry, and temperature	✓	?	?
is smooth (ideally C∞-continuous)	✓	?	?
exhibits relevant physical symmetries (currents, charges, their derivatives)	✓	?	?
exhibits asymptotic correctness over geometry, temperature, and bias	✓	?	?
includes modeling of electrothermal effects (with frequency dependence)	✓	?	?
includes, or enables, modeling of global and local statistical variation	✓	?	?
includes, or enables, modeling of aging	✓	?	?
enables modeling of parasitics for different layouts	✓	?	?
is verified to converge reliably in at least one circuit simulator	✓	?	?

[C4P] ICMC 2025

STRENGTHENING MODELING COLLABORATION WITH THE SEMICONDUCTOR INDUSTRY

International Compact Modeling Conference (ICMC 2025)

June 26-27, 2025; The Clift Royal Sonesta, San Francisco

IMPORTANT DATES Abstract Submission Deadline January 15, 2025 Acceptance Notifications March 10, 2025 Full Paper Submission Deadline April 20, 2025 ORGANIZING COMMITTEE General Chair Peter M. Lee Micron  Vice Chair Shahed Reza Sandia Lab Technical Program Chair Colin Shaw Silvaco Technical Program Vice Chair Gert-Jan Smit NXP  Treasurer Leigh Anne Clevenger Si2 Secretariat Conference Catalysts icmc@conferencecatalysts.com

The Compact Model Coalition (CMC) brings academia and industry partners together in the development and standardization of compact models for semiconductor devices. For 30 years now, the CMC has been instrumental in creating standardized and verified models for designers to use in their increasingly complex circuits for SPICE simulation. The CMC is organizing a new and innovative International Compact Modeling Conference. Cosponsored by IEEE EDS, it will focus uniquely on compact device models, their development and broad application in the semiconductor industry. You are invited to participate in the evolution of these models, guide model development to help circuit designers create the best circuit performance possible, and enable foundries to leverage the strength of their device fabrication to full extent. Join the world experts in design, process technology, and model development to discuss state-of-the-art semiconductor device modeling for a two-day in-person event in one location, offering a great opportunity to present and learn about this core element of circuit design and how to get the most from these global collaborations. We are seeking papers for oral or poster presentations in the following areas: APPLICATION OF DEVICE MODELS Innovative application of CMC standard device models Best practices, novel use, and benefits of standard device models in circuit design Use of compact models to demonstrate foundry device capabilities DEVICE MODEL DEVELOPMENT Modeling of physical phenomena: Statistical variation, reliability and aging, noise and fluctuations, high frequency effects, Electrostatic Discharge (ESD), self heating, layout effects, etc. Methodologies to assist in model development, practices for coding, quality assurance, circuit simulator integration, etc. Parameter extraction, measurement techniques, model calibration, validation, and verification methodologies, including solutions based on AI or Machine Learning. MODEL ENHANCEMENTS AND IMPLEMENTATIONS Model extensions to capture additional device features (leakage, noise, capacitance, second-order dependencies, …) or expand the operating range of existing devices (bias, power, temperature, frequency, etc.) Model enhancements to support the design of new or demanding circuits Model workflow, implementation, and integration into the design environment (PDK) Computing/simulation platforms, simulation algorithms, and methodologies to improve simulation performance (parallel processing, etc.) Models for established device types that currently lack standardization. MODELING FOR FUTURE/EMERGING TECHNOLOGIES AND APPLICATIONS Models for emerging device types or architectures on the horizon, such as, ferroelectric devices, silicon photonics, cryogenic, quantum computing, etc. Modeling of new physical phenomena in support of current and novel device technologies Novel device technologies currently being researched that could further revolutionize circuit performance, have implications in the design flow, and may become mainstream in the future Please submit your paper proposals in the form of a 2-page abstract for review by January 15, 2025 here 2025.si2-icmc.org. Acceptance notifications will be sent by March 10, 2025. Accepted contributions (for both oral and poster presentations) are expected to submit a camera-ready 4-page draft version of their papers by April 20, 2025 and final version by May 23, 2025 for publication in IEEE Xplore®.

[paper] FOSS support for CM with Verilog-A

Bűrmen, Árpád, Tadej Tuma, Iztok Fajfar, Janez Puhan, Žiga Rojec, Matevž Kunaver

and Sašo Tomažič

Free software support for compact modelling with Verilog-A

Informacije MIDEM 54, no. 4 (October 9, 2024)

<https://ojs.midem-drustvo.si/index.php/InfMIDEM/article/view/1999>

Abstract: Verilog-A is the analog subset of Verilog-AMS - a hardware description language for analog and mixed-signal systems. Verilog-A is commonly used for the distribution of compact models of semiconductor devices. For such models to be usable a Verilog-A compiler is required. The compiler converts the model equations into a form that can be used by the simulator. Such compilers have been supplied with commercial simulators for many years now. Free software alternatives are much more scarce and limited in the features they offer. The paper gives an overview of Verilog-A, Free software Verilog-A compilers, and Free software/Open source simulators that can simulate compact models defined in Verilog-A. Advantages and disadvantages of individual compilers and simulators are highlighted.

Tab: Comparison of Free software simulators

Asterisk denotes a feature under development as of Sep. 2024

Acknowledgements: This research was funded in part by the Slovenian Research Agency within the research program ICT4QoL—Information and Communications Technologies for Quality of Life, grant number P2-0246.

[paper] Compact Modeling of Hysteresis in OTFTs

Compact modeling of hysteresis in organic thin-film transistors

A. Romero^a, J.A. Jiménez-Tejada^a, R. Picos^b, D. Lara^a, J.B. Roldán^a, M.J. Deen^c

Organic Electronics 129 (2024) 107048

DOI : 10.1016/j.orgel.2024.107048

a Departamento de Electrónica y Tecnología de Computadores, CITIC-UGR, Uni Granada, Spain
b Department of Industrial Engineering and Construction, Universitat de les Illes Balears, Spain
c Department of Electrical and Computer Engineering, McMaster University, Canada

Abstract: In this work, we propose a model that describes the temporal evolution of the threshold voltage and trapped charge density in Thin-Film Transistors (TFTs) under dynamic conditions, paving the way for the characterization and modeling of memory transistors. The model is expressed as a first-order differential equation for the trapped charge density, which is controlled by a time constant and an independent term proportional to the drain current. The time-dependent threshold voltage is introduced in a previously developed compact model for TFTs with special consideration to the contact effects. The combination of both models and the use of an evolutionary parameter extraction procedure allow for reproducing the experimental dynamic behavior of TFTs. The results of the model and the evolutionary procedure have been validated with published experimental data of pentacene-based transistors. The procedure is able to simultaneously reproduce three kinds of experiments with different initialization routines and constraints in each of them: output and transfer characteristics with hysteresis and current transients characteristics

FIG: a.) Modeling the contact regions and intrinsic channel of an OTFT structure (a bottom contact configuration); b.)  Comparison of experimental transfer characteristics

Acknowledgements : The authors acknowledge support from the project PID2022 139586NB-44 funded by MCIN/AEI/10.13039/501100011033 and FEDER, EU. Funding for open access charge: Universidad de Granada / CBUA.

Appendix: Supplementary material related to this article can be found online.

[paper] Neural Compact Modeling Framework

Eom, Seungjoon, Hyeok Yun, Hyundong Jang, Kyeongrae Cho, Seunghwan Lee, Jinsu Jeong, and Rock‐Hyun Baek

Neural Compact Modeling Framework for Flexible Model Parameter Selection with High Accuracy and Fast SPICE Simulation

Advanced Intelligent Systems (2023): 2300435

DOI: 10.1002/aisy.202300435

Department of Electrical Engineering, Pohang University of Science and Technology, Pohang 37673 (KR)

Abstract: Neural compact models are proposed to simplify device-modeling processes without requiring domain expertise. However, the existing models have certain limitations. Specifically, some models are not parameterized, while others compromise accuracy and speed, which limits their usefulness in multi-device applications and reduces the quality of circuit simulations. To address these drawbacks, a neural compact modeling framework with a flexible selection of technology-based model parameters using a two-stage neural network (NN) architecture is proposed. The proposed neural compact model comprises two NN components: one utilizes model parameters to program the other, which can then describe the current–voltage (IV) characteristics of the device. Unlike previous neural compact models, this two-stage network structure enables high accuracy and fast simulation program with integrated circuit emphasis (SPICE) simulation without any trade-off. The IV characteristics of 1000 amorphous indium–gallium–zinc-oxide thin-film transistor devices with different properties obtained through fully calibrated technology computer-aided design simulations are utilized to train and test the model and a highly precise neural compact model with an average IDS error of 0.27% and R2 DC characteristic values above 0.995 is acquired. Moreover, the proposed framework outperforms the previous neural compact modeling methods in terms of SPICE simulation speed, training speed, and accuracy.

Fig: a) The structure of a-IGZO TFT structure simulated with TCAD

b) Calibrated a-IGZO sub-gap DOS

Acknowledgements: This work was supported in part by the LG Display Company, in part by the Brain Korea 21 Fostering Outstanding Universities for Research (BK21 FOUR) program, in part by Institute of Information and Communications Technology Planning and Evaluation (IITP) grant funded by the Korea government (MSIT) (grant no. 2019-0-01906, Artificial Intelligence Graduate School Program [POSTECH]), in part by the Ministry of Trade, Industry and Energy (MOTIE) under grant no. 20020265, in part by Korea Semiconductor Research Consortium (KSRC) support program for the development of the future semiconductor device, and in part by the Technology Innovation Program (grant no. RS2023-00231985) funded by the Ministry of Trade, Industry and Energy (MOTIE, Korea) (grant no. 1415187390).

[paper] Surface-Potential-Based Compact Modeling

M. Miura-Mattausch, T. Iizuka, H. Kikuchihara, H. J. Mattausch, and S. Saha

Evolution of Surface-Potential-Based Compact Modeling

IEEE EDS NEWSLETTER

OCTOBER 2023 VOL. 30, NO. 4 ISSN: 1074 1879

Abstract: Conventionally, a compact model of an electronic device is developed for utilization in circuit simulation. This means that the main task of the compact model is to accurately describe the characteristics of a device as a function of the applied voltages by simple equations in order to predict the performance of circuits using this device with sufficient precision. This overview article focuses on the compact modeling of the metal-oxide-semiconductor field-effect transistor (MOSFET)-device structure, which has the largest variety of applications. However, the modeling methodology is valid for any type of transistor or electronic device. The development of the compact modeling approach, based on the potential distribution induced within a transistor, is reviewed. The purpose of a compact model is to describe the transistor characteristics in a simple but accurate way, to enable correct circuit-performance prediction. Therefore, the basic physics of observed phenomena must be modeled by simplified and yet physically correct equations. To meet such requirements, potential-based modeling is a natural fit. A compact model and TCAD are both based on the same transistor equations. The difference is that TCAD considers the distribution of all physical quantities within a device, and a compact model integrates these distributions to calculate transistor characteristics at its nodes. The shortcomings of resulting simplifications, introduced for analytical integration, can be examined using TCAD, to identify observed phenomena still missing in the compact modeling. In this way, compact modeling is performed by learning from measurements macroscopically and from TCAD microscopically.

Fig: Schematic of a HV LDMOS FET (top) 

and its potential distribution (bottom)

[book chapters] Equation-Based Compact Modeling

 

Debnath, P., Sarkar, B., & Chanda, M. (Eds.). (2023).

Differential Equation Based Solutions 

for Emerging Real-Time Problems

(1st ed.). CRC Press 

DOI 10.1201/9781003227847

Chapter: Differential Equation-Based Compact 2-D Modeling of Asymmetric Gate Oxide Heterojunction Tunnel FET; By: Sudipta Ghosh, Arghyadeep Sarkar

Abstract: Tunnel Field Effect Transistor (TFET) has emerged as an effective alternative device to replace MOSFET for a few decades. The major drawbacks of MOSFET devices are the short-channel effects, due to which the leakage current increases with a decrease in device dimension. So, scaling down TFET is more efficacious than that of MOSFETs. Sub-threshold swing (SS) is another advantageous characteristic of TFET devices for high-speed digital applications. In TFETs the SS could be well below 60 mV/decade, which is the thermal limit for MOSFET devices and therefore makes it more suitable than MOSFET for faster switching applications. It is observed from the literature studies that the performances of the TFET devices have been explored thoroughly by using 2-D TCAD simulation but an analytical model is always essential to understand the physical behavior of the device and the physics behind this; which facilitates further, the analysis of the device performances at circuit level as and when implemented.

Chapter: Differential Equation-Based Analytical Modeling of the Characteristics Parameters of the Junctionless MOSFET-Based Label-Free Biosensors; by: Manash Chanda, Papiya Debnath, Avtar Singh

Abstract: Recently Field Effect transistor (FET)-based biosensing applications have gained significant attention due to the demand for quick and accurate diagnosis of different enzymes, proteins, DNA, viruses, etc; cost-effective fabrication process; portability and better sensitivity and selectivity compared to the existing biosensors. FET is basically a three-terminal device with source, drain, and gate terminals. Basically, the gate terminal controls the current flow between the source and drain terminals. In FETs, first, a nanogap is created in the oxide layer or in the gate by etching adequate materials. When the biomolecules are trapped inside the nanocavity then the surface potentials change and also the threshold voltage varies. As a result, the output current also changes. Finally, by measuring the changes in the threshold voltage or the device current, one can easily detect the biomolecules easily.

[paper] Schottky Barrier FET at Deep Cryogenic Temperatures

Christian Roemer^1,2, Nadine Dersch¹, Ghader Darbandy¹, Mike Schwarz¹,

Yi Han³, Qing-Tai Zhao³, Benjamın Iniguez² and Alexander Kloes¹

Compact Modeling of Schottky Barrier Field-Effect Transistors 

at Deep Cryogenic Temperatures

EUROSOI-ULIS 2023

in Tarragona (Catalonia, Spain) on May 10-12 2023

1 NanoP, TH Mittelhessen - University of Applied Sciences, Giessen, Germany
2 DEEEA, Universitat Rovira i Virgili, Tarragona, Spain
3 Peter-Grunberg-Institute (PGI 9), Forschungszentrum Julich, Germany

Abstract: In this paper, a physics-based DC compact model for Schottky barrier field-effect transistors at deep cryogenic temperatures is presented. The model uses simplified tunneling equations at temperatures of ϑ ≈ 0 K in order to calculate the field emission injection current at the device’s Schottky barriers. The compact model is also compared to and verified by measurements of ultra-thin body and buried oxide SOI Schottky barrier field-effect transistors and is able to capture the signature of resonant tunneling effects in the transfer characteristics.

FIG: Band diagram at the source side Schottky junction (left-hand side). The solid blue line is the conduction band of the channel and the blue dashed line shows the metal’s Fermi energy level. The right-hand side subplot shows the tunneling probability, with the exponential part (red line) and the total probability, including the oscillations (green line).

Compact Modeling of 2D Field-Effect Biosensors

Francisco Pasadas¹, Tarek El Grour², Enrique G. Marin¹, Alberto Medina-Rull¹, Alejandro Toral-Lopez¹, Juan Cuesta-Lopez¹, Francisco G. Ruiz¹, Lassaad El Mir² and Andrés Godoy¹

Compact Modeling of Two-Dimensional Field-Effect Biosensors.

Sensors 2023, 23, 1840.

DOI: 10.3390/s23041840

1 Pervasive Electronics Advanced Research Laboratory (PEARL), Departamento de Electrónica y Tecnología de Computadores, Universidad de Granada,18071 Granada, Spain
2 Laboratory of Physics of Materials and Nanomaterials Applied at Environment (LaPhyMNE) LR05ES14, Faculty of Sciences of Gabes, Gabes University, Erriadh City, Zrig, 6072 Gabes, Tunisia

Abstract: A compact model able to predict the electrical read-out of field-effect biosensors based on two-dimensional (2D) semiconductors is introduced. It comprises the analytical description of the electrostatics including the charge density in the 2D semiconductor, the site-binding modeling of the barrier oxide surface charge, and the Stern layer plus an ion-permeable membrane, all coupled with the carrier transport inside the biosensor and solved by making use of the Donnan potential inside the ion-permeable membrane formed by charged macromolecules. This electrostatics and transport description account for the main surface-related physical and chemical processes that impact the biosensor electrical performance, including the transport along the low-dimensional channel in the diffusive regime, electrolyte screening, and the impact of biological charges. The model is implemented in Verilog-A and can be employed on standard circuit design tools. The theoretical predictions obtained with the model are validated against measurements of a MoS2 field-effect biosensor for streptavidin detection, showing excellent agreement in all operation regimes and leading the way for the circuit-level simulation of biosensors based on 2D semiconductors

FIG: Schematic of a two-dimensional field-effect biosensor. A sketch of the position-dependent potential is also shown, highlighting the surface charge density at the 2D channel (σ2D), at the oxide-electrolyte interface (σ0), and at the membrane-diffuse regions of the electrolyte (σmd). The latter comprises a charge-free layer (Stern layer) and an ion-permeable membrane due to the presence of charged macromolecules, with a diffusion layer located between the barrier oxide surface and the bulk electrolyte. The potential difference from the electrolyte bulk to the barrier oxide surface, ψ0, encompasses two contributions originating from a potential drop (ψ0 − ψm) across the Stern layer extending between the outer Helmholtz plane (OHP) and the barrier oxide surface, and a potential drop across the ion-permeable membrane layer formed by charged macromolecules and the diffuse layer (ψm)

Funding: This work is funded by the Spanish Government MCIN/AEI/10.13039/501100011033 through the projects PID2020-116518GB-I00 and TED2021-129769B-I00 (MCIU/AEI/FEDER-UE); and by FEDER/Junta de Andalucía-Consejería de Transformacion Económica, Industria, Conocimiento y Universidades through the projects P20_00633 and A-TIC-646-UGR20. F. Pasadas acknowledges funding from PAIDI 2020 and the European Social Fund Operational Programme 2014–2020 no. 20804. A. Medina-Rull acknowledges the support of the MCIN/AEI/PTA grant, with reference PTA2020- 018250-I. J. Cuesta-Lopez acknowledges the FPU program FPU019/05132, and A. Toral-Lopez the support of Plan Propio of Universidad de Granada.

Data Availability Statement: The Verilog-A model for 2D EIS BioFETs is available from the corresponding author (fpasadas@ugr.es) upon reasonable request.

[analog-wg] Video of March 21 AWG Meeting

The Analog Workgroup (AWG) was formed by the CHIPS Alliance TSC to explore collaborations in open source Analog/Mixed-Signal design and verification. It focuses on sharing best practices, ideas, tooling (analog automation), and other challenge areas in the design space. The workgroup is composed of both industry and university members.

The AWG Video Meeting on March 21, 2023 included two presentations:

• Ken Kundert "Why Fund OpenVAF"
• Pascal Kuthe "OpenVAF: An innovative open-source Verilog-A Compiler"

Please note the following line of topics for the Analog Workgroup

• 4th April: Update from Tim Edwards: Magic and PEX extraction
• 18th April: Update from Sadayuki Yoshitomi: Ecosystem of compact model development 
• 2nd May (tentative): Update from C. Enz,EPFL:  test structures measurements

Neural networks and machine learning approach for compact modeling

[NN] Wang, Qiuwei, Mao Ye, Yao Li, Xiaoxiao Zheng, Jiaji He, Jun Du, and Yiqiang Zhao. "MOSFET modeling of 0.18 μm CMOS technology at 4.2 K using BP neural network." Microelectronics Journal (2023): 105678. DOI: 10.1016/j.sse.2022.108580

Highlights

• The cryogenic characterization of SMIC CMOS technology at 4.2K is presented.
• An optimization model VCCS is proposed to calibrate the cryogenic characteristics.
• BP neural network is, for the first time, used in MOSFET modeling.
• The cryo-model can be applied to SPICE simulator and assist in cryo-CMOS circuit design and simulation.

Fig: The structure of graph-based compact model of FinFET. The model receives the input features such as voltages, geometries, etc. as a vector and predicts the drain current (Ids) and its derivatives as output features.

[ML] Gaidhane, Amol D., Ziyao Yang, and Yu Cao. "Graph-based Compact Modeling (GCM) of CMOS transistors for efficient parameter extraction: A machine learning approach." Solid-State Electronics (2023): 108580.

Highlights

• Developed a Graph-based compact model for FinFET.
• Model implemented in Verilog-A for SPICE simulation.
• Requires less number of model parameters and is computationally efficient than BSIM

[paper] Universal Charge Model for Multigate MOS Structures

Kwang-Woon Lee and Sung-Min Hong

Derivation of a Universal Charge Model for Multigate MOS Structures

with Arbitrary Cross Sections

IEEE TED (2022, Early Access)

DOI:  10.1109/TED.2022.316486

   

* Gwangju Institute of Science and Technology (KR)

Abstract: A universal equation for the charge-voltage characteristics in the multigate metal oxide semiconductor (MOS) structure with an arbitrary cross section is presented. A generalized coordinate is proposed and the Poisson equation is integrated with a weighting factor related with the generalized coordinate and the electric field. A compact charge model is derived and analytic and numerical examples for various MOS structures are shown.

Fig: Thin slab in the semiconductor channel region of the multigate MOS structure. The A∗ surfaces are perpendicular to the z-direction, which is the transport direction and its generalized coordinate, ψ, for rectangular nanosheet MOS structures at 0.0 V (top) and 0.7 V (bottom).

Aknowlegements: This workwas supported by the National Research Foundation of Korea (NRF) Grant funded by the Korean Government under Grant NRF- 2019R1A2C1086656 and Grant NRF-2020M3H4A3081800.

[paper] Compact Modelling of Si Nanowire/Nanosheet MOSFETs

A. Cerdeira¹, M. Estrada¹, and M. A. Pavanello²

On the compact modelling of Si nanowire and Si nanosheet MOSFETs

Semiconductor Science and Technology, vol. 37, no. 2, p. 025014, Jan. 2022.

DOI: 10.1088/1361-6641/ac45c0

   

1 Centro de lnvestigacién y de Estudios Avanzados del IPN, Mexico City, Mexico
2 Centro Universitario PEI, Sao Bernardo do Cainpo, Sao Paulo, Brazil

Abstract: In this paper, three-dimensional technology computer aided design simulations are used to show that the electron concentration, current density, and electric field distribution from the interface at the lateral channels and from the top channel to the centre of the silicon wire, in nanowire and nanosheet structures, are practically same. This characteristic makes it possible to consider that the total channel width for these structures is equal to the perimeter of the transistor sheet, allowing to extend of the application of the symmetric doped double-gate model (SDDGM) model to nanowires and nanosheets metal-oxide-semiconductor field effect transistors, with no need to include new parameters. The model SDDGM is validated for this application using several measured and simulated structures of nanowires and nanosheets transistors, with different aspect ratios of fin width and fin height, showing very good agreement between measured or simulated characteristics and modelled. SDDGM is encoded in Verilog-A language and implemented in SPICE circuit simulator.

Fig: a.) Normalized measured and modelled transfer characteristics of stacked transistor in the linear region at VDS=0.025V and in saturation region at VDS=0.75V; b.) Output characteristic and conductance at VGS=1V.

Acknowledgments: The authors are grateful to CEA—Leti for providing the exper- imental samples used in this paper. This work was supported by the CONACYT project 236887, CNPq, Sao Paulo Research Foundation (FAPESP) Grants 2015/ 1049 1-7 and 2019/ 15500- 5, and the IBM/STMicroelectronics/Leti Joint Development Alliance.

 

8th EuroSOI-ULIS 2022 at University of Udine (Italy)

Organized by: University of Udine (Italy) Conference chair: Pierpaolo Palestri Local organizing Committee: Francesco Driussi David Esseni Daniel Lizzit Conference Secretariat: Centro Congressi Internazionali  Steering Committee: Francis BALESTRA (IMEP Minatec, France) Maryline BAWEDIN (IMEP-LAHC, France) Cor CLAEYS (KU-Leuven, Belgium) Bogdan CRETU (ENSICAEN, France) Sorin CRISTOLOVEANU (IMEP-LAHC, France) Francisco GAMIZ (UnivGranada, Spain) Elena GNANI (Univ. of Bologna, Italy) Benjamin INIGUEZ  (URV, Spain) Joris LACORD (CEA-Leti, France) Enrico SANGIORGI (Univ.Bologna, Italy) Luca SELMI (Univ. of Modena, Italy) Viktor SVERDLOV (TU Wien, Austria) Andrei VLADIMIRESCU (ISEP, France) Sponsors:

8th Joint International EuroSOI Workshop and International Conference on Ultimate Integration on Silicon (EuroSOI-ULIS) 2022 May 18-20, 2022 – Udine, Italy https://eurosoiulis2022.com The Conference aims at gathering together scientists and engineers working in academia, research centers and industry in the field of SOI technology and nanoscale devices in More-Moore and More-Than-Moore scenarios. High quality contributions in the following areas are solicited: Advanced SOI materials and structures, innovative SOI-like devices. Alternative transistor architectures (FDSOI, Nanowire, FinFET, MuGFET, vertical MOSFET, FeFET and TFET, MEMS/NEMS, Beyond-CMOS). New channel materials for CMOS (strained Si/Ge, III-V, carbon nanotubes; graphene and other 2D materials). Properties of ultra-thin semiconductor films and buried oxides, defects, interface quality; thin gate dielectrics: high-κ and ferroelectric materials for switches and memory. New functionalities and innovative devices in the More than Moore domain: nanoelectronic sensors, biosensor devices, energy harvesting devices, RF devices, imagers, integrated photonics (on SOI), etc. Transport phenomena, compact modeling, device simulation, front- and back-end process simulation. CMOS scaling perspectives; device/circuit level performance evaluation; switches and memory scaling; three-dimensional integration of devices and circuits, heterogeneous integration. Advanced test structures and characterization techniques, parameter extraction, reliability and variability assessment techniques for new materials and novel devices. Original 2-page abstracts with illustrations will be reviewed by the Scientific Committee. The accepted contributions will be published as 4-page letters in a special issue of the Elsevier journal Solid-State Electronics. Extended versions of outstanding papers will be published in a further special issue of Solid-State Electronics. A best poster award will be attributed by ELSEVIER.  The “Androula Nassiopoulou Best Paper Award" will be attributed by the SINANO institute. Important dates: abstract submission deadline: March 1, 2022 notification of acceptance: March 15, 2022