[paper] TCAD Modeling of SB Diode

Pedro Paulo Pessoa Oliveira1,2, Andreas Mai1,3, Norbert Herfurth1, 

and Davies William de Lima Monteiro2

TCAD Modeling of Schottky-Diode in an open-source SiGe BiCMOS technology

In 2026 40th Symposium on Microelectronics Technology and Devices 

SBMicro, pp. 1-4. IEEE, 2026

DOI: 10.1109/SBMicro70495.2026.11684441

1. IHP, Frankfurt (Oder), Germany
2. Department of Electrical Engineering, UFMG - Belo Horizonte-MG, Brazil
3. University of Applied Sciences Wildau, Germany

Abstract: Accurate simulation of Schottky barrier diodes (SBDs) is challenging because standard idealized models fail to capture non-ideal interface physics, such as Fermi-level pinning and image-force lowering. This paper presents an enhanced Technology Computer-Aided Design (TCAD) methodology to model an SBD from the IHP SG13G2 130-nm open-source SiGe BiCMOS technology. To overcome limitations of conventional simulations that often rely on oversimplified assumptions and empirical fitting, this work explicitly incorporates interface en- ergy states into the simulation, specifically modeling the fun- damental pinning mechanisms driven by Metal-Induced Gap States (MIGS). By calibrating the TiSi2/Si interface using the theoretical slope parameter, a value of 0.503 V was determined for the zero-bias barrier height. The resulting physics-based model captures the true rectifying nature of the contact and accurately reproduces the electrical characteristics targeted by the empirical model, achieving a nominal forward voltage drop of 0.39 V and a realistic reverse leakage current of 29.3 nA at -2.5 V. Ultimately, this paper shows the innovation and education gain of open- source foundry data by showcasing an open innovation path for a targeted near-industry device development flow.

FIG: a.) Energy band diagram of the Schottky diode at V=0V. Thecoordinate x = 0 corresponds to the TiSi2/n-Si Schottky interface. The inset displays the 2D device schematic, with the solid black line indicating the multi-segment cut-path used to extract the energy levels across the anode, n-buried layer and n-well RT to cathode contact. b.) Comparison of the simulated DC current-voltage (IV) characteristics between the proposed TCAD model and the standard SPICE macromodel.

Acknowledgment: The authors thank IHP for the open-source PDK and the collaborative research. They also thank Universidade Federal de Minas Gerais (UFMG) and the Brazilian Microelectronics Society (SBMicro) for supporting this work. Finally, gratitude is extended to S. Srivastava and B. Sake for their valuable guidance.

2nd Semiconductor Device Frontier Summit

Date: May 18, 2026; Time: 10:00AM ~ 05:00PM

Ewha Womans University Student Culture Center (Small Theater B101)

The Semiconductor Device Research Group of the Society of Semiconductor Engineers has been holding this event since 2025 to strengthen human networks among domestic researchers and share the latest research trends.

This year's summit, now in its second year, invited top-notch speakers from various fields to provide a broad view of the latest technologies in industry and academia. It will be a place for meaningful academic exchanges to grasp the latest semiconductor technology trends as well as to share in-depth opinions on international market trends. This event is co-organized by the Society of Semiconductor Engineers and the IEEE EDS Seoul Section Chapter and aims to become an international event representing the semiconductor device field in Korea in the future. We ask for your interest and participation so that the 'Semiconductor Device Frontier Summit', which will be the core pillar of the Korean researcher network, can become the cornerstone of the development of our semiconductor industry.

Pre-registration deadline: Until May 16, 2026 (Saturday)

Time	Program
Opening Session
10:00 – 10:20	Welcome & Registration
10:20 – 10:30	Opening Remarks (Prof. Sung‑Jae Cho, Ewha Womans University)
Session 1 | Chair: Prof. Sung‑Jae Cho
10:30 – 11:15	Semiconductor Devices for the New Computing Era Prof. Woo‑Young Choi, Seoul National University
11:15 – 12:00	Development Strategy for AI‑Oriented NAND Solutions Prof. Ki‑Hwan Song, Yonsei University
12:00 – 13:30	Lunch
Session 2 | Chair: Prof. Myung‑Gon Kang
13:30 – 14:15	Trends and Outlook of eNVM Technology Visiting Prof. Yong‑Gyu Lee, Seoul National University
14:15 – 15:00	Memcapacitor Technology for Charge‑Domain PIM Implementation Prof. Tae‑Hyun Kim, Seoul National University of Science and Technology
15:00 – 15:10	Coffee Break
Session 3 | Chair: Prof. Il‑Hwan Cho
15:10 – 15:55	Atomically Thin 2D Semiconductor Electronics toward Beyond‑CMOS Technology Prof. Chul‑Ho Lee, Seoul National University
15:55 – 16:40	Orders‑of‑Magnitude Faster TCAD Device Simulation of GAA MOSFETs without Additional Computational Training Cost Prof. Sung‑Min Hong, GIST
16:40 – 17:00	Closing Ceremony | Prof. Il‑Hwan Cho, Myongji University

[paper] Is there anything left to do in TCAD?

Z. Stanojevic, F. Schanovsky, G. Rzepa, X. Klemenschits, H. Demel, 

O. Baumgartner, C. Kernstock, and M. Karner

Is there anything left to do in TCAD?

SISPAD  in Grenoble, Sept. 24 2025

https://sispad2025.inviteo.fr/

1. Global TCAD Solutions GmbH., Bosendorferstraße 1/12, 1010 Vienna (A) 

Abstract: Over the past decade, the development of commercial technology computer-aided design (TCAD) software has followed an evolutionary rather than revolutionary path. Alongside established continuum and particle-based approaches in both process and device simulation, advanced carrier transport models - such as deterministic bulk and subband Boltzmann transport equation (BTE) solvers and non-equilibrium Green’s functions (NEGF) - have been incorporated into the TCAD toolkit for single-device simulation. At the system level, the field of design-technology co-optimization (DTCO) has expanded to encompass variability, reliability, and the extension of TCAD methodologies from devices to circuits. However, most of these innovations were introduced over a decade ago, prompting the question: What remains to be developed in TCAD? We address this question by analyzing current limitations and potential future directions in TCAD development across three key dimensions: (1) fidelity, (2) integration, and (3) efficiency - each with particular relevance in commercial and industrial contexts. We examine ongoing challenges in classical TCAD, advanced transport modeling, and DTCO flows, and point to potential directions for future developments. Among these, we include various methodologies related to machine learning and hardware accelerators, particularly within the efficiency dimension.

FIG: Device 3D structure generated from a layout (GDSII) and a technology file

See also...

[paper] Virtual N2 PDK

Yiying Liu , Minghui Yin , Huanhuan Zhou, Yunxia You, Weihua Zhang, Hongwei Liu, Chen Wang, Yajie Zou, and Zhiqiang Li

Virtual_N2_PDK: A Predictive Process Design Kit for 2-nm Nanosheet FET Technology

IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2025)

DOI: 0.1109/TVLSI.2025.3529504

1 EDA Center, Institute of Microelectronics, Chinese Academy of Sciences, Beijing (CN)
2 School of Integrated Circuits, University of Chinese Academy of Sciences, Beijing (CN)
3 State Key Laboratory of Fabrication Technologies for Integrated Circuits, Beijing (CN)

Abstract: Nanosheet FETs (NSFETs) are considered promising candidates to replace FinFETs as the dominant devices in sub-5-nm processes. To encourage further research into NSFET-based integrated circuits, we present Virtual_N2_PDK, a predictive process design kit (PDK) for 2-nm NSFET technology. All assumptions are based on publicly available sources. Ruthenium (Ru) interconnects are employed for the buried power rail (BPR) and tight-pitch layers. Wrap-around contact (WAC) is also integrated into Virtual_N2_PDK to investigate its impact on circuit performance. By calibrating the BSIM-CMG model with 3-D technology computer-aided design (TCAD) electrothermal simulation results, SPICE models that account for self-heating effects (SHEs) are generated for devices with and without WAC. The simulation results show that with the WAC structure, the energy-delay product (EDP) of standard cells is reduced by an average of 25.18%, while the frequency of a 15-stage ring oscillator circuit increases by 26.05%.

FIG: 3D view of the NSFET structure and layouts of SRAM bit cells:
(b) 111 SRAM cell, (c) 112 SRAM cell, and (d) 122 SRAM cell.

Acknowledgements: This work was supported in part by the Strategic Priority Research Program of Chinese Academy of Sciences (CAS) under Grant XDA0330401 and in part by CAS Youth Interdisciplinary Team under Grant JCTD-2022-07.

[paper] TCAD for Circuits and Systems

Z. Stanojevic, X. Klemenschits, G. Rzepa, F. Mitterbauer, C. Schleich,

F. Schanovsky, O. Baumgartner, and M. Karner

TCAD for Circuits and Systems: Process Emulation, Parasitics Extraction, Self-Heating

2024 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium

BCICTS, Fort Lauderdale, FL, USA, 2024, pp. 294-297

doi: 10.1109/BCICTS59662.2024.10745677

1 Global TCAD Solutions GmbH., Boesendorferstraße 1/12, 1010 Vienna, Austria

Abstract: We present TCAD-based methodologies that go beyond process and device simulations of single transistors. We show that TCAD solvers can be used as effective tools to resolve the intricacies of current and future technology nodes that are otherwise difficult to access using EDA-level methods alone.

Fig: Single NMOS/PMOS FinFET with the local contacts and their parasitic R/C-components; fitting results for NMOS and PMOS FinFET: gate capacitance, transfer characteristics, output characteristics

List of the publications using or referring to DEVSIM

List of the publications using or referring to DEVSIM

[1] K. Wang et al.; Design and simulation of a novel 4H-SiC LGAD timing device; Radiation detection technology and methods; (2023) https://doi.org/10.1007/s41605-023-00431-y
[2] J. Lauwaert; Technology computer aided design based deep level transient spectra: Simulation of high-purity germanium crystals; Journal of Physics D: Applied Physics; (2022) https://doi.org/10.1088/1361-6463/ac34ad
[3] Q. Chen et al.; Analytical model for donor like Gaussian traps in organic thin-film transistor; Organic Electronics; (2021) https://doi.org/10.1016/j.orgel.2022.106464
[4] Q. Chen et al.; The Impact of Contact Position on the Retention Performance in Thin-Film Ferroelectric Transistors; Physica Status Solidi A; (2021) https://doi.org/10.1002/pssa.202100408
[5] L. Hulbert; Designing a Simulator for an Electrically-Pumped Organic Laser Diode; Master’s Thesis; (2019) https://doi.org/10.15368/theses.2019.60
[6] J. E. Sanchez and Q. Chen; Element Edge Based Discretization for TCAD Device Simulation; IEEE Transactions on Electron Devices; (2021) https://doi.org/10.1109/TED.2021.3094776
[7] J. Lauwaert; Fill Factor Loss in a Recombination Junction for Monolithic Tandem Solar Cells; ACS Appl. Energy Mater.; (2023) https://doi.org/10.1021/acsaem.3c00041
[8] J. E. Sanchez; DEVSIM: A TCAD Semiconductor Device Simulator; Journal of Open Source Software; (2022) https://doi.org/10.21105/joss.03898
[9] L. Rickert et al.; High-performance designs for fiber-pigtailed quantum-light sources based on quantum dots in electrically-controlled circular Bragg gratings; Optics Express; (2023) https://doi.org/10.1364/OE.486060
[10] L. R. Brennaman & A. J. Samin; Insights into the performance of InAs-based devices in extreme environments from multiscale simulations; Applied Physics A; (2023) https://doi.org/10.1007/s00339-023-06756-1
[11] M. D. K Jones et al.; Modelling Interfaces in Thin-Film Photovoltaic Devices; Frontiers in Chemistry; (2022) https://doi.org/10.3389/fchem.2022.920676
[12] R. Sellers et al.; fabrication and modeling study to reduce valence band offset in HgCdTe MWIR nBn photodetectors grown on silicon using superlattice barriers; Proc. SPIE PC12687, Infrared Sensors, Devices, and Applications XIII,; (2023) https://doi.org/10.1117/12.2677394
[13] TANG Zhenglai and CAO Bingyang ; Simulations of self-heating effects and the heat generation mechanisms in SOI-MOS devices; Microelectronics & Computer; (2023) https://doi.org/10.19304/J.ISSN1000-7180.2023.0630
[14] Kotecha et al.; Modeling Needs for Power Semiconductor Devices and Power Electronics Systems; IEDM (2019) (2019) https://doi.org/10.1109/IEDM19573.2019.8993449

DEVSIM as TCAD mobile app

DEVSIM: TCAD mobile app

Now through January 18, 2024, the TCAD app is free for download. After this, you will be entitled to any free future updates [read more...]

• App is renamed to “TCAD app”
• Impact ionization model added
• Menus updated
• Easier plot navigation
• Series resistance available to aid in impact ionization model results
• Stop simulation and keep partial results to stop long-running simulation early

 

[paper] DEVSIM

Sanchez, J. E.,

DEVSIM: A TCAD Semiconductor Device Simulator

Journal of Open Source Software, 7(70), 3898, (2022).

DOI:10.21105/joss.03898

Abstract: DEVSIM is technology computer-aided design (TCAD) software for semiconductor device simulation. By solving the equations for electric fields and current flow, it simulates the electrical behavior of semiconductor devices, such as transistors. It can be used to model existing, fabricated devices for calibration purposes. It is also possible to explore novel device structures and exotic materials, reducing the number of costly and time-consuming manufacturing iterations While DEVSIM has limited capabilities for the creation of 1-D and 2-D meshes, the Pythoninterface allows the import of mesh structures from any format using a triangular representation (in 2-D) or a tetrahedral representation (in 3-D). This makes it possible for the user to utilize high quality open source meshing solutions.

FIG: 90-nm 3-D MOSFET. The polysilicon gate (2) is surrounded by oxide (5) and two nitride regions (3) and (4). The bulk region (1) has a 120nm drawn gate length. The source and drain contacts are both 50 nm underneath the nitride regions. A body contact was placed on the bottom of the 60nm silicon region. The oxide thickness is 4.9 nm and the device is 25nm thick.

[review] TCAD Simulations of Semiconductor Piezoresistance

Takaya Sugiura, Kazunori Matsuda*, Nobuhiko Nakano

Review: Numerical Simulations of Semiconductor Piezoresistance for Computer-Aided Designs

in IEEE J-EDS, vol. 11, pp. 325-336, 2023

DOI: 10.1109/JEDS.2023.3281866

  Department of Electronics and Electrical Engineering, Keio University, Yokohama, Kanagawa, Japan

* Division of Electrical, Electronic and Infocommunications Engineering, Osaka University, Suita, Japan

Abstract: The field of piezoresistance has mainly advanced through experimental research; however, the improved accuracy of simulations and the emergence of new materials have increased the importance of simulations in this field. This review discusses the methods and current topics related to simulations of piezoresistive devices. Advancing simulation modeling will facilitate the computer-aided design of piezoresistive devices, and this review introduces the means of establishing these models by discussing the current studies on simulations and calculations in this field. Two simulation methods currently exist namely, device simulations and first-principles theoretical analysis. This review focuses on numerical simulation approaches for modeling of the piezoresistive effect using the multiphysics simulations of the mechanical and electrical behaviors of piezoresistive materials.

FIG: Basic simulation flow for studies on semiconductor piezoresistors.

[paper] Teaching Traditional TCAD New Tricks

Sanghoon Myung¹, Wonik Jang¹, Seonghoon Jin²

Myung Choe¹, Changwook Jeong¹, and Dae Sin Kim¹

Restructuring TCAD System:

Teaching Traditional TCAD New Tricks

DOI: 10.1109/IEDM19574.2021.9720616

1Data and Information Technology Center, Samsung Electronics.
2Device Lab, Samsung Semiconductor Inc.

Abstract : Traditional TCAD simulation has succeeded in predicting and optimizing the device performance; however, it still faces a massive challenge - a high computational cost. There have been many attempts to replace TCAD with deep learning, but it has not yet been completely replaced. This paper presents a novel algorithm restructuring the traditional TCAD system. The proposed algorithm predicts three-dimensional (3D) TCAD simulation in real-time while capturing a variance, enables deep learning and TCAD to complement each other, and fully resolves convergence errors.

Fig: (a) A TCAD process simulation result. (b) A prediction result of RTT process model.

(c) 1D doping concentration plot in the horizontal direction below the gate.

(d) 1D doping concentration plot in the vertical direction at the center of drain.

[paper] Charge Trapping/Detrapping in Scaled MOSFETs

Ruben Asanovski, Pierpaolo Palestri*, and Luca Selmi

Importance of Charge Trapping/Detrapping Involving the Gate Electrode on the Noise Currents of Scaled MOSFETs

IEEE TED, Vol. 69, No. 3, March 2022 1313

DOI: 10.1109/TED.2022.3147158

  

 Università degli Studi di Modena e Reggio Emilia, Modena, Italy

*Università degli Studi di Udine, Udine, Italy

Abstract: Carrier trapping/detrapping from/to the gate into dielectric traps is often neglected when modeling noise in MOSFETs and, to the best of our knowledge, no systematic study of its impacts on scaled devices is available. In this article, we show that this trapping mechanism cannot be neglected in nowadays aggressively scaled gate dielectric thicknesses without causing errors up to several orders of magnitude in the estimation of the drain current noise. The noise generation mechanism is modeled analytically and then analyzed through the use of 2-D and 3-D TCAD simulations of scaled MOSFETs with different architectures and channel/gate-stack materials. The results provide new insights for technology and device designers, highlight the relevance of the choice of the gate metal work function (WF) and the role of valence band electron trapping at high gate voltages.

Fig: (a) FinFET with the single trap location highlighted. (b) Drain current noise comparison between TCAD simulations at VGS = 0.7 V, VDS = 25 mV and single trap located as in (a).

[paper] Compact model of 3D NAND

Kul Lee and Hyungcheol Shin

Distinguishing capture cross section parameter between 

in GIDL erase compact model and TCAD

Japanese Journal of Applied Physics. 2021 Oct 14.

 
ISRC and School of Electrical Engineering and Computer Science, Seoul National University, (KR)
 

Abstract: Compact model of 3D NAND enables simulation at circuit- or system- level. Although compact model for gate-induced-drain-leakage(GIDL)-assisted erase has been proposed in previous study, it is difficult to be used practically because it has not been properly validated. In particular, capture-cross-section (CCS) value that is far from the real value is used. Also, it doesn’t consider the latest device structure and its operation. In this paper, conventional GIDL-assisted erase compact model is validated using TCAD and improved more practically. It is confirmed that CCS should be distinguished in TCAD and compact model due to their different definition in each of them. Based on their physical differences, equation that can interconvert them is proposed and the model is successfully validated with proper CCS. Finally, the advanced GIDL-assisted erase compact model considering tapered angle, single-side injection and word-line voltage is suggested.

Fig: Schematic cross section of 3D NAND string considering tapered angle. Double stacking and singe-side GIDL injection are assumed. It is assumed that the upper and lower stacks have the same dimension parameters.

[paper] NCFET CMOS Logic

Reinaldo Vega, Senior Member, IEEE, Takashi Ando*, Senior Member, IEEE,  

Timothy Philip, Member, IEEE

Junction Design and Complementary Capacitance Matching 

for NCFET CMOS Logic 

IEEE J-EDS 2021

DOI 10.1109/JEDS.2021.3095923

IBM Research, Albany, NY 12203

* IBM T.J. Watson Research Center, Yorktown Heights, NY 10598

Abstract: Negative capacitance field effect transistors (NCFETs) are modeled in this study, with an emphasis on junction design, implications of complementary logic, and device Vt menu enablement. Contrary to conventional MOSFET design, increased junction overlap is beneficial to NCFETs, provided the remnant polarization (Pr) is high enough. Combining broad junctions with complementary capacitance matching (CCM) in MFMIS (metal/ ferroelectric/ metal/ insulator/ semiconductor) NCFETs, it is shown that super-steep and non-hysteretic switching are not mutually exclusive, and that it is theoretically possible to achieve non-hysteretic sub-5 mV/dec SS over > 6 decades. In a CMOS circuit, due to CCM, low-Vt pairs provide steeper subthreshold swing (SS) than high-Vt pairs. Transient power/performance is also modeled, and it is shown that a DC optimal NCFET design, employing broad junctions, CCM, and a low-Vt NFET/PFET pair, does not translate to improved AC power/performance in unloaded circuits compared to a conventional FET reference. It is also shown that the same non-hysteretic DC design point is hysteretic in AC and may also lead to full polarization switching at higher voltages. Thus, a usable voltage window for AC NCFET operation forces a retreat from the DC-optimal design point.

Fig: Equivalent capacitance network and illustrative C-V curve showing NMOS and NC curves. CNC > CINV results in non-hysteretic switching, but low voltage gain in the off-state due to CNC >> COV. Setting CNC to CNC2, which is matched more closely to COV, results in very low SS, but also hysteretic switching as CNC2 < CINV. 

Acknowledgment: The authors would like to thank Paul Solomon and Prof. Sayeef Salahuddin for insightful discussions, as well as Synopsys for technical support.

[paper] Nano Device Simulator

Zlatan Stanojevic , Member, IEEE, Chen-Ming Tsai, Georg Strof, Ferdinand Mitterbauer, Oskar Baumgartner, Member, IEEE, Christian Kernstock, and Markus Karner, Member, IEEE

Nano Device Simulator - A Practical Subband-BTE Solver for Path-Finding and DTCO

in IEEE TED, Open Access, June 2021

DOI: 10.1109/TED.2021.3079884.

Global TCAD Solutions GmbH, 1010 Vienna

Abstract: We present an in-depth discussion on the subband Boltzmann transport (SBTE) methodology, its evolution, and its application to the simulation of nanoscale MOSFETs. The evolution of the method is presented from the point of view of developing a commercial general purpose SBTE solver, the GTS nano device simulator (NDS). We show a wide range of applications SBTE is suited for, including state-of-the-art nonplanar and well-established planar technologies. It is demonstrated how SBTE can be employed both as a path-finding tool and a fundamental component in a DTCO-flow. 

Fig: NDS simulation of a device generated using level-set topography simulation; left: level-set generated FinFET with complex warped surfaces, typical of topography simulation; the analytical doping is shown; middle: the SBTE domain is cut out of the device and meshed using an extruded grid, and mixed with the mesh of the rest of the device; cuts are then extracted from the SBTE domain and remeshed; right: electron drift velocity in the FinFET, DD versus SBTE; the SBTE result clearly shows the velocity overshoot effect not seen in the DD solution.

Acknowledgment: The authors would like to thank Dr. Edward Chen for many fruitful discussions and the continued valuable feedback.

[papers] Aging and Device Reliability Compact Modeling

IEEE International Reliability Physics Symposium

(IRPS 2021)

[1] N. Chatterjee, J. Ortega, I. Meric, P. Xiao and I. Tsameret, "Machine Learning On Transistor Aging Data: Test Time Reduction and Modeling for Novel Devices," 2021 IEEE International Reliability Physics Symposium (IRPS), 2021, pp. 1-9, doi: 10.1109/IRPS46558.2021.9405188.

Abstract: Accurately modeling the I-V characteristics and current degradation for transistors is central to predicting circuit end-of-life behavior. In this work, we propose a machine learning model to accurately model current degradation at various stress conditions and extend that to make nominal use-bias predictions. The model can be extended to track and predict any parametric change. We show an excellent agreement of the model with experimental results. Furthermore, we use a deep neural network to model the I-V characteristics of aged transistors over a wide drain and gate playback bias range and show an excellent agreement with experimental results. We show that the model is reliably able to interpolate and extrapolate demonstrating that it learns the underlying functional form of the data.

URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9405188&isnumber=9405088

[2] P. B. Vyas et al., "Reliability-Conscious MOSFET Compact Modeling with Focus on the Defect-Screening Effect of Hot-Carrier Injection," 2021 IEEE International Reliability Physics Symposium (IRPS), 2021, pp. 1-4, doi: 10.1109/IRPS46558.2021.9405197.

Abstract: Accurate prediction of device aging plays a vital role in the circuit design of advanced-node CMOS technologies. In particular, hot-carrier induced aging is so complicated that its modeling is often significantly simplified, with focus limited to digital circuits. We present here a novel reliability-aware compact modeling method that can accurately capture the full post-stress I-V characteristics of the MOSFET, taking into account the impact of drain depletion region on induced defects.

URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9405197&isnumber=9405088

[3] Z. Wu et al., "Physics-based device aging modelling framework for accurate circuit reliability assessment," 2021 IEEE International Reliability Physics Symposium (IRPS), 2021, pp. 1-6, doi: 10.1109/IRPS46558.2021.9405106.

Abstract: An analytical device aging modelling framework, ranging from microscopic degradation physics up to the aged I-V characteristics, is demonstrated. We first expand our reliability oriented I-V compact model, now including temperature and body-bias effects; second, we propose an analytical solution for channel carrier profiling which-compared to our previous work-circumvents the need of TCAD aid; third, through Poisson's equation, we convert the extracted carrier density profile into channel lateral and oxide electric fields; fourth, we represent the device as an equivalent ballistic MOSFETs chain to enable channel “slicing” and propagate local degradation into the aged I-V characteristics, without requiring computationally-intensive self-consistent calculations. The local degradation in each channel “slice” is calculated with physics-based reliability models (2-state NMP, SVE/MVE). The demonstrated aging modelling framework is verified against TCAD and validated across a broad range of VG/VD/T stress conditions in a scaled finFET technology.

URL: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9405106&isnumber=9405088

[C4P] SISPAD 2021, September 27-29

International Conference on Simulation of Semiconductor Processes and Devices

SISPAD 2021, September 27-29

The abstract submission deadline April 9th.

Two-page abstract (text and figures, A4, 10 – 12 pt, pdf) should be sent to <sispad2021@utdallas.edu>  Authors of accepted papers are requested to submit a four-page final paper which will be published in the conference proceedings. The deadline for submission of the four-page final paper is July 9, 2021.

The SISPAD conference series provides an open forum for the presentation of the latest results and trends in process and device simulation. The conference is the leading forum for Technology Computer-Aided Design (TCAD) and is held alternatingly in the United States, Japan, and Europe in September.

Original contributions are solicited for SISPAD 2021 on topics that include but are not limited to:

• Modeling and simulation of established semiconductor device, including FinFETs, GAA FETs, ultra-thin SOI devices, optoelectronic devices, TFTs, sensors, power electronic devices, and organic electronic devices.
• Modeling and simulation of emerging devices including tunnel FETs, SETs, spintronic devices, straintronic devices, bio-electronic devices, and new material-based devices for various applications
• Modeling and simulation of interconnects, including noise and parasitic effects
• Modeling and simulation of all sorts of semiconductor processes, including first principles material design, and growth simulation of nano-scale fabrication
• Advances in fundamental aspects of device modeling and simulation, including of charge, spin, and thermal transport, of collective states including spin/magnetic and charge, and of fluctuation, noise, and reliability.
• Numerical methods and algorithms, including grid generation, user-interface, and visualization
• Compact modeling for circuit simulation, including low-power, high frequency, and power electronics applications
• Process/device/circuit co-simulation in context with system design and verification, including for emerging devices
• Modeling and simulation of equipment, topography, lithography
• Benchmarking, calibration, and verification of simulators

[papers] compact/SPICE modeling

[1] M. Müller, P. Dollfus and M. Schröter, "1-D Drift-Diffusion Simulation of Two-Valley Semiconductors and Devices," in IEEE Transactions on Electron Devices, vol. 68, no. 3, pp. 1221-1227, March 2021, doi: 10.1109/TED.2021.3051552.

Abstract: A two-valley formulation of 1-D drift-diffusion transport is presented that takes the coupling between the valleys into account via a new approximation for the nonlocal electric field. The proposed formulation is suitable for the simulation of III–V heterojunction bipolar transistors as opposed to formulations that employ the single electron gas approximation with a modified velocity-field model, which also causes convergence problems. Based on Boltzmann transport equation simulations, model parameters of the proposed two-valley formulation are given for GaAs, InP, InAs, and GaSb at room temperature. Applications of the new formulation are also demonstrated. 
Code/Dataset: This article contains datasets made available via IEEE DataPort, a repository of datasets intended to facilitate analysis and enable reproducible research. Click the dataset name below to access it on the IEEE DataPort website.

[2] A. Rawat et al., "Experimental Validation of Process-Induced Variability Aware SPICE Simulation Platform for Sub-20 nm FinFET Technologies," in IEEE Transactions on Electron Devices, vol. 68, no. 3, pp. 976-980, March 2021, doi: 10.1109/TED.2021.3053185.

Abstract:We propose an experimentally validated physics-based process-induced variability (PIV) aware SPICE simulation framework–enabling the estimation of performance variation due to line-edge-roughness (LER), metal-gate-granularity (MGG), random-dopant-fluctuation (RDF), and oxide-thickness-variation (OTV) at sub-20 nm technology node devices. The framework utilizes LER, RDF, OTV, and MGG defining parameters such as fin-edge correlation coefficient (ρ), autocorrelation length (Λ), grain-size (GS), σ[EOT], etc. as the inputs, and produces IdVg distribution of ensemble size 250 as an output. We have validated the framework against 14 nm FinFET experimental data for IdVg trends as well as for the threshold-voltage (Vth), ON-current (Ion), and subthreshold slope (SS) distributions for a range of device dimensions with a reasonably good match. The worst and the best case R square errors are 0.64 and 0.98, respectively, for the validation. The very nature of the proposed framework allows the designers to use it for a vast range of process technologies. Such models are of dual importance, as it enables a PIV aware prediction of circuit-level performance, and provides a platform to estimate PIV parameters efficiently, on-par with sophisticated structural characterization tools.

[3] Blake W. Nelson, Andrew N. Lemmon, Sergio J. Jimenez, H. Alan Mantooth, Brian T. DeBoi, Christopher D. New, Md Maksudul Hossain, "Computational Efficiency Analysis of SiC MOSFET Models in SPICE: Dynamic Behavior," in IEEE Open Journal of Power Electronics, vol. 2, pp. 106-123, 2021, doi: 10.1109/OJPEL.2021.3056075.

Abstract: Transient simulation of complex converter topologies is a challenging problem, especially in detailed analysis tools like SPICE. Transistor models presented for SPICE are often evaluated by accuracy, with less consideration for the computational cost of model elements. In order to optimize models for application simulations, this research quantifies the relative simulation performance of modeling approaches and contextualizes the results with regard to accuracy. It is well established that the primary contributor to semiconductor dynamic behavior is the voltage-dependent interelectrode capacitances. Therefore, this study isolates these model components to resolve their influence on model accuracy and run-time. Both the voltage-dependencies modeled, and the mathematic formulation chosen strongly influence the accuracy of interelectrode capacitance models. In addition to these factors, the specific implementation chosen within SPICE also determines simulation performance. Through careful evaluation of these factors, this study offers specific recommendations for optimal implementations of interelectrode capacitances in SPICE.

Fig: DPT system schematic, components, and metrology.

[4] Sherif M. Sharroush & Yasser S. Abdalla; Parameter extraction and modelling of the MOS transistor by an equivalent resistance, Mathematical and Computer Modelling of Dynamical Systems, (2021) 27:1, 50-86, DOI: 10.1080/13873954.2020.1857790

Abstract: During the analysis of multi-transistor circuits, the need arises to evaluate the time delay or the power consumption of the circuit. Due to the complexity of the transistor model, several complicated equations arise from which a compact-form solution cannot be obtained and a suitable physical insight cannot be drawn. With this regard, two contributions are presented in this paper. The first one is a fully analytical parameter extraction approach to be applied on the MOS transistors. The second one is a quantitative method for simplifying the analysis of MOS circuits by modelling the MOS transistor by a suitable equivalent resistance adopting the time-delay or the power-consumption equivalence criteria. The parameter-extraction method is verified by using the extracted parameters in the derived expressions according to the second contribution. Compared to other representations, the agreement of the proposed model with the simulation results is very good.

Fig: Finding Vthn0 as the intercept of the linear portion of the Id-Vgs characteristics with the horizontal axis. The curve corresponds to Vds=1V. The term ‘exact relationship’ means data from the simulation results

[DAY 2] 1st Asia/South Pacific MOS-AK Workshop

Arbeitskreis Modellierung von Systemen und Parameterextraktion

Modeling of Systems and Parameter Extraction Working Group

1st Asia/South Pacific MOS-AK Workshop

(virtual/online) FEB. 25-26, 2021

Day2: FEB.26
Session C Chair: Sadayuki Yoshitomi, Kioxia (J)

[8] eSim: An open source CAD software for circuit simulation
Kannan Moudgalya
IIT Bombay (IN)

[9] A modular approach to next generation Qucs
Felix Salfelder and Mike Brinson
QUCS Team; Centre for Communications Technology, London Metropolitan University (UK)

[12] Machine learning-based approach to model and analyze GaN power devices
Tian-Li Wu
National Yang Ming Chiao Tung University, Taiwan (TW)

[11] TCAD-inspired compact modeling approach
Sung-Min Hong and Kwang-Woon Lee
Gwangju GIST (KR)

Session D Chair: Sheikh Aamir Ahsan, NIT Srinagar (IN)
[10] An Innovative Technique for Ultrafast Carrier Dynamics and THz Conductivities of Semiconductor Nanomaterials
Praveen Kr. Saxena and Fanish Kr. Gupta
Tech Next Lab, Lucknow (IN)

[13] Compact Modeling of 3D NAND Flash Memory for Diverse Unconventional Analog Applications
Shubham Sahay
IIT Kanpur (IN)

[14] Steep Subthreshold Slope PN-Body Tied SOI-FET for Ultralow Power LSI, Sensor, and Neuromorphic Chip
Takayuki Mori and Jiro Ida
Kanazawa Institute of Technology, Nonoichi (J)

[Pic] Group photo of selected MOS-AK participants attending 2nd Day of the workshop

[DAY 1] 1st Asia/South Pacific MOS-AK Workshop

Arbeitskreis Modellierung von Systemen und Parameterextraktion

Modeling of Systems and Parameter Extraction Working Group

1st Asia/South Pacific MOS-AK Workshop

(virtual/online) FEB. 25-26, 2021

DAY 1: FEB. 25, 2021
Session A Chair: Usha Gogineni, ams AG, Hyderabad (IN)

[1] New Insights in Low Frequency Noise Characteristics in PE-BJTs
Peijian Zhang and Ma Long
Science and Technology on Analog Integrated Circuit Laboratory; WHU (CN), Keysight Technologies (US)

[2] Direct white noise characterization of short-channel MOSFETs
K. Ohmori and S. Amakawa
DeviceLab, Tsukuba (J)

[3] SPICE Modeling of 2D-material based FETs with Schottky-barrier contacts
Sheikh Aamir Ahsan
Nanoelectronics Research and Development Group, NIT Srinagar, Jammu and Kashmir (IN)


[4] Physics-based model of SiC MOSFETs including high voltage and current regions
Sourabh Khandelwal, Cristino Salcines, and Ingmar Kallfass
Macquarie University Sydney (AU), University of Stuttgart (D)

Session B Chair: Daniel Tomaszewski, IMiF, Warszaw (PL)
[5] Compact Modeling for Gate-All-Around FET Technology
Avirup Dasgupta
IIT Roorkee (IN)


[6] BSIM-HV: Advanced High Voltage MOSFET Compact Model
Harshit Agarwal
IIT Jodhpur (IN)

[7] ASCENT+ Transnational Access for the nanoelectronics
Georgios Fagas
Tyndall (IE)

[Pic] Group photo of selected MOS-AK participants attending 1st Day of the workshop

[C4P] New simulation methodologies for next-generation TCAD

Call for Papers for a Special Issue of

IEEE Transactions on Electron Devices on

"New simulation methodologies for next-generation TCAD" 

Submission deadline: February 28, 2021 

Publication date: November 2021

Technology Computer Aided Design is used to simulate semiconductor processes and devices,a field which has become increasingly complex and heterogeneous. Processing of integrated circuits requires nowadays over 400 process steps, and the resultant devices often have a complicated 3D structure and contain various materials. The full device behavior can only be understood by considering effects on all length scales from atomistic (interfaces, defects etc.) over nanometric (quantum confinement, non-bulk properties etc.) to full chip dimensions (strain, heat transport etc.), and time scales from femtoseconds to seconds. Voltages, currents and charges have been scaled to such low levels that electronic noise, statistical effects and process variations have a strong impact. Devices based on new materials (e.g. 2D crystals) and physical principles (ferroelectrics, magnetic materials, qubits etc.) challenge standard TCAD approaches. While the simulation methods developed by the physics community can describe the basic device behavior, they often lack important simulation capabilities like, for example, transient simulations or integration with other TCAD tools and are too slow for daily use. Due to the complexity of semiconductor technology, it becomes more and more difficult to assess the impact of a change in processing or device structure on circuit performance by looking at a single aspect of an isolated device under idealized conditions. Instead a TCAD tool chain is required that can handle realistic device structures embedded in a chip environment. New methodologies are required for all aspects of TCAD to ensure an efficient tool chain covering from atomistic effects to circuit behavior based on flexible simulation models that can handle new materials, device principles and the ensuing large-scale simulations.

This Special Issue of the IEEE Transactions on Electron Devices will feature the most recent developments and the state of the art in the field of TCAD for processing and for device behavior with a focus on new methodologies that improve the tool chain. Papers must be new and present original material that has not been copyrighted, published or accepted for publications in any other archival publications, that is not currently being considered for publications elsewhere, and that will not be submitted elsewhere while under considerations by the Transactions on Electron Devices.

Topics of interest include, but are not limited to:
• Artificial Intelligence applied to TCAD

• TCAD device models for
• new materials (2D materials, oxides, organic semiconductors, oxide semiconductors,
nanowire devices etc.)
• new device types (magnetic devices, memristors, spintronics, qubits, sensors etc.)
• physical effects (ferroelectric dielectrics, thermal transport at nanoscale, atomistic
simulation etc.)
• simulation conditions that push the limits of standard TCAD: ballistic transport, THz
frequencies, cryogenic conditions, device degradation, electromagnetic and plasma
waves in active devices, transient simulations, noise and fluctuations, microscopic 
simulation of large power devices

• Process simulation

• Atomistic process simulation to generate structures for atomistic device simulations
(including both interconnects and transistors)
• Gate stack modeling including dipole diffusion
• Stress simulation for nanosheet and forksheet devices and stress simulations
including layout effects
• Topological simulation
• Equipment simulation

• New methods for the TCAD tool chain

• Self-consistent integration of simulation models into the hierarchy
• Device-circuit interaction
• Multi-physics and multi-scale integration
• Efficient use of the data produced along the chain
• Workflow improvements
• Methods that improve the turn-around-time for TCAD simulations

Submission instructions: Manuscripts should be submitted in a double column format
using an IEEE style file. Please visit the following link to download the templates:
http://www.ieee.org/publications_standards/publications/authors/author_templates.html
In your cover letter, please indicate that your submission is for this special issue.

Guest Editors:

1. Prof. Fabrizio Bonani, Politecnico di Torino, Italy
2. Dr. Stephen Cea, Intel Corp., USA
3. Prof. Elena Gnani, University of Bologna, Italy
4. Prof. Sung-Min Hong, GIST, Republic of Korea
5. Dr. Seonghoon Jin, Samsung, USA
6. Prof. Christoph Jungemann, RWTH Aachen, Germany
7. Prof. Xiaoyan Liu, Peking University, China
8. Dr. Victor Moroz, Synopsys, USA
9. Dr. Anne Verhulst, imec, Belgium